1/4

Intelligent Semiconductor
System Lab.


Switching propertied of MOSFETS
2/4
1. nFET Pass Transistors

2. pMOS Transmission Characteristics

3. The Inverter Revisited

4. Series-Connected MOSFETs

5. Transient Modelling

6. MOSFET Switch Logic
CONTENTS
4.1. nFET Pass Transistors
The input has volatage V
IN
and the output is connected to capacitive load
C
OUT
that has voltage across it


V
G
= Apply high voltage(=V
DD
) for nFET into conduction mode


Examine two condition

- VIN = 0 (= Low Voltage)
- VIN = 1 (= High Voltage)
4.1.1 Logic 1 Input
Logic 1 = V
DD

()
=>

>

2
=

0 = 0

= (

)
t/2
n
1+ t/2
n

)
=

Problem nFET pass transistor

1. The charging if the output capacitor is described by time dependence(t/2
n
) and slowly level out
=> V
out
(t) increases in time both of the device bias voltage decrease with time

=> A decreasing value of V
GSn
reduces the channel charge density, while a smaller V
DSn
indicates a reduction in the
drain-source electric field

# nFET is difficult to pass a logic 1 volatge
4.1.1 Logic 1 Input
Problem nFET pass transistor

2. The nFET cannot pass the power supply voltage V
DD
from drain to
source
=> In time

=> In order to maintain conduction through the device, the gate-source
voltage must have a minimum value of min

to
maintain the inversion layer
max

min

=> This is called Threshold Voltage Loss
Adding body bias effect

=
0
+ 2

Maximum value of the output voltage

0
+ 2

= (

0
) 2

Conculsion

The two characteristics of slow logic 1 transfers and the threshold voltage loss can be critical factors
when using nFETs as pass transistors in high-speed circuit design.
4.1.1 Logic 1 Input
Example 4.1
Consider an n-channel pass transistor that is connected as shown in Figure 4.2(a). We will assume
device parameter value of
0
= 0.7, 2

= 0.58, = 0.0053
1
2
. With

= 3.3 applied to the gate, the

maximum voltage that can be passed is calculated from

= 3.3 0.7 0.0053 0.58 +

0.58
= 2.6 0.0053 0.58 +

0.58

1. Guess a value for

2. Calculate the right-hand side (RHS) of the equation
3. If the RHS is equal to the original guess for

then we have the solution

4. Otherwise, use the RHS as the new guess, and redo the calculation starting at step 2








Solution : V
out
= 2.55V

4.1.2 Logic 0 Input
Logic 0 =GND

Initially charged V
DD

the maximum value of

occurs at the beginning of the

discharge.

is always maintained, so that the nFET is always

non-saturated.

Discharging event
=

2
[2

2
]
<= the current flow is out of the positive terminal

2
=

= (

)
2

1+

Important notes
1. Discharging speed show a rapid exponential decay
2. the nFET has a constant gate-source bias is of

so that it remains active through out the entire discharge.

3. The nFET can pass the 0v input voltage without any problems, and that the discharge is fast.
4.1.3 Switching Times
1.

the low-to high time

between the voltage levels 0v and

= 0.9

= 2

1
1

1 <= substituting

= 0.9

= 18

2.

The high-to-low time

between the voltage levels

and

= 0.1

= 2

()
1 <= substituting

= 0.1

= ln 19

2.94

3.

The discharge is much faster than charging event

18
2.94
6.11
Combined with the threshold voltage loss, the nFET acts well to pass a strong
logic 0 voltages
circuits that require a logic 1 voltage transmission through an nFET may cause a
slowdown in the logic throughput
4.1.4 Interpretation of the Results

: gate drain or gate source cap

-

: junction drain-bulk or source bulk cap

-

: the external load cap

-

, internal FET cap

4.1.4 Interpretation of the Results

)

=

=
,
+
,

,
: charging time needed for internal parasitic capacitor
:
,
=

,
: additional time needed to charge external load
:
,
=

)

1.

case : use a large aspect ratio (W/L) to decrease the FET resistance and speed up the transfer
2.

case : increasing the aspect ratio has less effect on shrinking the time constant
4.1.5 Layout
RC equivalent network analysis
Resistor
=
1

)
, where =

the gate overlap

Capacitor

1
2

,
=

0,

0
+

0,

+ +

,
=

0,

0
+

0,

( + +

=
,
+

=
,
+
1
2

=
,
+

=
,
+
1
2

the right (load) side since the voltage there never
exceeds

if the left side is driven by an inverter, then

should be replaced by

in the

equation to be
consistent.
4.2 pMOS Transmission
Characteristics
The pFET is the electrical complement of the nFET
it behaves in exactly the opposite manner when passing low and high
voltages.

Examine two condition

- VIN = 0 (= Low Voltage)
- VIN = 1 (= High Voltage)

4.2.1 Logic 0 Input
Initial condition

= 0

= 0 =

Terminal voltage

>

|
- pFET capacitor discharge equation
=

2
<=

0 =

1 +t/2
p

)
=

4.2.1 Logic 0 Input
Problem pFET pass transistor

- For large times t

the pFET must maintain a source-gate voltage off or the
conducting channel to exist.
=>the smallest voltage that can be supported by the pFET at
the output node is |

| corresponding the to minimum

source-gate voltage.
Adding body bias effect

= |
0
2

|

Conclusion
- the pFET transistor can only pass a weak logic 0 since it can never reach 0v.
- Minimum voltage cannot reach 0V
4.2.2 Logic 1 Input

0 =

the pFET is at the border between saturation and non-saturation.

- Capacitor charge event

> 0

increase in time. Thus, for times t > 0, and the pFET conducts
in the on-saturated mode.

= = |

|
=

2
2

2

=
2

()
|

|
2

1 +

a p-channel MOSFET can pass a strong logic 1 voltage without any problems.
4.2.3 Switching Times
.

vs

= 18

= ln 19

2.94

18
2.94
6.11
exactly the inverse of the ratio for the nFET

4.3 The Inverter Revisited
1. the nFET passes a strong logic 0, while the pFET passes a strong logic 1. This connection insures that the output
can attain a full-rail output voltage swing.
2. The input variable x acts as the MUX control signal, and determines which input is sent to the output.
= 1 + 0
=

4.4.1 nFET Chains
Case 1 :

= 0
- nFET strong pass 0 signal
- 0

= 0

Case 2 :

- nFET weak pass 1 signal and has threshold voltage loss
- max

- max

is acting as the input to MnB, and can never exceed

because of drop induced by MnA. The same argument

may be applied to the third FET MnC. This says that only one threshold loss occurs in a series connected chain
-

4.4.2 pFET Chains
Case 1 :

- pFET strong pass V
DD
signal
-

Case 2 :

= 0
- pFET weak pass 0 signal and has threshold voltage loss
-

= |

|
- min

= |

|
-

must be at least |

| to maintain a conducting channel. due to the threshold limitation on MpA, the second
FET MpB receives an input that never drops below anyway.
- 0

= |

= |

= 0

4.4.3 FETs Driving Other FETs
-1. nFET drive
-2. pFET drive
Connecting nFETs in this manner induces one threshold drop per transistor, resulting in a large reduction in the logic 1
voltage
Connecting pFETs in this manner induces one threshold rise per transistor, resulting in a large increase in the logic 0
voltage
- They do have the advantage that they are relative stable voltage values and are sometimes useful for reference devices
4.5.1 The MOSFET RC Model

Non-linear model
LTI model
convert


Equivalent resistor
=
1
(

)
=

Equivalent capacitor

1
=
1
2

+
1

2
=
1
2

+
2

1,2

,
1,2
=
4.5.1 The MOSFET RC Model
Transit analysis

- Initial condition

- Output capacitor voltage

=

- Transit time
= ln
1
1

- Charging time (0V to 90% voltage V
DD
)

= ln 10 2.3
- Initial condition

1

- Output capacitor voltage

- Transit time
= ln

- Discharging time (V
DD
to 10% V
DD
)

= ln 10 2.3
4.5.1 The MOSFET RC Model
Problem RC model
Ignore threshold voltage loss
the asymmetry of the MOSFET with regard to
logic 0 and logic 1 transfer times is still
ignored by the analysis

4.5.2 Voltage Decay On an RC Ladder
- Capacitor discharging

1
: discharge through
1

2
: discharge trough series resistor
1
,
2


- Voltage change
2
()

- Time constant decay for the decay

1

1
+
1
+
2

2

4.5.2 RC Ladder Analysis
Node 1 Node 2
- Node Equation
- Node 1

=

1

2

1

2


- Node 2

=

2

1

2

- Laplace transform

1
+
1

1
0 =

!

1

2

2
+
2

2
0 =

2

1

2

- Matrix form

1
+
1

1
+
1

2

1

2

2
+
1

2
()
=

1

- Determinant of matrix
=

1
+
1

1
+
1

2

1

2

2
+
1

2

4.5.2 RC Ladder Analysis
- Matrix form

1
+
1

1
+
1

2

1

2

2
+
1

2
()
=

1

- Determinant of matrix
=

1
+
1

1
+
1

2

1

2

2
+
1

2

- Cramers rule

1
=
1

2
+
1

2
=
1

1
+
1

1
+
1

2

1

2

2

- Pole figure out

1
+
1

1
+
1

2

1

2

2
+
1

2
= 0

=
1

2

2
+ + = 0
=
1

1
+
1

2
+
1

1

=
1

2

-
1
,
2

2
+ + = 0

1
=

2
+
1
2

2
4

2
=

1
2

2
4

1
+
2
=

2
=
4.5.2 RC Ladder Analysis
Case 1 :
1

2

to identify the roots, we will assume
1
<
2


- Find
1

1
2
+
1
+ = 0 <=
1
1

1
+ 0

1

1
+
2


- Find s
2

2
2
+
2
0 <= both the square and the linear terms are large compared to the constant c in the quadratic equation

2


1

2
+
1

1
<= s
2
is more negative than s
1


Case 2 :
2

1

2

1

1

4.5.2 RC Ladder Analysis

2
=
(1/C
1
C
2
)
(
1
)(
2
)

1

+
2

1
+
1

2
+

2
=

1
(+
1
)
+

2
(+
2
)
<= partial fraction extension

2
=
1

+
2

() <=s1 and s2 are negative value

2
=
1

1

+
2

2

() <=the dominant root that determines the transient response is s
1

2

1

1

<=
1
=

(
1

2
)

1
+

2
1

1
1

1
+
1

2
+

2
1

2
= V
MAX

s
2
s
1
s
2

s
2
s
1
s
2

- Compare with ideal decay

= ,

() =

1
=
2
(

s
2
s
1
s
2

=
(
1

+ln

1

2
)
=
1



4.5.2 RC Ladder Analysis
- Figure out

+ln

1

2
= 1 <= ln
1

1
1

1
+
1

1
=

1
+
2

=
1

2
(
1

1
+
1

2
+
1

1
)
=
2

2
+
1

1
+
1

2

=
1

1
+
2
(
1
+
2
)

2
=
1

= K
1
e

<=
1
=
1

1
+
2
(
1
+
2
)

4.5.2 RC Ladder Extension to Longer RC Chains
- Charging case

- Discharging case

=1

=1


4.5.2 RC Ladder Extension to Longer RC Chains
Example 4-2




=
4

1
+
2
+
3
+
4
+
3

1
+
2
+
3
+
2

1
+
2
+
1

1



Charging

4

[1 +

]

Discharging

4

4.5.2 RC Ladder Application to FET Chains
Limitation RC ladder
It does not include the threshold voltage modification through the chain;
The linearized resistance of a MOSFET is at best a crude approximation; and
The capacitances are assume to all have the same initial condition as the final
capacitor at the end of the chain.
Biggest problem of accuracy
modelling the voltage using an exponential time function greatly oversimplifies
the operation of the circuit
nFET

10

1

<= discharging approximate reasonable

01

1
t/2
n
1+ t/2
n

<= this is much slower than RC ladder approximation
pFET

01
V
1
1

<= charging approximate reasonable

10

1+

2

<= this is much slower than RC ladder approximation

4.5.2 RC Ladder Application to FET Chains

1

,
- Resistor
=
1

= +2
0

- Capacitor
- Gate source, gate drain capacitor

1
2

- Junction capacitor

0,

0
+

0,

+ +

0,

0
+2

0,

+ +2

0,

0
+2

0,

+ + 2

- Equivalent capacitor

4.5.2 RC Ladder Application to FET Chains
4.6 MOSFET Switch Logic
nFET Pass Transistors
G = 1 : A -> B
B = A*G
pFET Pass Transistors
G = 0 : A -> B
B = A*

4.6.1 Multiplexor Networks
Input data
Select signal
2:1 MUX basic operation

=
0

+
1

nFET 2:1 MUX
pFET 2:1 MUX

Weak VDD signal

Weak GND signal
S
S
D0
D1
Y S
Only need 4 TR
4.6.1 Multiplexor Networks+a
g = 0, gb = 1
a b
g = 1, gb = 0
a b
0 strong 0
Input
Output
1
strong 1
g
gb
a
b
a b
g
gb
a b
g
gb
a b
g
gb
g = 1, gb = 0
g = 1, gb = 0
4.6.1 Multiplexor Networks
4
4
D1
D0
S
Y
4
2
2
2
Y
2
D1
D0
S
S
D0
D1
Y
S
D0
D1
Y
0
1
S
Y
D0
D1
S
S
S
S
S
S
Use a lot of Transistor
4.6.1 Multiplexor Networks
Pull up network
Pull down network