Transistor Physics

IHP
Im Technologiepark 25
15236 Frankfurt (Oder)
Germany
IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com 2005 - All rightsreserved
Physics of Metal Oxide Semiconductor
Field Effect Transistors
(MOSFET`s)
Thomas Schrder
The MOS structure discussed up to now is a two terminal system
but the MOSFET transistor is a four terminal device:
How does the transistor switch ?
This four terminals are source, substrate, gate and drain electrodes
most simple working mode of a n-channel MOSFET:
Source and substrate are on the same potential
drain potential V
D
more positive than source
to attract electrons
Transistor is switched on when gate voltage V
G
is
sufficiently positive to invert the channel
2
( )/ ( )/
( )
V V
i D t D t
i
A
n
n x e ne
N

= =
( ) 2
s F D
inv V = +
Equilibrium Non-equilibrium
MOS structure under equilibrium
and non-equilibrium condition
gate voltage V
G
applied;
drain voltage V
D
not applied;
gate voltage V
G
applied;
drain voltage V
D
applied;
As the positive drain voltage takes over electrons,
the electron concentration is lowered under
applied V
D
in the vicinity of the drain electrode
In order to invert the channel under applied V
D
,
a higher surface band bending (higher V
G
) is required
Drain current characteristics of a MOSFET device
V
G
> V
T
; V
D
small: linear region
inversion layer charge is induced uniformly in the channel;
current flows from source to drain through conducting channel;
channel acts as resistor and drain current
increases proportional to drain potential
V
G
> V
T
; V
D
= V
D Sat
: onset of saturation
inversion charge near drain decreases until it becomes zero
close to drain region
V
D
at which this happens is called pinchoff
drain current starts to saturate
V
G
> V
T
; V
D
> V
D Sat
: saturation
pinchoff moves towards source leaving behind a depleted region;
inversion charge drifts down conducting channel and
is then injected in depletion region;
I
D
will essential remain constant because
inside channel potential is fixed at V
D Sat
Drain current characteristics of a MOSFET device
V
G
> V
T
; V
D
small: linear region
inversion layer charge is induced uniformly in the channel;
current flows from source to drain through conducting channel;
channel acts as resistor and drain current
increases proportional to drain potential
V
G
> V
T
; V
D
= V
D Sat
: onset of saturation
inversion charge near drain decreases until it becomes zero
close to drain region
V
D
at which this happens is called pinchoff
drain current starts to saturate
V
G
> V
T
; V
D
> V
D Sat
: saturation
pinchoff moves towards source leaving behind a depleted region;
inversion charge drifts down conducting channel and
is then injected in depletion region;
I
D
will essential remain constant because
inside channel potential is fixed at V
D Sat
Typical MOSFET characteristics:
( ) ( )
d n
J qn x v qn x = =

Q Q /
D I n I n
I W W V y = =
0
Q ( )
X
I
I
qn x dx =
On state current characteristics of a MOSFET device

Starting point: current density x: from the surface in the bulk
y: along the channel
mobility
electron concentration
electric field
Current equation
charge
channel width
Inversion layer charge
Current continuity for each distance dy x: from the surface in the bulk
gate voltage
semiconductor charge
Band bending tight to strong inversion condition
0 0
Q ( )
y V
D n I
I dy W y dV =

Depletion approximation to calculate inversion charge Q
I
:
Q ( ) Q ( ) Q ( ) [ ( )] Q ( )
I S D i G s D
y y y C V y y = =
depletion charge
insulator capacitance
in inversion
band bending
( ) 2 ( )
s F
y V y = +
Q 2 [2 ( )]
D A m s A F
qN w qN V y = = +
Depletion charge in depleted area:
Putting the last two expressions in the formula of Q
I
:
and integrate current continuity until drain (y=L; V=VD) results in complex equation:
Simplification 1: gradual channel approxiamtion:
V
D
smaller than two times Fermi potential:
I
Q ( ) [ 2 ( )] 2 [2 ( )]
i G F s A F
y C V V y qN V y = +
{
( 2 / 2 )
D n i G F D D
W
I C V V V
L
=
}
3 / 2 3 / 2
2 2
[ ( 2 ) ( 2 ) ]
3
s A
F D F
i
q N
V
C

+
( /2)
D n i G T D D
W
I C V V V V
L
=
The treshold voltage is given by:
and factor K (characteristic ratio of semiconductor and insulator capacitance) is given by:
The current equation can be understood than as follows:
( /2)
D n i G T D D
W
I C V V V V
L
=
2 2
2 2 2
s A F
T F F t F
i
qN
v K
C

= + = +
Band bending term
2 /
/
2
s A t
s D
i i
qN
L
K
C C

= =
Thermal voltage
potential across dielectric
Induced by depletion charge
An average Q
I
across the channel at an average potential V
D
/2
factor V
D
/ L is average electric field
Dsat G T
V V V =
2
( )
2
G T
Dsat n i
W V V
I C
L

=
( /2)
D n i G T D D
W
I C V V V V
L
=
The drain current characteristic of MOSFET`s:
I
D
increases linearly with V
D
until it levels of at V
DSat
:
The saturated drain current then reads:
The central message of transistor physics:
The figure of merit of the performance of a transistor is the drain current.
The higher the drain current, the quicker the load of the circuit is charged or discharged.
High speed electronics relies on transistors with high drain current
( /2)
D n i G T D D
W
I C V V V V
L
=
Be the electric engineer: Raise the drain current of the MOSFET device !
Strategy 1: Keep supply voltage V high
indeed stays as high as long as possible
Drawbacks:
a) low power for mobile devices
b) electric breakdown of highly scaled electronics
( /2)
D n i G T D D
W
I C V V V V
L
=
Strategy 2: Raise the channel width W:
Drawbacks:
In conventional planar MOSFET technology this approach is not useful as it costs chip area
New promising device concept : Multiple gate transistors
( /2)
D n i G T D D
W
I C V V V V
L
=
Strategy 3: Raise the carrier mobility :
Source : IBM
Important technology trends:
Strained Si technology
Si
1-x
Ge
x
channels
( /2)
D n i G T D D
W
I C V V V V
L
=
Strategy 4: Transistor Scaling reduces channel length L:
Primary means of microelectronic engineers !!!
The philosophy in
microelectronic
industry relies
on engineering
and not on the
integration of
new materials !!!
( /2)
D n i G T D D
W
I C V V V V
L
=
Primary means of microelectronic engineers !!!
However, if planar conventional planar MOSFET technology is kept, further scaling
requires integration of new materials
Reason:
Scaling reduces transistor area A and therefore the insulator capacitance C
i
:
C
i
= k A / d
This was counterbalanced over the last 40 years by reducing the insulator thickness d
( /2)
D n i G T D D
W
I C V V V V
L
=
~ 1.2 nm
Source: Intel Corporation
The SiO
2
thickness in the state-of-the art MOSFET technology is just 1 to 1.5 nm.
Further thickness reduction of the insulator results in unacceptable high leakage currents
on the order of 1 A / cm
2
due to the quantum mechanical tunneling effect.
Interesting example how quantum mechanics triggers technology developments
( /2)
D n i G T D D
W
I C V V V V
L
=
Materials science apporach to keep planar MOSFET technology:
Replace SiO
2
by an insulator of higher static permittivity k
C
i
= k A / d
In this way, same capacitance can be achieved with reasonable oxide thickness (low leakage currents)
Source: Intel Corporation
( /2)
D n i G T D D
W
I C V V V V
L
=
Strategy 5: Integrate high-k gate oxides to raise C
i
:
Alternative dielectrics discussed in literature:
Polycrystalline
none
Epitaxial
SrTiO
3
Y
2
O
3
Pr
2
O
3
etc.
Amorphous:
Al
2
O
3
Hf-Silicates
Pr-Silicates
etc.
HfO
2
ZrO
2
TiO
2
( /2)
D n i G T D D
W
I C V V V V
L
=
i
:
Important requirements for high-k dielectrics:
none
Good breakdown characteristics:
time dependent breakdown
Reasonable k - value:
k about 15 to 30
Low leakage currents:
Band offset of at least 1 eV
( /2)
D n i G T D D
W
I C V V V V
L
=
i
:
Important requirements for high-k dielectrics:
4) Inversion layer mobility
a) Coulomb scattering due to fixed
charges in the dielectric
b) Coulomb scattering due to
ionized atoms in depletion layer
c) Quantization of inversion charge
results in lower effectiv electric fields
d) Surface roughness, phonon
scattering, interface traps

Transistor Physics

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