Chip Synthesis Workshop 1392

Table of Contents
31833-000-S16B i Synopsys Chip Synthesis Workshop

Day 1: Pre-Synthesis Processes
Introduction & Overview
Workshop Goal.................................................................................................................. i-3
Workshop Prerequisites...................................................................................................... i-4
Workshop Target Audience ................................................................................................ i-5
Workshop Agenda.............................................................................................................. i-6
Unit 1: Introduction to Synthesis
Unit Objectives .................................................................................................................. 1-2
Just What Is Synthesis? .................................................................................................. 1-3
Synthesis is Constraint-Driven............................................................................................ 1-7
Synthesis is Path-Based...................................................................................................... 1-8
Chip Synthesis Process ..................................................................................................... 1-9
Design Compiler Interfaces............................................................................................... 1-10
Need Help? .................................................................................................................... 1-11
Search in Acrobat Reader ................................................................................................ 1-12
Module Synthesis Roadmap............................................................................................. 1-13
Analyze, Elaborate - Read................................................................................................ 1-14
Unit 2: Setup, Libraries, and Objects
Chapter Overview.............................................................................................................. 2-3
Synthesis Review............................................................................................................... 2-4
Technology Library............................................................................................................ 2-5
Target Library.................................................................................................................... 2-6
Link Library Variable ......................................................................................................... 2-7
Use link to Resolve Design References ............................................................................... 2-9
The search_path Variable ................................................................................................. 2-10
Design Compiler Interfaces............................................................................................... 2-13
Design Compiler Three Initialization Files.......................................................................... 2-14
.synopsys_dc.setup File: Example..................................................................................... 2-15
.synopsys_dc_setup: Tcl and dcsh Mode.......................................................................... 2-16
Design Objects: VHDL Perspective.................................................................................. 2-18
Design Objects: Verilog Perspective ................................................................................. 2-19
Table of Contents
31833-000-S16B ii Synopsys Chip Synthesis Workshop
Design Objects: Schematic Perspective............................................................................. 2-20
Multiple Objects with the Same Name.............................................................................. 2-21
The get Command............................................................................................................ 2-22
What Is a List?................................................................................................................. 2-23
Other Handy List Commands........................................................................................... 2-25
Finding objects with dc_shell-t.......................................................................................... 2-26
Appendix - Synopsys DesignWare................................................................................... 2-32
Unit 3: Partitioning for Synthesis
What is Partitioning?........................................................................................................... 3-3
Why Partition a Design? .................................................................................................... 3-4
Partitioning Within the HDL Description.............................................................................. 3-5
Eliminate Unnecessary Hierarchy........................................................................................ 3-6
No Hierarchy Dividing Combinational Paths........................................................................ 3-7
Partition at Register Boundaries .......................................................................................... 3-9
Avoid Glue Logic: Example .............................................................................................. 3-10
Balance Block Size With Run Times ................................................................................. 3-12
Separate Core Logic, Pads, Clocks, and JTAG................................................................ 3-14
Partitioning Within Design Compiler.................................................................................. 3-15
The group Command ....................................................................................................... 3-16
The ungroup Command.................................................................................................... 3-17
Partitioning Strategies for Synthesis................................................................................... 3-19
Unit 4: Coding for Synthesis
The Importance of Quality of Source .................................................................................. 4-3
RTL Coding Guide............................................................................................................. 4-4
The Big Picture: Think Hardware! ...................................................................................... 4-5
The Big Picture: Think Synchronous! ................................................................................. 4-6
The Big Picture: Think RTL! .............................................................................................. 4-7
RTL Synthesis Cookbook.................................................................................................. 4-8
Synthesis of if Statements............................................................................................... 4-9
if-else Statements............................................................................................................. 4-10
if Statements and Latches ................................................................................................. 4-12
if-then-elseif Statements.................................................................................................... 4-13
Priority Interrupt Circuit - Synthesis Results ...................................................................... 4-15
Table of Contents
31833-000-S16B iii Synopsys Chip Synthesis Workshop
When NOT to Use if-then-elseif ...................................................................................... 4-16
Synthesis of case Statements........................................................................................... 4-17
case Statements .............................................................................................................. 4-18
Synthesis of loop Statements ............................................................................................ 4-25
Unrolling Loops ............................................................................................................... 4-26
Tradeoffs with Loops....................................................................................................... 4-27
Hardware Result .............................................................................................................. 4-28
Recoded Loop................................................................................................................. 4-29
Synthesis of Flip-Flops..................................................................................................... 4-30
Inferring Sequential Devices.............................................................................................. 4-31
Synthesis of Arithmetic Circuits......................................................................................... 4-34
Inferring Arithmetic Parts.................................................................................................. 4-35
DesignWare Arithmetic Resources.................................................................................... 4-36
DesignWare Implementation Selection.............................................................................. 4-37
Implying a Structure by Operand Placement...................................................................... 4-39
Verilog Preprocessor Directive ......................................................................................... 4-41
Appendix: Verilog Inference and Instantiation.................................................................... 4-44

Day 2: Constraining the Design
Unit 5: Timing and Area
RTL Block Synthesis.......................................................................................................... 5-3
Specifying an Area Goal..................................................................................................... 5-4
Timing Goals: Synchronous Designs.................................................................................... 5-5
Defining a Clock ................................................................................................................ 5-7
Defining a Clock in Design Compiler................................................................................... 5-8
Timing Goals: Synchronous Designs, I/O............................................................................. 5-9
Constraining the Input Paths ............................................................................................. 5-10
set_input_delay: Effect on Input Paths............................................................................... 5-13
Constraining Output Paths of a Design.............................................................................. 5-14
set_output_delay: Effect on Output Paths.......................................................................... 5-17
Useful Commands............................................................................................................ 5-19
Unit 6: Environmental Attributes
Table of Contents
31833-000-S16B iv Synopsys Chip Synthesis Workshop
Constraining for TimingWhats Missing? ........................................................................ 6-4
Describing Environmental Attributes.................................................................................... 6-5
Modeling Capacitive Load ................................................................................................. 6-6
set_load examples.............................................................................................................. 6-7
Modeling Input Drive Strength............................................................................................ 6-8
set_driving_cell Examples .................................................................................................. 6-9
Variations in cell delays .................................................................................................... 6-10
Operating Conditions ....................................................................................................... 6-11
Net delays ....................................................................................................................... 6-14
What is a Wire load model? ............................................................................................ 6-15
Specifying Wire Loads in Design Compiler ....................................................................... 6-17
Wireload Model Mode .................................................................................................... 6-18
Check Your Constraints .................................................................................................. 6-19
Appendix - Create an Operating Condition....................................................................... 6-25
Unit 7: Time and Load Budgeting
Time Budgeting.................................................................................................................. 7-4
Load Budgeting.................................................................................................................. 7-8
Summary of Describing Constraints.................................................................................. 7-14
Unit 8: Timing Analysis
Does Your Design Meet its Goals?..................................................................................... 8-3
Timing Analysis: What Tool Do I Use? .............................................................................. 8-4
Static Timing Analysis......................................................................................................... 8-5
Timing Paths in Design Compiler......................................................................................... 8-6
Organizing Timing Paths Into Groups .................................................................................. 8-7
Schematic Converted to a Timing Graph........................................................................... 8-10
Components of Static Timing Analysis .............................................................................. 8-11
How DesignTime Calculates Delays ................................................................................. 8-12
Non-Linear Delay Model ................................................................................................. 8-13
Wire Delay Calculations and Topology............................................................................. 8-15
Operating Conditions ....................................................................................................... 8-16
Edge Sensitivity in Path Delays ......................................................................................... 8-17
Setup Relationship Between Flip-Flops............................................................................. 8-18
Table of Contents
31833-000-S16B v Synopsys Chip Synthesis Workshop
DesignTime Timing Reports.............................................................................................. 8-19
Timing Report: Path Information Section........................................................................... 8-20
Timing Report: Path Delay Section.................................................................................... 8-21
Timing Report: Path Required Section............................................................................... 8-22
Timing Report: Summary Section...................................................................................... 8-23
Timing Report: Options .................................................................................................... 8-24
Timing Analysis: Diagnose Synthesis Results...................................................................... 8-25

Unit 9: DC Shell Tcl Interface
What is Tcl?....................................................................................................................... 9-4
Why Tcl? .......................................................................................................................... 9-5
Converting from dc_shell to dc_shell t............................................................................... 9-6
Executing DC-Tcl Script.................................................................................................... 9-7
Getting Help....................................................................................................................... 9-8
Comments in DC-Tcl....................................................................................................... 9-11
Nesting Commands and Quoting ...................................................................................... 9-12
Using Wildcards............................................................................................................... 9-13
Tcl Data Types ................................................................................................................ 9-14
Using Variables................................................................................................................ 9-15
Arithmetic Expressions ..................................................................................................... 9-17
Using Lists in dc_shell-t.................................................................................................... 9-18
Definitions: Objects and Attributes.................................................................................... 9-19
Definitions: Collections & Collection Handle ..................................................................... 9-20
Creating Collections ......................................................................................................... 9-21
Manipulating Collections................................................................................................... 9-23
Filtering Collections.......................................................................................................... 9-26
Running dc_shell t Interactively....................................................................................... 9-27
Day 3: Synthesizing the Design
Unit 10: Timing Revisited
Timing Goals: Part Two.................................................................................................... 10-5
Modeling Clock Trees...................................................................................................... 10-6
Modeling Uncertainty on Clock Edges.............................................................................. 10-7
set_clock_uncertainty and Setup Timing............................................................................ 10-8
Table of Contents
31833-000-S16B vi Synopsys Chip Synthesis Workshop
Modeling Source Latency................................................................................................. 10-9
Pre/Post Layout Clock................................................................................................... 10-10
Multiple Clocks - Synchronous....................................................................................... 10-11
Synchronous Multiple Clock Designs.............................................................................. 10-12
Creating a Virtual Clock................................................................................................. 10-14
Timing Goals for Multiple Clock Designs ........................................................................ 10-15
Hints for Multiple Clock Designs ................................................................................... 10-20
Multiple Clocks - Asynchronous..................................................................................... 10-21
Asynchronous Multiple Clock Designs............................................................................ 10-22
Synthesizing with Asynchronous Clocks.......................................................................... 10-23
The set_false_path command.......................................................................................... 10-24
Timing Goals Summary................................................................................................... 10-26
check_timing.................................................................................................................. 10-27
Appendix: Multi-Cycle Behavior..................................................................................... 10-29
Unit 11: Optimization
Three Phases of Optimization........................................................................................... 11-3
Architectural Optimization ................................................................................................ 11-4
Arithmetic Operators........................................................................................................ 11-5
DesignWare Implementation Selection.............................................................................. 11-6
Other High-Level Optimizations........................................................................................ 11-8
Sharing Common Sub Expressions ................................................................................... 11-9
Coding To Force Sharing ............................................................................................... 11-10
Resource Sharing: Example ............................................................................................ 11-11
Operator Reordering...................................................................................................... 11-13
Reordering Operators for Fast Design ............................................................................ 11-14
High-Level Synthesis is Constraint-Driven ...................................................................... 11-15
Logic-Level Optimization............................................................................................... 11-16
What is Structuring? ...................................................................................................... 11-18
What is Flattening? ........................................................................................................ 11-19
Structuring vs. Flattening................................................................................................. 11-20
Three Phases of Optimization......................................................................................... 11-21
Combinational Mapping................................................................................................. 11-22
Sequential Mapping ....................................................................................................... 11-23
Fixing Design Rule Violations.......................................................................................... 11-24
Table of Contents
31833-000-S16B vii Synopsys Chip Synthesis Workshop
Unit 12: Compile Strategies
Compile Completion ........................................................................................................ 12-3
User Interrupt.................................................................................................................. 12-5
Compile Report ............................................................................................................... 12-6
Compile Strategies........................................................................................................... 12-7
Constraint and Timing Analysis ......................................................................................... 12-8
Things to Look for........................................................................................................... 12-9
Use Re-Compile ............................................................................................................ 12-12
Change the Effort Level.................................................................................................. 12-13
Use Incremental Mapping............................................................................................... 12-16
When You Have Design Rule Violations ........................................................................ 12-19
What if You Have Hold Time Violations? ...................................................................... 12-20
Checking For Hold Time Violations ............................................................................... 12-23
Use Simultaneous Min-Max .......................................................................................... 12-24
Apply set_input_delay For Hold Time ........................................................................... 12-25
Apply set_output_delay For Hold Time .......................................................................... 12-26
Calculation of set_output_delay...................................................................................... 12-27
Fixing Hold Violations .................................................................................................... 12-28
Unit 13: Compiling a Hierarchical Design
Compiling a Hierarchical DesignUnder the Hood........................................................... 13-3
Compiling a Hierarchy ..................................................................................................... 13-4
First Phase of Compile ..................................................................................................... 13-5
Second Phase of Compile ................................................................................................ 13-6
Resolving Multiple Instances............................................................................................. 13-7
Designs Instantiated More Than Once .............................................................................. 13-8
check_design................................................................................................................... 13-9
Methods to Resolve Multiple Instances........................................................................... 13-10
Method #1: uniquify ....................................................................................................... 13-11
Method 2: compile + dont_touch.................................................................................... 13-13
Using set_dont_touch..................................................................................................... 13-15
uniquify vs. compile + dont_touch.................................................................................. 13-16
Table of Contents
31833-000-S16B viii Synopsys Chip Synthesis Workshop
Unit 14: DC-Tcl Procedures
Control Flow: Examples................................................................................................... 14-3
Looping Structures........................................................................................................... 14-4
Tcl Procedures................................................................................................................. 14-6
Scope of Variables........................................................................................................... 14-8
Procedure Information...................................................................................................... 14-9
Tcl Procedure Example .................................................................................................. 14-10
Table of Contents
31833-000-S16B ix Synopsys Chip Synthesis Workshop
Day 4: Post-Synthesis Processes
Unit 15: Compiling a Large Design
Techniques for Compiling a Hierarchical Design ................................................................ 15-3
Hierarchical Compile Techniques: Types........................................................................... 15-4
Top-Down Compile Methodology.................................................................................... 15-5
Advantages of Top-Down................................................................................................ 15-6
Simple Compile Mode ..................................................................................................... 15-7
Hierarchical Compile Techniques...................................................................................... 15-8
Bottom-Up Compile Methodology................................................................................... 15-9
Pros & Cons of Bottom-Up Compile ............................................................................. 15-12
Techniques for the Second-Pass Compile ....................................................................... 15-14
Problems After the First-Pass Compile ........................................................................... 15-15
Use report_constraint -all............................................................................................... 15-16
Use report_timing........................................................................................................... 15-17
Build a New Design Budget............................................................................................ 15-22
characterize.................................................................................................................... 15-23
Appendix - Design Budgeter .......................................................................................... 15-30
Unit 16: Design Exploration
Traditional Reactive Flow................................................................................................. 16-4
Proactive Design Methodology......................................................................................... 16-6
Design Exploration........................................................................................................... 16-7
Typical Compile Script (Basic) ....................................................................................... 16-11
Special WLM for Ports.................................................................................................. 16-13
set_max_capacitance ..................................................................................................... 16-15
set_max_transition.......................................................................................................... 16-16
set_max_fanout.............................................................................................................. 16-17
Fanout Loads................................................................................................................. 16-18
Fastest Runtimes for Design Exploration......................................................................... 16-21
Scenarios: Exploring Subdesigns..................................................................................... 16-23
I/O Timing Constraint Options........................................................................................ 16-28
Exploring Combinational Paths ....................................................................................... 16-30
User-Defined Path Groups............................................................................................. 16-31
Table of Contents
31833-000-S16B x Synopsys Chip Synthesis Workshop
Path Groups vs Critical Range........................................................................................ 16-34
Unit 17: Synthesizing for Test
Chip Defects: Theyre Not My Fault! ............................................................................... 17-3
Manufacturing Defects...................................................................................................... 17-4
Why Test for Manufacturing Defects? .............................................................................. 17-5
How Is Manufacturing Test Performed? ........................................................................... 17-6
The Stuck-At Fault Model ............................................................................................... 17-7
Controllability................................................................................................................... 17-9
Observability.................................................................................................................. 17-10
Fault Coverage .............................................................................................................. 17-11
Testing a Multistage, Pipelined Design............................................................................. 17-12
Scan Chains Help .......................................................................................................... 17-13
Use One-Pass Scan Synthesis........................................................................................ 17-15
DFT Checking: Example ................................................................................................ 17-17
Testability Violation: Example......................................................................................... 17-18
Running ATPG............................................................................................................... 17-19
What Is DFTC?............................................................................................................. 17-20
Test Tools Summary ...................................................................................................... 17-22
Synthesizing for Test Summary......................................................................................... 17-2
Unit 18: Conclusion
Some Thoughts on Coding ............................................................................................... 18-3
Synthesis Quality Depends on Algorithms!........................................................................ 18-4
Classic Algorithms, Architectures, & Tradeoffs ................................................................. 18-5
Reflections on Synthesis: .................................................................................................. 18-6
Pre-Compile Checklist ..................................................................................................... 18-7
What Do You Do First? .................................................................................................. 18-8
Compile Strategy ............................................................................................................. 18-9
Timing Analysis to Diagnose the Problem........................................................................ 18-10
Need More Training? .................................................................................................... 18-12
Advanced Chip Synthesis............................................................................................... 18-13
Coding Styles for Synthesis ............................................................................................ 18-14
Need More Information or Help? .................................................................................. 18-15
Synopsys on the World Wide Web................................................................................ 18-16
Table of Contents
31833-000-S16B xi Synopsys Chip Synthesis Workshop
How to Use solv-NET! ................................................................................................. 18-17
Human Sources for Information and Help ....................................................................... 18-18
Other Sources for Information and Help ......................................................................... 18-19
i-1
Introduction
Chip Synthesis Workshop
Synopsys 31833-000-S16
For BHNEC internal use only.
For BHNEC internal use only.
Chip Synthesis
Workshop
31833-000-S16
Synopsys Customer Education Services
2000 Synopsys, Inc. All Rights Reserved
i-2
Introduction
Fi r st Thi ngs Fi r st
? Instructor Introduction
? Student Guide
? Lab Guide
? Measurement of Learning Objectives
i-3
Introduction
Wor k shop Goal
Acquire the basic skills to synthesize a design
using Synopsys Design Compiler
i-4
Introduction
Wor k shop Pr er equi si t es
? Understanding of digital IC design
? Some knowledge of Verilog or VHDL
? Familiarity with UNIX and X-Windows
? Familiarity with a Unix-based text editor
i-5
Introduction
Wor k shop Tar get Audi enc e
? Board, FPGA, or ASIC-level Digital Designers
? Some Verilog or VHDL knowledge
? Little or no formal experience with Design Compiler
i-6
Introduction
4 Day Wor k shop Agenda
Synthesizing the Design
Day
3
Post-synthesis Processes
Day
4
Constraining the Design
Day
2
Pre-synthesis Processes
Day
1
i-7
Introduction
I c ons Used i n t hi s Wor k shop
Lab Exercise
Question
Checklist
Hint, Tip, or Suggestion
Caution
Note
Remember
i-8
Introduction
Abbr evi at i ons and Ac r onyms: Ex er c i se
Acronym Meaning
DC
DC
RTL
RTL
HDL
HDL
GTECH
GTECH
SDF
SDF
SOLD
SOLD
Acronym Meaning
DFT
DFT
PDEF
PDEF
Tcl
Tcl
ATPG
ATPG
1-1
Introduction to Synthesis
Chip Synthesis Workshop Synopsys 31833-000-S16
Agenda: Day 1
DAY
1
Introduction to Synthesis 1
Topic Lab Unit
Setup, Libraries, and Objects 2
Partitioning for Synthesis 3
Coding for Synthesis 4
1-2
Uni t Obj ec t i ves
After completing this unit you should be able to:
? List the basic steps of synthesis
? Describe advantages of synthesis
1-3
J ust What I s Synt hesi s?
Synthesis is the transformation of an idea
into a manufacturable device to carry out an
intended function
1-4
Our focus will
be here
Level s of Abst r ac t i on
Idea
Idea captured on
back of envelope
Gate-Level
Netlist
Register Transfer
Architectural HDL
Behavioral
HDL and
simulation language
Functional
Graphical or textual
description
Physical Device
Silicon
1-5
For Our Pur poses, Synt hesi s i s
Synthesis =
residue = 16h0000;
if (high_bits == 2b10)
residue = state_table[index];
else
state_table[index] = 16h0000;
HDL Source
Generic Boolean
(GTECH)
Translate
Target Technology
Optimize + Map
Translation + Optimization + Mapping
1-6
Why Synt hesi s?
Productivity
How else to do 10
6
gates in 6 months?
Portability
IEEE standards; HDL
portable across tools;
technology-independent
designs
Verifiable
Validate, implement, &
verify in same language,
Less error-prone entry
Abstraction
Focus on high-level
issues; tool & computer
do dirty work to meet
constraints
Design Tricks
DC knows plenty, tries
them in context of loads,
fanouts, library limitations
Reusability
Parameterized code;
Building-block approach;
Retarget new libraries;
Prestige
Impress friends; hot skill
on resume; job security;
wealth and fame
Why
Me?
1-7
Synt hesi s i s Const r ai nt -Dr i ven
Design Compiler optimizes the design to meet your goals
Large
Area
Small
Short
Delay
High

You set the goals (through constraints)
1-8
Synt hesi s i s Pat h-Based
D Q
QB
D Q
QB
FF2 FF3
MY_DESIGN
A
CLK
Z
How many timing
paths do you see
in MY_DESIGN?
Design Compiler uses Static Timing Analysis (STA)
to calculate the timing of the paths in the design.
1-9
Chi p Synt hesi s Pr oc ess
Chip Specification
Partition Chip
Floorplan
RTL Block Synthesis
Integrate Blocks
Insert Test
Floorplan
Place & Route
Final Verification
1-10
Desi gn Compi l er I nt er f ac es
Three ways to interface to Design Compiler (DC):
1 2
3 Design Analyzer
dc_shell (DCSH) dc_shell-t (DC-Tcl)
4
Design Vision
in 2000.11 release
1-11
Need Hel p?
%SOLD
acroread \
$SYNOPSYS/doc/online/top.pdf
%alias sman man -M \
$SYNOPSYS/doc/syn/man
%setenv MANPATH ${MANPATH}:
$SYNOPSYS/doc/syn/man
or
1-12
There are More than
4000 SOLV-IT! articles
Sear c h i n Ac r obat Reader
Search allows you to scan all documents in SOLD
Download
Acrobat Reader with Search
www.acrobat.com
1-13
w
r
i
t
e
Modul e Synt hesi s Roadmap
gtech.db
GTECH
my_chip.v(hd)
w
r
i
t
e
OPTIMIZATION + MAPPING
i
n
c
l
u
d
e
DC_MEMORY
TRANSLATION
scripts
constraints.scr
mapped
my_chip.db
my_chip.edif
compi l e
DC_MEMORY
MY_CHIP
core_slow.db
target_library
r ead
HDL source
unmapped
my_chip.db
r
e
a
d
anal yze/
el abor at e
Y=A+B
MY_CHIP
1-14
Anal yze, El abor at e - Read
analyzed
mychip.syn
mychip.sim(VHDL)
mychip.mra
DC MEMORY
Y=A+B
MYCHIP
mychip.v
mychip.vhd
read -f verilog mychip.v
unmapped
mychip.db
write -ouput ./unmapped/mychip.db -hier
analyze -f vhdl mychip.vhd
elaborate MYCHIP
1-15
Summar y: Ex er c i se
Synthesis = __________ + __________ + __________
Advantages of Synthesis:
____________________
____________________
____________________
1-16
Lab 1: I nt r oduc t i on
LAB
25 min
Run through the
basic Synthesis
Flow using scripts
Save the design
Inspect the design
Synthesise the design
Constrain the design
Bring in the design
1-17
Appendi x
Synopsys Physical Synthesis
1-18
Physi c al Chal l enge
1.0? 0.5? 0.25? 0.18?
P
e
r
c
e
n
t
a
g
e

o
f

D
e
l
a
y
W
i
r
e
G
a
t
e
Silicon Technology
1-19
Physi c al Synt hesi s
0.8? 0.5? to 0.35?
Place
& Route
Logic
Synthesis
Place
& Route
Logic
Synthesis
?0.25?
Physical
Synthesis
Flow
Place
& Route
1-20
Synopsys Physi c al Synt hesi s
FlexRoute:
Detailed Top
Level Routing
Pin
assignment
Design Compiler :
Logic Synthesis
Chip Architect:
Detailed Placement
Coarse Routing
Gates
Micro
Controller
Datapath
Module Compiler :
Specialized
Datapath
Synthesis
Chip Architect:
Budgeting
Estimation
Floor Planning
IO Placement
Memory
M
e
m
o
r
y
Physical Compiler:
RTL Synthesis &
Placement
Together
Placed
Gates
2-1
Setup, Libraries, and Objects
Synopsys Workshop Synopsys 31833-000-S16
Agenda: Day 1
Topic Lab Unit
Setup, Libraries and Objects 2
DAY
1 11 1
2-2
Uni t Measur abl e Obj ec t i ves
After completing this unit, you should be able to:
Specify the target library
Create the setup file for DC
Differentiate between the design objects
Find objects in DCSH mode and Tcl mode
2-3
Chapt er Over vi ew
Technology
Libraries
DC Setup File
Design Objects
2-4
Your ASIC vendor must provide a DC-compatible
technology library for synthesis!
Synt hesi s Revi ew
Recall the 3 steps involved in synthesis:
Translation
Optimization
Mapping
When DC maps a circuit, how will it know which
cell library you are using?
How will it know the timing of your cells?
2-5
Tec hnol ogy Li br ar y
Y = A | B
t
cell ( OR2_3 ) {
area : 8.000 ;
pin ( Y ) {
direction : output;
timing ( ) {
related_pin : "A" ;
timing_sense : positive_unate ;
rise_propagation (drive_3_table_1) {
values ("0.2616, 0.2608, 0.2831,..)
}
rise_transition (drive_3_table_2) {
values ("0.0223, 0.0254, ...)
. . . .
function : "(A | B)";
max_capacitance : 1.14810 ;
min_capacitance : 0.00220 ;
}
pin ( A ) {
direction : input;
capacitance : 0.012000;
. . . .
Cell name
Cell Area
Pin A -> Pin Y nominal
delays (look-up table)
Design Rules for
Output Pin
Electrical
Characteristics of
Input Pins
Pin Y functionality
A
B
Y
Example of a cell description in .lib Format
2-6
set target_library my_tech.db
Tar get Li br ar y Var i abl e
The Target Library is the library used by Design
Compiler for building a circuit
During mapping, DC will
choose functionally-correct gates from this library
calculate the timing of the circuit using vendor-supplied
timing data for these gates
target_library is a reserved variable in DC
Set it to point to the library file(s) provided by your silicon
vendor
2-7
DC Memory
*
Target
Library
Li nk Li br ar y Var i abl e
Used to resolve design references
First DC searches the memory and then the library
files specified in the link_library variable
Second DC searches the all paths defined in the
search_path variable
set link_library {* my_tech.db}
2-8
Ex ampl e
UNIX% dc_shell-t
dc_shell-t> read_verilog source/ALU.v
Loading db file standard.sldb
Loading db file gtech.db
Loading db file my_tech.db
Loading verilog file source/ALU.v
Current design is now ALU
ALU.v
module ALU (A,B,OUT1);
input A, B;
output [1:0] OUT1;
always @(A or B)
begin . . .
bob/ my_tech.db
DECODE.db
source/
TOP.v
ALU.v
2-9
Use l i nk t o Resol ve Desi gn Ref er enc es
dc_shell-t> read_verilog source/TOP.v
dc_shell-t> link
Unable to resolve reference DECODE in TOP
TOP.v
module TOP (A,B,OUT1);
input A, B;
output [1:0] OUT1;
ALU U1 (.AIN (A), . .
DECODE U2 (.A (BUS0), . .
How do we tell DC to find DECODE.db in bob?
bob/ my_tech.db
DECODE.db
source/
TOP.v
ALU.v
2-10
Set t he sear c h_pat h Var i abl e
bob/ my_tech.db
DECODE.db
source/
TOP.v
ALU.v
TOP.v
input A, B;
output [1:0] OUT1;
ALU U1 (.AIN (A), . .
dc_shell-t> read_verilog source/TOP.v
dc_shell-t> link
Loading db file bob/DECODE.db
dc_shell-t> which DECODE.db
/server/my_project/bob/DECODE.db
lappend search_path {bob}
2-11
Use of anal yze / el abor at e
bob/ my_tech.db
DECODE.db
source/
TOP.v
ALU.v
TOP.v
input A, B;
output [1:0] OUT1;
ALU U1 (.AIN (A), . .
dc_shell-t> analyze -f vhdl source/ALU.vhd
dc_shell-t> analyze -f vhdl source/TOP.vhd
dc_shell-t> elaborate TOP
Loading db file bob/DECODE.db
Current design is now TOP
Where do we specify the directory for the analyzed files?
lappend search_path {bob}
2-12
Chapt er Over vi ew
Technology
Libraries
DC Setup File
Design Objects
2-13
Desi gn Compi l er I nt er f ac es
Four ways to interface to Design Compiler (DC), the
Synopsys synthesis engine:
Design Vision
In release 2000.11
dc_shell-t
dc_shell
design_analyzer
Design Analyzer
dcsh mode dcsh mode
Design
Compiler
(DC)
Tcl mode
design_vision (-tcl)
2-14
Desi gn Compi l er Thr ee I ni t i al i zat i on Fi l es
.synopsys_dc.setup
.synopsys_dc.setup .synopsys_dc.setup
$SYNOPSYS/admin/setup ~user
risc_design
Users Specific
Project Setup
Users General
Setup
Standard
Setup
1
3
2
./command.log
command
log
./view_command.log
complete
log of DA
session
2-15
.synopsys_dc .set up Fi l e: Ex ampl e
target_library = "tc6a.db"
link_library = {"*" tc6a.db opcon.db}
symbol_library = "tc6a.sdb"
search_path = search_path + "./unmapped
alias h history
alias rc report_constraint -all_violators
2-16
.synopsys_dc .set up: Tc l and dc sh Mode
#
set target_library {tc6a.db}
set link_library {* tc6a.db opcon.db}
set symbol_library {tc6a.sdb}
set search_path $search_path ./unmapped
alias h history
alias rc "report_constraint -all_violators"
2-17
Chapt er Over vi ew
Technology
Libraries
DC Setup File
Design Objects
2-18
Desi gn Obj ec t s: VHDL Per spec t i ve
entity TOP is
port (A, B, C, D, CLK: in STD_LOGIC;
OUTI: out STD_LOGIC_VECTOR (1 downto 0));
end TOP;
architecture STRUCTURAL of TOP is
...
signal INV1, INV0, BUS1, BUS0: STD_LOGIC;
begin
U1: ENCODER port map (AIN=>A, . . . Q1=>BUS1);
U2: INV port map (A => BUS0, Z => INV0);
U3: INV port map (A => BUS1, Z=> INV1);
U4: REGFILE port map (D0=>INV0, D1=>INV1, . . CLK=>CLK);
end STRUCTURAL;
Reference
Pin
Net
Design
Cell
Clock
Port
2-19
module TOP (A,B,C,D,CLK,OUT1);
input A, B, C, D, CLK;
output [1:0] OUT1;
wire INV1,INV0,bus1,bus0;
ENCODER U1 (.AIN (A), . . . .Q1 (bus1));
INV U2 (.A (BUS0), .Z( INV0)),
U3 (.A( BUS1), .Z( INV1));
REGFILE U4 (.D0 (INV0), .D1 (INV1), .CLK (CLK) );
endmodule
Desi gn Obj ec t s: Ver i l og Per spec t i ve
Pin
Cell
Reference
Port
Design
Clock
Net
2-20
D0 Q[1:0]
D1
REGFILE
U4
OUT[1:0]
INV0
INV1
AIN
BIN
CIN
DIN
Q0
Q1
ENCODER
INV
INV
U1
U2
A
B
C
D
CLK
BUS0
BUS1
A
B
C
D
CLK
U3
TOP
Pin
CLK
Desi gn Obj ec t s: Sc hemat i c Per spec t i ve
Clock
Reference and Design
Design Cell Net
Port
Designs: {TOP, ENCODER, REGFILE}
References: {ENCODER, REGFILE , INV}
Cells: {U1, U2, U3, U4}
2-21
Mul t i pl e Obj ec t s w i t h t he Same Name
set_load 5 CLK
Does CLK refer to a clock, port, net, or pin object?
Does it matter onto which object DC places the load?
ADD
A
B
AIN
BIN
S
A
B
SIN
SUM
CLK
DFF
D
CLK
Q
U2
U1
TOP
CLK
2-22
The get Command
Searches the current_design
Can be used stand-alone or composed with other
functions
get commands return a list of object names, if
any are found, or an empty list
dc_shell-t> set_load 5 [get_nets CLK]
2-23
What I s a Li st ?
Lists are a key component of Design Compiler
A list is a special type of character string
A list begins and ends with a curly brace {}
Each item is separated by white space
dc_shell-t> set mylist {el1 el2 el3}
Information: Defining new variable mylist
el1 el2 el3
More to lists and objects in Chapter 9
2-24
ADD
A
B
AI
BI
S
A
B
SIN
SOUT
SUM
CLK
DFF
D
CLK
Q
U2
U1
TOP
CLK
get Command Ex er c i se
Write find commands to do the following:
1. List all of the ports in the design
2. List all of the cells with the letter Uin their name
3. List all of the nets ending with CLK
4. List all of the Qpins in the design
2-25
Ot her Handy Li st Commands
List all the input ports of the current design:
dc_shell-t> all_inputs
List all the output ports of the current design:
dc_shell-t> all_outputs
List all designs in the current design:
dc_shell-t> get_designs
2-26
Fi ndi ng obj ec t s w i t h dc _shel l -t
Many of the get commands shown previously have
an individual DC-Shell equivalent:
dcsh mode
get_cells *U* find(cell, *U*)
get_nets * find(net, *)
get_ports CLK find(port, CLK)
get_clocks CLK find(clock, CLK)
all_inputs all_inputs()
all_outputs all_outputs()
Tcl mode
2-27
Lab Det ai l s: Di r ec t or y St r uc t ur e
Source code for the CPU has been analyzed, elaborated,
and saved (in .db format ) in the unmapped subdirectory
NOTE: Always invoke Design Compiler
from the risc_design directory!
risc_design/
source/ unmapped/ scripts/ mapped/ reports/
vhdl/ verilog/
2-28
Lab Det ai l s: Hi er ar c hy of RI SC_CORE
PRGRM_CNT_TOP ALU
RISC_CORE
CONTROL DATA_PATH
INSTRN_LAT REG_FILE
STACK_TOP
OUT_VALID
PSW[10:0]
RESULT_DATA[15:0]
Rd_Instr
STACK_FULL
CLK
Xecutng_Instrn[31:0]
Instrn[31:0]
Reset
EndOfInstrn
RISC_CORE
PRGRM_CNT
PRGRM_DECODE
PRGRM_FSM
2-29
Lab Det ai l s: Desi gn Spec i f i c at i ons
Clock Speed
Clock Skew
Voltage
Operating Temperature
Technology Library
Symbol Library
200MHz (5ns)
300 psec max
1.8V ! !! !0.18V
0" "" "C to 125" "" "C
core_slow.db
core.sdb
2-30
Lab Det ai l s: Ex er c i se
From the specifications on the previous page,
define the library setup variables:
set target_library
set link_library
set symbol_library
2-31
LAB
Save the design
Inspect the design
Synthesize the design
Bring in the design
PRGRM_CNT_TOP
PRGRM_CNT
PRGRM_DECODE
PRGRM_FSM
Introduction to
Design Analyzer
and the
Synthesis Flow
60 min
2-32
Appendi x : Synopsys Synopsys Synopsys Synopsys Desi gnWar e Desi gnWar e Desi gnWar e Desi gnWar e
Silicon
Libraries
Standard
Cells
Memories
+ ProMA
Memory Generator
I/Os
0
.
1
8

0
.
1
5

0
.
1
3

Building
Blocks
>100 Components:
memBIST, LFSR,
FIFO CTL, etc
+ - << >> * Pipeline Mult,
Floating Point
Complex
IP Cores
MPEG2
USB2.0 PCI-X
8051 PCI 16550...
DesignWare
Complete Source
for Commodity IP
I
P

P
a
c
k
a
g
i
n
g

a
n
d

D
e
l
i
v
e
r
y
H
D
L

D
R
C

T
o
o
l
s
R
e
u
s
e

T
o
o
l
s
Star
IPs
e.g.,
ARM
MIPS
2-33
Desi gnWar e St andar d Cel l s
0.18m and 0.15m
Optimized for Design Compiler
Optimized for Module Compiler
Optimized for Power Compiler
Over 600 cells
simple and complex gates,
buffers, flip flops, latches,
complex cells, gated-clock cells
Actual silicon based on
DesignWare
standard cells
2-34
Single-port synchronous SRAM
Dual-port synchronous SRAM
Two-port register file
ROM
Desi gnWar e Pr oMA Memor y Gener at or s
2-35
Synopsys Si l i c on Li br ar i es
Synopsys
Silicon
Libraries
Design Creation Verification & Analysis
High Level
Physical
Design Compiler
Module Compiler
Power Compiler
Behavioral Compiler
DFT Compiler
COSSAP
VCS, Scirocco
Verilog-XL
ModelSim
VERA, Formality
PrimeTime
TetraMAX
RailMill
PathMill
TimeMill
PowerMill
Arcadia
Dracula
Calibre, Hercules
FlexRoute
Chip Architect
Physical Compiler
Apollo
Silicon Ensemble
3-1
Partitioning for Synthesis
Topic Lab Unit
DAY
1 11 1
Agenda: Day 1
3-2
List two effects of partitioning a circuit through
combinational logic
State the main guideline for partitioning for
synthesis
State how partitions are created in HDL code
List two DC commands for modifying partitions
3-3
Partitioning is the process of dividing complex
designs into smaller parts
Divide and conquer!
What i s Par t i t i oni ng?
Ideally, all partitions would be planned prior to
writing any HDL
Initial partitions are defined by the HDL
Initial partitions can be modified using Design Compiler
3-4
Focus will be on partitioning for synthesis
Why Par t i t i on a Desi gn?
Partitioning is driven by many (often competing) needs:
Separate distinct functions
Achieve workable size and complexity
Manage project in team environment
Design Reuse
Meet physical constraints
And many, many others ...
3-5
ADR_BLK
DEC
OK
ADR
AS
OK
INST
CLK
module ADR_BLK (...
DEC U1(ADR,CLK,INST);
OK U2(ADR,CLK,AS,OK);
endmodule
entity ADR_BLK is... end;
architecture STR of ADR_BLK is
U1:DEC port map(ADR, CLK, INST);
U2:OK port map(ADR,CLK,AS,OK);
end STR;
U1
U2
Par t i t i oni ng Wi t hi n t he HDL Desc r i pt i on
entity and module statements define hierarchical blocks
Instantiation of an entity or module also creates a new level of
hierarchy
Inference of Arithmetic Circuits (+, -, *, ..) can create a new
level of hierarchy
process and always statements do not create hierarchy
3-6
CLK
REG
A
COMBO
LOGIC
A
A
COMBO
LOGIC
B
B
COMBO
LOGIC
C
CLK
REG
C
C
? ?
Are these partitions truly needed?
El i mi nat e Unnec essar y Hi er ar c hy
Design Compiler must preserve port definitions
Logic optimization does not cross block boundaries
Adjacent blocks of combinational logic cannot be merged
Path from REG A to REG C may be larger and slower
than necessary!
3-7
Better Partitioning
CLK
CLK
REG
A
REG
C
COMBO LOGIC
A & B & C
A C
No Hi er ar c hy i n Combi nat i onal Pat hs
Related combinational logic is grouped into one block
No hierarchy separates combinational functions
A, B, and C
Combinational optimization techniques can now be fully
exploited
3-8
Best Partitioning
CLK
REG
A
CLK
REG
C
COMBO LOGIC
A & B & C
A C
No Hi er ar c hy i n Combi nat i onal Pat hs (c ont )
Related combinational logic is grouped into the same
block with the destination register
Combinational optimization techniques can still be
fully exploited
Sequential optimization may now absorb some of the
combinational logic into a more complex Flip-Flop
(J K, T, Muxed, Clock-enabled)
3-9
Good Partitioning
CLK
REG
A
A
CLK
REG
B
B
CLK
REG
C
C
Try to design so hierarchy boundaries
follow register outputs.
Par t i t i on at Regi st er Boundar i es
Simplifies timing constraints:
All inputs to each block arrive with the same relative delay
3-10
Poor Partitioning
TOP
COMBO
LOGIC C
CLK
REG
C
COMBO
LOGIC A
CLK
REG
A
A C
COMBO
LOGIC B
CLK
REG
B
B
Avoi d Gl ue Logi c : Ex ampl e
The NAND gate at the top level serves only to glue
the instantiated cells:
Optimization is limited because the glue logic cannot be absorbed
3-11
Good Partitioning
Nothing but nets
at top level
TOP
COMBO
LOGIC C
+
GLUE
CLK
REG
C
COMBO
LOGIC A
CLK
REG
A
A
C
COMBO
LOGIC B
CLK
REG
B
B
Remove Gl ue Logi c Bet w een Bl oc k s
The glue logic can now be optimized with other logic
Top-level design is only a structural netlist, doesnt
need to be compiled
3-12
Poor Partitioning
Too Small
500
Gates
TEENY
Too Big
100,000
Gates
370,000
Gates
8,000
Gates
BIG
Bal anc e Bl oc k Si ze Wi t h Run Ti mes
If blocks are too small, the designer may be restricting
optimization with artificial boundaries
If blocks are too big, compile run times can be very long
3-13
Good Partitioning
150,000
Gates
BIGGER
50,000
Gates
BIG
5,000
Gates
SMALL
Bal anc e Bl oc k Si ze Wi t h Run Ti mes
For quick turnaround, partition so that each block has 5,000
- 150,000 gates
Design Compiler has no inherent limit
Match module size to CPU and memory:
Larger modules are fine if sufficient resources are available
Choose smaller sizes when workstation power is limited
3-14
Partition the Top-Level design into at least three levels of hierarchy:
1. Top-level
2. Mid-level
3. Core
Separ at e Cor e Logi c , Pads, Cl oc k s, and J TAG
CLOCK GEN
JTAG
CORE
MID
ASYNCH
This partitioning is recommended due to:
Possible technology-dependent ( black box ) I/O pad cells
Possible untestable Di vide By clock generation
Possible technology-dependent JTAG circuitry
TOP
3-15
Par t i t i oni ng w i t hi n Desi gn Compi l er
The group and ungroup commands modify the partitions
in a design
group
ungroup
3-16
DES_A
TOP_DESIGN
U1
The gr oup Command
group creates a new hierarchical block
group -design_name NEW_DES
-cell_name U23
{U2 U3}
DES_A
DES_B
TOP_DESIGN
U1 U2 U3
DES_C
NEW_DES
U23
DES_B DES_C
U2 U3
3-17
DES_A
TOP_DESIGN
U1 U23
DES_B DES_C
U2 U3
The ungr oup Command
ungroup removes either one or all levels of hierarchy
TOP_DESIGN
DES_A
U1
NEW_DES
U23
NEW_DES
current_design NEW_DES
ungroup {U2 U3}
3-18
The ungr oup Command: Ex er c i se
ungroup {U23}
DES_A
TOP_DESIGN
U1 U23
DES_Y DES_Z
U2 U3
DES_B
What happens if
you ungroup U23?
3-19
Par t i t i oni ng St r at egi es f or Synt hesi s
Do not separate combinational logic across
hierarchical boundaries
Place hierarchy boundaries at register outputs
Size blocks for reasonable runtimes
Separate core logic, pads, clocks, and JTAG
3-20
Par t i t i oni ng f or Synt hesi s: Summar y
What do we gain by partitioning for synthesis ?
Better results -- smaller and faster designs
Easier synthesis process -- simplified constraints and
scripts
Faster compiles -- quicker turnaround
3-21
LAB
Design Problem: Timing Violation
Change Partition for Better Synthesis Results
PRGRM_FSM
PRGRM_
DECODE PRGRM_CNT
30 min
group / ungroup
4-1
Coding for Synthesis
Agenda: Day 1
Topic Lab Unit
DAY
1 11 1
4-2
Uni t Measur abl e Obj ec t i ves
Describe hardware implications for the following
coding constructs:
if-else
case
loops
Compile HDL code and observe the effects in
synthesis
Use DesignWare elements in your RTL source code
4-3
The I mpor t anc e of Qual i t y of Sour c e
Code that is functionally equivalent, but coded
differentl y, will give different synthesis results
You cannot rely solely on Design Compiler to fix
a poorly coded design!
Try to understand the hardware you are
describing, to give DC the best possible starting
point
Poor
Start
Point
Better
Start
Point
Best
Start
Point
Goal
4-4
RTL Codi ng Gui de
H
D
L
Coding cookbook
The three big picture guidelines
4-5
The Bi g Pi c t ur e, Thi nk Har dw ar e!
Write HDL hardware descriptions
Think of the topology implied by the code
Do not write HDL simulation
models
No explicit delays
No file I/O
after 20 ns and
2 clock cycles
OUTPUT <= IN1 + RAM1;
wait 20 ns;
...
Yes!
No!
4-6
ADDR
DECODE
ADDR_IN
ACK
ACK_SET
AS
+5
ACK_CLR
How am I going to
synthesize this?
The Bi g Pi c t ur e, Thi nk Sync hr onous!
Synchronous designs run smoothly through synthesis,
test, simulation, and layout
Asynchronous designs may require hand instantiation
and extensive simulation to verify
Isolate asynchronous logic into separately compiled blocks
4-7
The Bi g Pi c t ur e, Thi nk RTL!
RTL = Register Transfer Level
Writing in an RTL coding style
means describing
the register architecture,
the circuit topology, and
the functionality between
registers
Design Compiler optimizes logic
between registers
It does not optimize the register
placement
4-8
RTL Synt hesi s Cook book
H
D
L
The three big picture guidelines
Coding cookbook
4-9
Synt hesi s of if St at ement s
Synthesis of loop statements
Synthesis of Flip-Flops
Synthesis of case statements
Synthesis of if statements
Synthesis of arithmetic circuits
4-10
if (Aflag = '1') then
OutData <= A + B;
else
OutData <= C + D;
end if;
Aflag
OutData
D1
S
+
D0
+
A
B
C
D
How could we recode this example so that the
multiplexing hardware was before the adder?
i f -el se St at ement s
The if-else construct implies multiplexing hardware
One output value is selected based on a certain condition
Actual circuit implementation depends on target library and
constraints
4-11
if (Aflag == 1b1)
begin
Op1 <= A;
Op2 <= B;
end
else
begin
Op1 <= C;
Op2 <= D;
end
OutData <= Op1 + Op2;
What if Aflag was late-arriving? Which circuit is better?
What if the else was missing?
OutData
Aflag
+
D1
S
D0
A
Op2
D1
S
D0
C
B
D
Op1
Aflag
i f -el se St at ement s (c ont )
Location of multiplexing hardware depends on
location of if-else construct
4-12
LS373: process (ALE, ADBUS)
begin
if (ALE = 1) then
ABUS <= ADBUS;
end if;
end process LS373;
always @ (ALE or ADBUS)
begin
if (ALE)
ABUS <= ADBUS;
end
ABUS
ADBUS
ALE G
D Q
8
/
8
/
i f St at ement s and Lat c hes
To infer latches, use an if statement without an else
clause
VHDL/Verilog language definitions require signals to
maintain their old value unless a new value is assigned
Latches implement this requirement in hardware
4-13
int0
int1
int2
int3
active[0]
active[1]
active[2]
active[3]
i f -t hen-el sei f St at ement s
Since VHDL and Verilog if-elseif statements imply priority,
they should only be used if priority checking is a circuit
requirement
Otherwise, priority control logic will be synthesized
Result will be more, and possibly slower logic
Example:
Priority Interrupt Controller
One or more of four (input) interrupt lines (int0..int3) may be
asserted
Only one output should be asserted
int0 has the highest priority
4-14
i f -t hen-el sei f St at ement s (c ont )
module test(active,int0,int1,int2,int3);
input int0,int1,int2,int3;
output [3:0] active;
reg int0,int1,int2,int3;
reg [3:0] active;
always@(int0 or int1 or int2 or int3) begin
active[3:0] <= 4b0;
if (int0) active[0] <= 1b1;
else if (int1) active[1] <= 1b1;
end; endmodule
Which flag has the
highest priority?
Why are the
outputs active[3:0]
initialized to 0?
4-15
Pr i or i t y I nt er r upt Ci r c ui t : Synt hesi s Resul t s
Priority Logic
int0
active[0]
active[1]
active[2]
active[3]
int1
int2
int3
4-16
When NOT t o Use i f -t hen-el sei f
When signals have equal priority
When signals are mutually exclusive
4-17
Synt hesi s of c ase St at ement s
Synthesis of if Statements
Synthesis of case Statements
Synthesis of loop Statements
Synthesis of Arithmetic Circuits
4-18
c ase St at ement s
case statements in Verilog
case statements in VHDL
4-19
c ase St at ement s
Case statements implyparallel mux function.
always@(SEL or A or B or C or D)
begin
case (SEL)
2b00 : OUTC = A;
2b01 : OUTC = B;
2b10 : OUTC = C;
default : OUTC = D;
endcase
end
process (SEL,A,B,C,D) begin
case SEL is
when 00 => OUTC <= A;
when 01 => OUTC <= B;
when 10 => OUTC <= C;
when others => OUTC <= D;
end case;
end process;
VHDL Code
Verilog Code
Note: Actual gates synthesized
might not be a 4:1 MUX.
00
01
10
11
A
SEL
OUTC
2
B
C
D
4-20
I nt er r upt Vec t or Addr ess Gener at or
Build a logic that takes the signals of the priority interrupt circuit and
generates a 16-bit memory address that is unique for each interrupt.
active[0]
active[1]
active[2]
active[3]
vec[15:0]
interrupt address to be generated
active[0] 0000000000 00000100b (0004h)
active[1] 0000000000 00000110b (0006h)
active[2] 0000000000 00001000b (0008h)
active[3] 0000000000 00001010b (000Ah)
Each of the above memory locations contain the starting address of an
interrupt handling routine, which is read by the processor at an
appropriate time after a valid interrupt is recognized.
4-21
always @(active[3] or active[2] or active[1] or active[0])
begin
case ({active[3], active[2], active[1], active[0]})
4b1000 : temp = 3b010;
4b0100 : temp = 3b011;
4b0010 : temp = 3b100;
4b0001 : temp = 3b101;
4b0000 : temp = 3b000;
default : temp = 3bxxx;
endcase
end
always vec[15:4] = 12h000;
always vec[0] = 0;
always @(posedge clk) vec[3:1] = temp;
Addr ess Gener at or : Ver i l og
What happens if you do not include the
default clause?
4-22
Sc hemat i c of Addr ess Gener at or
D Q
CLK
D Q
CLK
D Q
CLK
vec[0]
vec[1]
vec[2]
vec[3]
vec[15:4]
vec[15:0]
gnd
active[2]
active[3]
active[0]
active[1]
clk
A schematic after compiling the source code of the Interrupt Vector Address Generator.
Without the default clause, the case statement would not
be fully specified and infer latches.
Can be controlled by compiler directives.
4-23
Compi l er Di r ec t i ve f ul l _c ase
begin
case ({active[3], active[2], active[1], active[0]})
//synopsys full_case
4b1000 : temp = 3b010;
4b0100 : temp = 3b011;
4b0010 : temp = 3b100;
4b0001 : temp = 3b101;
4b0000 : temp = 3b000;
endcase
end
always vec[15:4] = 12h000;
always vec[0] = 0;
4-24
Compi l er Di r ec t i ve par al l el _c ase
begin
temp = 3b000;
case (1b1) //synopsys parallel_case
active[3] : temp = 3b010;
endcase
end
always vec[15:4] = 12h000;
always vec[0] = 0;
4-25
Synt hesi s of l oop St at ement s
4-26
Unr ol l i ng Loops
In synthesis, for loops are unrolled during translation,
and then synthesized
out(0) <= a(0) and b(3);
out(1) <= a(1) and b(2);
out(2) <= a(2) and b(1);
out(3) <= a(3) and b(0);
integer i;
always@( a or b) begin
for ( i = 0; i <= 3 ; i = i + 1 )
out[i] <= a[i] & b[3 - i];
end
integer i;
always@( a or b) begin
for ( i = 0; i <= 3 ; i = i + 1 )
out[i] <= a[i] & b[3 - i];
end
process ( a, b )
begin
for i in 0 to 3 loop
out(i) <= a(i) and b(3 - i);
end loop;
end process;
process ( a, b )
begin
out(i) <= a(i) and b(3 - i);
end loop;
end process;
a(0)
b(3)
out(0)
a(1)
b(2)
out(1)
a(2)
b(1)
out(2)
a(3)
b(0)
out(3)
4-27
Tr adeof f s w i t h Loops
always@(data)
begin
sum = 0;
/* Count the number of 1s */
for (i = 0; i < 8; i = i + 1)
sum = sum + data[i];
/* Check if even or odd number */
odd_parity = sum[0];
end;
process (data)
variable sum : integer;
begin
sum := 0;
-- Count the 1s
sum := data(i) + sum;
end loop;
--check parity
odd_parity <= sum mod 2;
end process;
What does the hardware look like for this example?
4-28
Har dw ar e Resul t
...
2
Data(0)
+
Data(1)
/
+
Data(2)
/
2
+
Data(7)
+
Data(6)
/
3
How could this be recoded?
4-29
Rec oded Loop
always@ (data)
begin
odd_parity = ^data;
end
binary XOR
Verilog
VHDL
optimized design
process (data)
variable odd_parity : bit;
begin
odd_parity <= 0;
odd_parity <= data(i) xor odd_parity;
end loop;
end process;
unrolled
4-30
Synt hesi s of Fl i p-Fl ops
4-31
I nf er r i ng Sequent i al Devi c es
Registering a signal means clocking it into a Flip-Flop
For DC to infer Flip-Flops, your code must imply signal
assignments that take place in response to the edge of
another signal
DC requires specific coding templates to infer registers
How do you:
A
B
CLK
RSTn
D Q + S1
assign A+B to S1
With an asynchronous
reset?
in response to a rising edge
on CLK ?
4-32
Fl i p-Fl op: Ex ampl e
always@(posedge CLK or negedge RSTn)
begin
if (! RSTn)
S1 <= 1b0;
else
S1 <= A + B;
end
process (CLK, RSTn)
begin
if (RSTn =0) then -- async reset
S1 <= 0;
elsif (CLKevent and CLK = 1) then
S1 <= A + B;
end if;
end process;
A
B
CLK
RSTn
D Q +
S1
4-33
Latch
Latch
w/
Async
Latch
w/Dual
Async
DFF
w/
Async
DFF
w/Dual
Async DFF
Muxed
DFF
JKFF
MS
Latch
Latch
w/Sync
Clr
DFF
w/Sync
Cntl.
The registers in your final circuit depend on:
Coding style (including attributes and directives)
Types of registers available in the target_library
(V)HDL Compiler generates an inference report
Example: Inference Report for an AR Flip-Flop
Register Name Type Width Bus MB AR AS SR SS ST
Q_reg Flip-Flop 1 - - Y N N N N
I nf er r i ng Sequent i al Devi c es
Design Compiler can synthesize hardware using a
wide variety of flip-flops and latches
4-34
Synt hesi s of Ar i t hmet i c Ci r c ui t s
4-35
I nf er r i ng Ar i t hmet i c Par t s
process (A, B, C, D, addr)
begin
if (addr = 12) then
Result <= A + B;
else
Result <= C + D;
end if;
end process;
always@ (A or B or C or D or addr)
begin
if (addr == 4d12)
Result <= A + B;
else
Result <= C + D;
end
What does the hardware look like in this example?
Where do the mathematical circuits come from?
4-36
Technology
Library
link_library,
target_library
DesignWare
Library
synthetic_library
AND Gates,
OR Gates,
Flip-Flops...
Adders,
Multipliers,
Comparators...
if (A1 >= A2)
Y <= M * X + B;
else
Y <= M * X + C;
Desi gnWar e Ar i t hmet i c Resour c es
What is DesignWare?
Technology-independent soft macrossuch as adders,comparators, etc.,
which are synthesized into gates from your target library
Enables the user to imply large and complex arithmetic operations to be
synthesized:
4-37
Desi gnWar e I mpl ement at i on Sel ec t i on
Multiple architectures for each macro allow DC to evaluate
speed/area tradeoffs and choose the best implementation
HDL
Operator
+
smallest
fastest
Carry Look-Forward
Carry Look-Ahead
Ripple Carry
Z <= A + B;
Brent-Kung
Conditional
Sum Synthesis
DW
Foundation
DW
Basics
Ripple Carry Select
4-38
synthetic_library = {dw_foundation.sldb}
Enabl i ng Fast er DW I mpl ement at i ons
DesignWare components come from synthetic libraries
Synopsys-provided synthetic library files reside in
directory $SYNOPSYS/libraries/syn
The synthetic_library variable points to a list of
synthetic library database (.sldb) files:
link_library = link_library + synthetic_library
4-39
SUM <= A*B + C*D + E + F + G
*
SUM
A
B
*
+
+
C
D
E
+
F
+
G
Total Delay = Multiplier + 4 adders
I mpl yi ng a St r uc t ur e by Oper and Pl ac ement
As with if-else blocks, coding style implies a circuit
topology
V/HDL Compiler parses expressions from left to right
Parentheses will override this default order
DesignWare built in this order is the starting point for DC
4-40
I mpl yi ng a St r uc t ur e by Oper and Pl ac ement (c ont )
Change the order, or use parentheses to force a different
topology:
+
SUM
E
F
*
+
+
C
D
+
G
*
A
B
Max Delay = Multiplier + 2 adders
SUM <= (A*B) + ( (C*D) + ((E+F) + G) )
SUM <= E + F + G + C*D + A*B
4-41
Ver i l og Pr epr oc essor Di r ec t i ve
module IFDEF(out,a,b,clk);
output out;
input clk,a,b;
reg out;
always@(posedge clk)
begin
ifdef SYN
out=b && a;
else SYN
$display (The output is: );
out=b && a;
endif
end
endmodule
set hdlin_enable_vpp true
analyze -f verilog -d SYN IFDEF.v
elaborate IFDEF -lib WORK
4-42
Doc ument at i on
Synopsys On-Line Documentation
HDL Compiler for Verilog Reference Manual
VHDL Compiler Reference Manual
Guide to HDL Coding Styles for Synthesis
Nonblocking Assignments in Verilog Synthesis,
Coding Styles That Kill!
www.synopsys.com -> SNUG -> SNUG Papers -> 2000 San J ose
full_case parallel_case, the Evil Twins of Verilog
Synthesis
www.synopsys.com -> SNUG -> SNUG Papers -> 1999 Boston
4-43
LAB
Examine Coding Style Issues
Area
Path Value
LOOP_BAD LOOP_GOOD
IF_BAD IF_GOOD
LOOP_BEST
IF_BEST
compare_design IF_BAD IF_GOOD
60 min
4-44
Appendi x
Inference and Instantiation
4-45
Ver i l og I nf er enc e and I nst ant i at i on
always @(A or B) begin :b1
/* synopsys resource r0:
map_to_module = "DW02_mult",
implementation = "wall",
ops = "a1"; */
PROD <= A * B; //synopsys label a1
end;
// synopsys dc_script_begin
// set_implementation wall U1
// synopsys dc_script_end
DW02_mult #(Awidth, Bwidth) U1(A, B, TC, PROD);
Instantiation
Inference
report_resources
identifier for the resource
Wallace tree
synthesis model
synthetic
module
4-46
VHDL I nf er enc e and I nst ant i at i on
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
inside the architecture block:
PROD <= A * B;
library IEEE, DWARE;
use IEEE.std_logic_1164.all;
use DWARE.DW_Foundation_comp;
inside the architecture block:
U1: DW01_add
Instantiation
Inference
5-1
Timing and Area
Agenda: Day 2
DAY
2 22 2
Timing and Area 5
Topic Lab Unit
Environmental Attributes 6
Time and Load Budgeting 7
Timing Analysis 8
DC Tcl - Introduction 9
5-2
Timing and Area
Constrain a design for area
Constrain a design for timing
5-3
Timing and Area
RTL Bl oc k Synt hesi s
Simulate
OK?
Yes
Rewrite
Yes
No
Major
Violations?
No
Yes
No
Write RTL
HDL Code
Synthesize
HDL Code
To Gates
Met
Constraints?
Analysis
Constraints & Attributes
Area & Timing Goals
5-4
Timing and Area
dc_shell-t> current_design PRGRM_CNT_TOP
dc_shell-t> set_max_area 100
dc_shell-t> current_design PRGRM_CNT_TOP
dc_shell-t> set_max_area 100
Spec i f yi ng an Ar ea Goal
Units are those of target library,
defined by the vendor
2-input-NAND-gate
transistors
square mils
5-5
Timing and Area
Ti mi ng Goal s: Sync hr onous Desi gns
Synchronous Designs:
Data arrives from a clocked device
Data goes to a clocked device
Objective:
Define the timing constraints for all paths within a design:
all input logic paths
the internal (register to register) paths, and
all output paths
5-6
Timing and Area
Ti mi ng Goal s: Sync hr onous Desi gns (c ont )
D Q
QB
D Q
QB
D Q
QB
D Q
QB
Clk
TO_BE_SYNTHESIZED
FF1
FF2
FF3
FF4
M
N
X
S
T
Example:
Clock Period = 10ns Setup = 1ns
What information must you provide to constrain all
the register-to-register paths in your design?
Does the duty cycle of your clock matter?
What is the max delay requirements for the register-to-register
paths in the block TO_BE_SYNTHESIZED?
5-7
Timing and Area
Def i ni ng a Cl oc k
User MUST Define:
Clock Source (port or pin)
Clock Period
Period
Clk
N X S
D Q D Q
TO_BE_SYNTHESIZED
FF2
FF3
User may also define:
Duty Cycle
Offset/Skew
Clock Name
Clk
1 Clock Cycle
5-8
Timing and Area
Def i ni ng a Cl oc k i n Desi gn Compi l er
Creating a clock constrains timing paths between registers
Use report_clock to see defined clocks and their
attributes
set_dont_touch_network tells DC not to buffer up the
clock net, even if there are too many flip-flops loading it
TO_BE_SYNTHESIZED
Clk
dc_shell-t> create_clock -period 10 [get_ports Clk]
dc_shell-t> set_dont_touch_network [get_clocks Clk]
5-9
Timing and Area
D Q D Q
D Q
QB
D Q
QB
Clk
TO_BE_SYNTHESIZED
FF1
FF2
FF3
FF4
M
N
X
S
T
Ti mi ng Goal s: Sync hr onous Desi gns, I /O
Method:
1. Define the clocks
2. Define the I/O timing relative to the clocks
Path X constrained
by create_clock
Paths N & S are still
unconstrained!
5-10
Timing and Area
Const r ai ni ng t he I nput Pat hs
TO_BE_SYNTHESIZED
N
D Q
Clk
M
D Q
T
Clk-q
T
M
T
N
T
SETUP
Next edge
captures data
External Logic
(Input Delay)
(T
Clk-q
+ T
M
) (T
N
+ T
SETUP
)
Clk
A
What information must you provide to constrain the input paths?
Launch edge
triggers
data
A
Clk
Valid new data
5-11
Timing and Area
Const r ai ni ng I nput Pat hs i n DC
The set_input_delay command constrains input paths
You specify how much
time is used by
external logic...
DC calculates how much
time is left for the
internal logic
Launch Edge
4
delay of
external
logic
time left
for
internal
logic
Capture Edge
dc_shell-t> set_input_delay -max 4 -clock Clk [get_ports A]
5-12
Timing and Area
7.4
0.0 10.0 20.0
Clk
A
set _i nput _del ay: Ex er c i se
Constraint of
YOUR input path
create_clock _______________________________________
set_dont_touch_network ____________________________
set_input_delay ____________________________________
TO_BE_SYNTHESIZED
A
Clock
(50 MHz)
CLK-OUTPUT
7.4 ns
(worst)
U1
EXTERNAL CIRCUIT
D Q N
Clk
5-13
Timing and Area
set _i nput _del ay: Ef f ec t on I nput Pat hs
TO_BE_SYNTHESIZED
A
Clk
(50 MHz)
EXTERNAL CIRCUIT
If U1 has a 1 ns setup requirement:
What is the maximum delay for T
N
?
create_clock -period 20 [get_ports Clk]
set_dont_touch_network [get_clocks Clk]
set_input_delay -max 7.4 -clock Clk [get_ports A]
D
Q
N
Clk
CLK-OUTPUT
7.4 ns
(worst)
U1
5-14
Timing and Area
Const r ai ni ng Out put Pat hs of a Desi gn
Clk
S
D Q
T
s
TO_BE_SYNTHESIZED
D Q
T
T
T
SETUP
T
External Logic
U3 B
T
Clk-q
T
T
+ T
SETUP
Launch Edge Capture Edge
T
Clk-q
+ T
S
(Output Delay)
Clk
B
What information must you provide to constrain the output paths?
U3
Launches
Data
External
Flip-Flop
captures
data
Valid new data
5-15
Timing and Area
Launch
Edge
Capture
Edge
5.4
Const r ai ni ng Out put Pat hs i n DC
The set_output_delay command constrains output paths
You specify how much
time is needed by
external logic...
DC calculates how much
time is left for
internal logic
Constraint of
YOUR output path
dc_shell-t> set_output_delay -max 5.4 -clock Clk [get_port B]
5-16
Timing and Area
set _out put _del ay Ex er c i se
0.0 10.0 20.0
7.0
Data
launched
here
Must be valid
here
Gets
clocked
here
create_clock _______________________________________
set_dont_touch_network _____________________________
set_output_delay ___________________________________
Clk
B
Clk
S
D Q
TO_BE_SYNTHESIZED
U3 B
EXTERNAL CIRCUIT
Setup
Requirement:
7.0 ns
Clk
(50 MHz)
5-17
Timing and Area
set _out put _del ay: Ef f ec t on Out put Pat hs
set_dont_touch_network [get_clocks Clk]
set_output_delay -max 7.0 -clock Clk [get_ports B]
If U3 has T
CLK-Q
= 1.0ns:
What is the maximum delay for T
S
?
Clk
S
D Q
TO_BE_SYNTHESIZED
B
EXTERNAL CIRCUIT
Setup
Requirement:
7.0 ns
Clock
(50 MHz)
U3
5-18
Timing and Area
Ar ea & Ti mi ng Goal s Summar y: Ex er c i se
Clk
D Q
QB
D Q
QB
D Q
QB
D Q
QB
TO_BE_SYNTHESIZED
FF1
FF2
FF3
FF4
M
N
X
S
T
How do you constrain the register to register paths?
How do you constrain the the I/O paths?
How do you constrain for area?
5-19
Timing and Area
Usef ul Commands
report_port -verbose Returns all attributes and constraints
placed on all input and output ports
report_clock Returns the source, waveform and
period of all clock objects in
current_design
reset_design Removes attributes and constraints
from current_design
list_libs Returns the available libraries in
memory
5-20
Timing and Area
LAB
Apply Timing Constraints
30 min
Save the design
Bring in the design
unmapped
PRGRM_CNT_TOP.db
unmapped
prgrm_attr.db
6-1
Environmental Attributes
Agenda: Day 2
DAY
2 22 2
Timing and Area 5
Topic Lab Unit
Timing Analysis 8
6-2
Scale cell delays for Temperature and Voltage
extremes
Use Wire Load Models within DC
Use constraints for DC to account for external
circuitry
6-3
Area & Timing Goals
Simulate
OK?
Met
Constraints?
Analysis
Yes
Rewrite
Yes
Netlist
No
Major
Violations?
No
Yes
No
Write RTL
HDL Code
Synthesize
HDL Code
To Gates
6-4
D Q
QB
D Q
QB
CLK
TO_BE_SYNTHESIZED
FF2
FF3
N
X
S
set_input_delay
set_output_delay
create_clock
Const r ai ni ng f or Ti mi ng: What s Mi ssi ng?
What physical information about the chip is required in
order to accurately calculate the speed of each path?
What information (besides external setup) does DC require
in order to ensure logic S meets timing?
What information (besides input delay) does DC require in
order to ensure logic N meets timing?
6-5
Desc r i bi ng Envi r onment al At t r i but es
set_driving_cell
set_load
set_operating_conditions
set_wire_load_model
6-6
TO_BE_SYNTHESIZED
Model i ng Capac i t i ve Load
In order to accurately calculate the timing of an output
circuit, DC needs to know the total capacitance driven by
the output cells
set_load allows the user to specify the external capacitive
load on ports
By default, DC assumes that the external load on ports is 0
You can specify some other constant value, or...
The load_of command can be used to specify the external load as
the pin load of a cell in your technology library
6-7
set _l oad Ex ampl es
Use set_load to specify a load value on an output port:
set_load 5 [get_ports OUT1]
OUT1
5
set_load [expr [load_of(my_lib/inv1a0/A) * 3]] OUT1
A
OUT1
A
A
OUT1
AN2
A
Use set_load load_of(lib/cell/pin) to place the
load of a gate from the technology library on the port:
set_load [load_of(my_lib/and2a0/A)] [get_ports OUT1]
B
6-8
TO_BE_SYNTHESIZED
Model i ng I nput Dr i ve St r engt h
In order to accurately calculate the timing of an input
circuit, DC needs to know the transition time of the
signal arriving at the input port
set_driving_cell allows the user to specify a realistic
external cell driving the input ports
By default, DC assumes that the external signal has a transition
time of 0
Placing a driving cell on the input ports causes DC to calculate
the actual (non-zero) transition time on the input signal as
though the specified library cell was driving it
6-9
set _dr i vi ng_c el l Ex ampl es
dc_shell-t> set_driving_cell -lib_cell and2a0 \
[get_ports IN1]
ND2
IN1
TO_BE_SYNTHESIZED
6-10
Var i at i ons i n Cel l Del ays
Library cells are usually characterized using nominal
voltage and temperature:
What if the circuit is to operate at a voltage
and/or temperature OTHER than nominal?
nom_process : 1.0;
nom_temperature : 25.0;
nom_voltage : 1.8;
6-11
best
nominal
worst
Process
Delay
Delay
Voltage
worst
nominal
best
Temperature
worst
nominal
best
Delay
Oper at i ng Condi t i ons
Vendors allow for synthesis of circuits which will not
operate under nominal conditions by embedding
operating condition models in the technology libraries
Operating conditions can be placed on your design by
using the set_operating_conditions command
During synthesis, nominalcell and wire delays will be scaled
based on the operating conditions
6-12
Operating Conditions:
Name Library Process Temp Volt
----------------------------------------------------
typ_25_1.80 my_lib 1.00 25.00 1.80
slow_125_1.62 my_lib 1.00 125.00 1.62
fast_0_1.98 my_lib 1.00 0.00 1.98
Def aul t Oper at i ng Condi t i ons
By default, NO operating conditions are specified for a
design
Use report_lib libname to list the vendor-supplied
operating conditions
dc_shell-t> set_operating_conditions -max slow_125_1.62
quotes are optional
To set operating conditions, enter
6-13
Mul t i pl e Tec hnol ogy Li br ar i es
dc_shell-t> set_min_library ssc_core_slow
-min_version ssc_core_fast
dc_shell-t> set_operating_conditions -max slow_125_1.62 \
-min fast_0_1.98
set_min_library max_library -min_version min_library
Syntax:
Example:
Cannot use -min without -max
ASIC vendors might deliver multiple technology libraries,
defining:
best-case and worst-case operating conditions
optimistic and pessimistic WLM
minimum and maximum timing delay
6-14
Net del ays
Prior to layout, how
can the RC delay of
nets be estimated?
Receiving Gates
I/O Pad Driver
RAM
6-15
What I s a Wi r e Load Model ?
A wire load model is an estimate of a nets RC parasitics
based on the nets fanout:
Model is created by your vendor
Estimates are based on statistics from other designs the vendor
has fabricated using this process
6-16
Wi r e Load Model : St andar d For mat
Name : 160KGATES
Location : ssc_core_slow
Resistance : 0.000271
Capacitance : 0.00017
Area : 0
Slope : 50.3104
Fanout Length
---------------------------------
1 31.44
2 81.75
3 132.07
4 182.38
5 232.68
Example: Standard Format
R per unit length
C per unit length
Extrapolation slope
Time Unit : 1ns
Capacitive Load Unit : 1.000000pf
Pulling Resistance Unit : 1kilo-ohm
6-17
Spec i f yi ng Wi r e Loads i n Desi gn Compi l er
dc_shell-t> set current_design addtwo
dc_shell-t> set_wire_load_model -name 160KGATES
Manual model selection
Automatic model selection
Selection Wire load name
min area max area
-------------------------------------------
0.00 43478.00 5KGATES
43478.00 86956.00 10KGATES
86956.00 173913.00 20KGATES
173913.00 347826.00 40KGATES
347826.00 695652.00 80KGATES
Definition from report_lib:
dc_shell-t> set auto_wire_load_selection true
6-18
Wi r el oad Model Mode
mode = enclosed
WLM_SUB
TOP
B1 B2
SUB
dc_shell-t> set_wire_load_mode enclosed
Specifies wire load model to use for nets that cross
hierarchical boundaries.
mode = top
SUB
B2
TOP
B1
WLM_TOP
Example:
less pessimistic mode
6-19
a
Chec k Your Const r ai nt s
check_design
report_port -v
report_design
report_clock
write_script
check_timing
6-20
Commands f or Dat a Removal
You have several useful commands for libraries and
designs:
reset_design Erases all attributes and constraints from design
remove_design -design Removes designs from Design Compiler memory
remove_design -all Removes designs and libraries from DC memory
6-21
Li st Commands
list_files Lists all files in DC memory
list_designs Lists all design names in DC memory
list_lib Lists all libraries in DC memory
list_license Lists all licenses uses by this shell
6-22
Create a default script file which can be applied to each
subblock of a large ASIC, using the following specifications:
Ex er c i se: Desc r i be t he Envi r onment
Clock Speed
Input logic use 40% of clock period
Output logic use 40% of clock period
Operating at 85! !! !C and 1.6 volts
Wireload Model
Cell driving inputs
Output have to drive 5 pF
125 MHz
3.2 ns
3.2 ns
oc_85_16
40KGATES
inv1a0
5 pF
6-23
.
Sc r i pt Fi l e: Desc r i be t he Envi r onment
reset_design
# Environment
# Timing
6-24
LAB
Apply Environmental Constraints
30 min
mapped
PC.db
unmapped
prgrm_attr.db
Save the design
Inspect the design
Bring in the design
6-25
Appendi x
Create an Operating Condition
6-26
Cr eat e Your Ow n Oper at i ng Condi t i ons
You can create your own operating conditions
without a Library Compiler license if there are none
that satisfy your design requirements
library (extra) {
operating_conditions("SLOW") {
process : 1.75 ;
temperature : 100;
voltage : 1.60 ;
tree_type : worst_case_tree;}
}
After you create your own operating conditions, you
must compile them to make them available for use by
the Design Compiler
dc_shell-t> read_lib extra.lib
dc_shell-t> write_lib extra -output extra.db
dc_shell-t> set link_library * tech_library extra.db
dc_shell-t> set_operating_conditions SLOW -library extra
extra.lib:
7-1
Timing and Load Budgeting
Agenda: Day 2
DAY
2 22 2
Timing and Area 5
Topic Lab Unit
Timing Analysis 8
7-2
Create a timing budget for a design block
Use the set_max_capacitance command to limit
the input capacitance of a block
Budget the load on the output ports using the
set_load command
7-3
Area & Timing Goals
Simulate
OK?
Met
Constraints?
Analysis
Yes
Rewrite
Yes
Netlist
No
Major
Violations?
No
Yes
No
Write RTL
HDL Code
Synthesize
HDL Code
To Gates
7-4
Ti me Budget i ng
MY circuit
ckt X
D Q D Q
FF2
FF3
N X S
D Q
FF1
?
CLK
(100 MHz)
What if you dont know the delays on your
inputs or the setup requirements of your
outputs?
A: Create a Time Budget !
?
D Q
FF4
?
?
ckt Y
7-5
Ti me Budget i ng (c ont )
Better to budget conservatively
than to compile with paths unconstrained!
MY circuit circuit X
D
FF2
N
CLK
(100 MHz)
Q D
FF1
Q ? X
40% of clock
period
7-6
Ti me Budget i ng Ex ampl e
# A generic Time Budgeting script file
# for MY_BLOCK
create_clock -period 10 [get_ports CLK]
set_dont_touch_network [get_clocks CLK]
set_input_delay -max 6 -clock CLK [all_inputs]
remove_input_delay [get_ports CLK]
set_output_delay -max 6 -clock CLK [all_outputs]
D Q D Q
MY_BLOCK
FF2
FF3
N X S D Q
X_BLOCK
FF1
X S
D Q
Y_BLOCK
FF4
N X
4 4 10 10 10
DC still needs to consider delay of FF1 and setup of FF2
7-7
Ti me Budget i ng Ex ampl e (c ont )
# Time Budgeting script file
# for X_BLOCK and Y_BLOCK
set_input_delay -max 6 -clock CLK [all_inputs]
remove_input_delay [get_ports CLK]
set_output_delay -max 6 -clock CLK [all_outputs]
D Q D Q
FF2
FF3
N X S D Q
FF1
X S
D Q
FF4
N X
10 4 10 4 10
Would it be easier to specify a time budget if all
outputs were registered?
MY_BLOCK
X_BLOCK
Y_BLOCK
7-8
Load Budget i ng
MY_BLOCK
X_BLOCK
D Q D Q
FF2
FF3
N X S
D Q
FF1
?
A: Create a Load Budget!
?
D Q
FF4
?
?
Y_BLOCK
What if, prior to compiling, the cells driving your inputs,
and the loads on your outputs are not known?
Z_BLOCK
7-9
Q: What if, prior to compiling, the loads on your outputs,
and the cells driving your inputs are not known?
What if, prior to compiling, the loads on your outputs,
and the cells driving your inputs are not known?
How do we limit the input capacitance of an input port?
A: Place restrictive design rules on our input ports
Load Budget i ng (c ont )
A: Create a load budget
Assume a weak cell driving the inputs, to be
conservative
Limit the input capacitance of each input port
Estimate the number of other major blocks your outputs
may have to drive
7-10
Load Budget Ex ampl e
Example Specification:
Inputs of any block shall present no more than the load of
10 AND2 gates to their driving block
Outputs of any blocks will only be allowed to connect to a
maximum of 3 other blocks
Otherwise, output port will need to be replicated in code
1
2
3
10
Limit the load imposed
on driving block
Keep track of how many other
designers are using each output
Assume a weak
cell driving the
inputs
10x
10x
10x
10x
C
internal
C
external
7-11
Load Budget Ex ampl e (c ont )
current_design myblock
link
source timing_budget.tcl
# Assume a weak driving buffer on the inputs
set_driving_cell -lib_cell inv1a0 [all_inputs]
remove_driving_cell [get_ports Clk]
# Limit the input load
set MAX_INPUT_LOAD [expr [load_of(tech_lib/and2a0/A) * 10]]
set_max_capacitance $MAX_INPUT_LOAD [all_inputs]
remove_attribute max_capacitance [get_ports Clk]
# Model the max possible load on the outputs, assuming
# outputs will only be tied to 3 subsequent blocks
set_load [expr [$MAX_INPUT_LOAD * 3]] [all_outputs]
7-12
Ex er c i se: Desc r i be t he Envi r onment
Clock Speed
input / output ports use 40% of clock
Operating at 85 C and 1.6V
Wireload Model
Cell driving inputs
max input capacitance at input ports
Output drive no more than 4 blocks
125 MHz
3.2 ns
oc_85_45
40KGATES
inv1a0
10x pin A of buf1a0
4 blocks
Create a default script file which can be applied to each
subblock of a large ASIC, using the following specifications:
7-13
Sc r i pt Fi l e: Desc r i be t he Envi r onment
reset_design
# Environment
# Timing
7-14
Timing and Area Goals:
set_max_area set_input_delay
set_output_delay
create_clock set_dont_touch_network
Environmental Attributes:
set_driving_cell set_load
set_operating_conditions set_wire_load_model
Design Rules:
set_max_capacitance
Reports:
report_clock
report_port -verbose write_script
report_design
Problems?
reset_design remove_design
Summar y of Desc r i bi ng Const r ai nt s
7-15
LAB
Apply Timing and Load Budget
45 min
unmapped
PRGRM_CNT_TOP.db
Save the design
Inspect the design
Bring in the design
unmapped
prgrm_attr.db
8-1
Timing Anal ysis
Agenda: Day 2
DAY
2 22 2
Timing and Area 5
Topic Lab Unit
Timing Analysis 8
8-2
Timing Anal ysis
Generate a worst-case (maximum) timing report
Interpret a timing report to determine if you have
met timing constraints
Use a timing report to diagnose timing constraint
violations
8-3
Timing Anal ysis
Does Your Desi gn Meet I t s Goal s?
Use Timing Analysis!
Area & Timing Goals
Simulate
OK?
Met
Constraints?
Analysis
Yes
Rewrite
Yes
Netlist
No
Major
Violations?
No
Yes
No
Write RTL
HDL Code
Synthesize
HDL Code
To Gates
8-4
Timing Anal ysis
Ti mi ng Anal ysi s: What Tool Do I Use?
Design Compiler has a built-in static timing analyzer
called DesignTime
Design Anal yzer
DesignTime
Design Compiler
HDL Compiler VHDL Compiler
Verilog VHDL
8-5
Timing Anal ysis
D Q A
CLK
Z
Path 1
Path 3
Path 2
St at i c Ti mi ng Anal ysi s
Static Timing Analysis can determine if a circuit meets
timing constraints without dynamic simulation
This involves three main steps:
Design is broken down into sets of timing paths
The delay of each path is calculated
All path delays are checked to see if timing constraints have
been met
8-6
Timing Anal ysis
Ti mi ng Pat hs i n Desi gn Compi l er
DesignTime breaks designs into sets of signal paths
Each path has a startpoint and an endpoint
Startpoints:
Input ports
Clock pins of Flip-Flops or registers
Endpoints:
Output ports
Data input pins of sequential devices
D Q
QB
D Q
QB
FF1
FF2
MY_DESIGN
A
CLK
Z
8-7
Timing Anal ysis
Or gani zi ng Ti mi ng Pat hs i nt o Gr oups
D Q
QB
D Q
QB
FF2
FF3
MY_DESIGN
A
CLK1
CLK2
Z
path4
Paths are grouped by the clocks controlling their endpoints
The default path group contains all paths not captured by a clock
path1
CLK1
path2
CLK2
Timing Paths Path Groups
path1 path2 path3
DEFAULT
path3
path4
8-8
Timing Anal ysis
Ti mi ng Pat h Ex er c i se
How many timing paths do you see?
How many path groups are there?
CLK_1
CLK_2
8-9
Timing Anal ysis
Ti mi ng Pat h Ex er c i se
CLK_1
CLK_2
Clock Group 1
Clock Group 2
Default
Group
12 timing paths
3 path groups
8-10
Timing Anal ysis
Sc hemat i c Conver t ed t o a Ti mi ng Gr aph
To calculate total delay, Design Time breaks each path into
timing arcs
Each timing arc contributes either a net delay or cell delay
8-11
Timing Anal ysis
Component s of St at i c Ti mi ng Anal ysi s
What components are used in STA
path delay calculations?
Cell delay models
Linear and Nonlinear
Wire load models
Pre-layout estimates of wire parasitics: How
much R? How much C?
Interconnect models (R-C tree type)
How are R and C distributed?
Operating conditions
How are the delays affected by process,
voltage, and temperature?
D
e
s
ig
n
T
im
e
Look whats
under the hood of
this thing!
8-12
Timing Anal ysis
How Desi gnTi me Cal c ul at es Cel l Del ays
Cell delay model used by the technology library is
chosen by the Vendor
Cell delays are calculated using one of several cell
delay models:
Nonlinear Delay Model
Linear Delay Model
Others
8-13
Timing Anal ysis
Nonl i near Del ay Model
R
Cell
R
Net
C
Net
C
pin
input
transition
output
response
zero load
delay
D
Slope
+ D
Intrinsic
+ R
Cell
(C
Net
, C
Pin
)
f(T
Input
, R
Cell
, C
Net
, C
Pin
) + f(R
Net
, C
Net
, C
Pin
)
time-of-flight
WLM
cell delay from
2D table
intrinsic
delay
linear
delay
model
nonlinear
delay
model
8-14
Timing Anal ysis
Cel l Del ay: Nonl i near Del ay Model s
In the two-dimensional NLDM, output loading and input
transition affect the cell delay and output transition
Output transition becomes the next cells input transition
There are typically two NLDM tables per cell
0
0
10
20
I
n
p
u
t

T
r
a
n
s
i
t
i
o
n
Output Load (fF)
1 2 3
2
3
5
3
4.5
8
4
6
10.7
5
7
13
0
0
10
20
I
n
p
u
t

T
r
a
n
s
i
t
i
o
n
Output Load (fF)
1 2
1
2
4
10
13
16
18
25
39
Cell Delay (ps)
Output Transition
(vendor units)
Example:
Output load = 2 fF
Input transition = 10 units
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Cell Delay = 6 ps
Output Transition = 25 units
........ ........
8-15
Timing Anal ysis
Wi r e Del ay Cal c ul at i ons and Topol ogy
WLM determines the amount of R and C for a net
Tree-type determines R and C distribution for timing calculations
Interconnect delay (D
C
) is measured from state change at driver pin
to state change at each receiving cells input pin (same in every branch!)
best_case_tree
balanced_tree
worst_case_tree
Load adjacent to driver (net resistance is zero)
D
C
= 0
Each load pin shares equal portion of nets R and C
D
C
= ( R
net
/ N ) x ( C
net
/ N + C
pin
)
where N= fanout
Assume a lumped RC load
D
C
= R
net
x ( C
net
+ C
pins
)
Pessimistic
Default
Optimistic
R/2
C/2
R/2
C/2
R
C
8-16
Timing Anal ysis
Oper at i ng Condi t i ons
Operating Conditions:
Name Library Process Temp Volt Interconnect
---------------------------------------------------------------------
slow_125_1.62 ssc_core_slow 1.00 125.00 1.62 balanced_tree
slow_125_1.62_WCT ssc_core_slow 1.00 125.00 1.62 worst_case_tree
STA scales each cell and net delay based on process,
voltage, and temperature (PVT) variations
Tree type indicates which interconnect model to use
8-17
Timing Anal ysis
Edge Sensi t i vi t y i n Pat h Del ays
What is the longest path for the circuit below?
What is the shortest?
Cant we just add the longest delays and add the shortest delays?
There is an edge sensitivity (called unateness) in a
cells timing arc
DesignTime keeps track of unateness in each timing path
library: pin(Z)
intrinsic_rise : 1.2;
intrinsic_fall : 0.5;
library: pin(Z)
intrinsic_rise : 1.5;
intrinsic_fall : 0.3;
8-18
Timing Anal ysis
Set up Rel at i onshi p Bet w een Fl i p-Fl ops
The default behavior of Design Compiler is to assume that all
data must go from launch to capture edge in one clock cycle.
The path between FF1 and FF2 has a max delay constraint of
T
CLK
- FF2
libSetup
FF1 FF2
FF1
FF2
Default
setup check
Launch
Edge
Capture Edge
8-19
Timing Anal ysis
Desi gnTi me Ti mi ng Repor t s
Users will typically access DesignTime via the
report_timing command
The report_timing command
The design is broken down into individual timing paths
Each timing path is timed out twice;
once for a rising edge input, and
once with a falling edge input
The critical path (worst violator) for each clock group is
found
A timing report for each clock group is echoed to the
screen
A DesignTime timing report has four major sections
8-20
Timing Anal ysis
Ti mi ng Repor t : Pat h I nf or mat i on Sec t i on
****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : TT
Version: 2000.05
Date : Tue Aug 29 18:22:38 2000
****************************************
Operating Conditions: slow_125_1.62 Library: ssc_core_slow
Wire Load Model Mode: enclosed
Startpoint: data1 (input port clocked by clk)
Endpoint: u4 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
TT 5KGATES ssc_core_slow
8-21
Timing Anal ysis
Ti mi ng Repor t : Pat h Del ay Sec t i on
Point Incr Path
---------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 1.00 1.00 f
data1 (in) 0.00 1.00 f
u2/Y (inv1a1) 0.12 1.12 r
u12/Y (or2a1) 0.26 1.38 r
u23/Y (mx2d2) 0.23 1.61 f
u4/D (fdef1a1) 0.00 1.61 f
data arrival time 1.61
Running Total of
the Path Delay
Individual Contribution
to Path Delay
Total
Delay
Signal
Transition
Net & Cell Delays
0.0001
0.12
data1
Y
U2
U12
U23
D
U4
Time-of-flight
8-22
Timing Anal ysis
Point Incr Path
-----------------------------------------------
clock clk (rise edge) 5.00 5.00
U4/CLK (fdef1a1) 0.00 5.00
library setup time -0.19 4.81
data required time 4.81
Ti mi ng Repor t : Pat h Requi r ed Sec t i on
Clock Edge
Data must be valid
by this time
From the
Library
8-23
Timing Anal ysis
Ti mi ng Repor t : Summar y Sec t i on
------------------------------------------------
data arrival time -1.61
------------------------------------------------
slack (MET) 3.20
Timing margin (slack): negative
indicates constraint violation
Either (MET) or (VIOLATED)
0 1.61
CLK
Data
Required
Data
Arrival
4.81 5
Slack
8-24
Timing Anal ysis
Ti mi ng Repor t : Opt i ons
report_timing
[ -delay max/min ]
[ -to name_list ]
[ -from name_list ]
[ -through name_list ]
[ -input_pins ]
[ -max_paths path_count ]
[ -nets ]
...
Remember, the default behavior of report_timing is to
report the path with the worst slack within each path group
8-25
Timing Anal ysis
Ti mi ng Anal ysi s: Di agnose Synt hesi s Resul t s
u_int/U68/Q (INVB)
Incr Path
clock (input port clock) (rise edge)
0.00 0.00
addr31 (in) 0.00 22.40 f
u_proc/address31 (proc) 1.08 23.48 f
u_proc/u_dcl/int_add[7] (dcl) 0.00 23.48 f
u_proc/u_dcl/U159/Q (NAND3H) 0.62 24.10 r
u_proc/u_dcl/U160/Q (NOR3F) 0.75 24.85 f
u_proc/u_dcl/U186/Q (AND3F) 1.33 26.18 f
u_proc/u_dcl/U86/Q (INVF) 0.64 26.82 r
u_proc/u_dcl/U135/Q (NOR3B)
1.36 28.17 f
u_proc/u_dcl/U100/Q (NBF) 0.87 29.54 r
u_proc/u_dcl/U95/Q (BF) 0.44 29.98 f
u_proc/u_dcl/U96/Q (BF) 0.45 30.43 r
u_proc/u_dcl/ctl_rs_N (dcl) 0.00 32.21 r
u_proc/u_ctl/ctl_rs_N (ctl) 0.00 32.21 r
u_proc/u_ctl/U126/Q (NOR3B) 1.78 33.98 f
u_proc/u_ctl/U120/Q (NAND2B) 1.07 35.06 r
u_proc/u_ctl/U99/Q (NBF) 0.88 35.94 r
u_proc/u_ctl/U122/Q (OR2B) 10.72 46.67 r
u_proc/u_ctl/read_int_N (ctl) 0.00 46.67 r
u_proc/int_cs (proc) 0.00 46.67 r
u_int/readN (int) 0.00 46.67 r
u_int/U39/Q (NBF) 1.29 47.95 r
u_int/U17/Q (INVB) 1.76 49.71 f
u_int/U16/Q (AOI21F) 2.49 52.20 r
u_int/U60/Q (AOI22B) 1.43 53.63 f
1.81 55.44 r
u_int/int_flop_0/D (DFF) 0.00 55.44 r
Point
Spot the whales in the timing report: Where are they? What are they? And why?
Six buffers back
to back?!
Rather late arrival for
a 30 ns period!
11 ns delay for an OR
gate is not good
Four hierarchical
partitions
8-26
Timing Anal ysis
dc_shell> report_timing
****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : AM2910
Version: 1998.08
Date : Thu Feb 11 10:53:32 1999
****************************************
Operating Conditions: WCCOM
Library: lsi10k
Wire Loading Model Mode: top
Design Wire Loading Model Library
------------------------------------------------
AM2910 30x30 lsi10k
Startpoint: U3/OUTPUT_reg[12]
(rising edge-triggered Flip-Flop clocked by CLOCK)
Endpoint: U2/OUTPUT_reg[2]
Path Group: CLOCK
Path Type: max
dc_shell> report_timing
****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : AM2910
Version: 1998.08
Date : Thu Feb 11 10:53:32 1999
****************************************
Operating Conditions: WCCOM
Library: lsi10k
Wire Loading Model Mode: top
Design Wire Loading Model Library
------------------------------------------------
AM2910 30x30 lsi10k
Startpoint: U3/OUTPUT_reg[12]
Endpoint: U2/OUTPUT_reg[2]
Path Group: CLOCK
Path Type: max
Ti mi ng Repor t Ex er c i se
What type of startpoint does this
path have (input port or register?
What type of startpoint does this
path have (input port or register?
What type of endpoint does this
path have?
What type of endpoint does this
path have?
8-27
Timing Anal ysis
Point Incr Path
--------------------------------------------------
clock CLOCK (rise edge) 0.00 0.00
U3/OUTPUT_reg[12]/CP (FD1) 0.00 0.00 r
U3/OUTPUT_reg[12]/Q (FD1) 3.97 3.97 r
. . . . . . . . . .
U3/U148/Z (IV) 2.90 17.25 r
U3/ZERO (REGCNT) 0.00 17.25 r
U5/REGCNT_ZERO (CONTROL) 0.00 17.25 r
U5/U230/Z (ND2) 0.64 17.88 f
U5/U232/Z (XOR2) 2.77 19.65 f
U5/U236/Z (IVA) 1.75 21.15 r
U5/U193/Z (ND4) 1.38 22.53 f
U5/Y_CONTROL[1] (CONTROL) 0.00 22.53 f
U4/OPERATION[1] (Y) 0.00 22.53 f
U4/core/MUXOUT[1] (Y_core) 7.24 29.77 r
U4/MUXOUT[1] (Y) 0.00 29.77 r
U2/DATA[12] (UPC) 0.00 29.77 r
. . . . . . . . . .
U2/U62/Z (AN2) 1.92 38.90 f
U2/OUTPUT_reg[2]/D (FD1) 0.01 38.91 f
Point Incr Path
--------------------------------------------------
U3/OUTPUT_reg[12]/CP (FD1) 0.00 0.00 r
U3/OUTPUT_reg[12]/Q (FD1) 3.97 3.97 r
. . . . . . . . . .
U3/U148/Z (IV) 2.90 17.25 r
U3/ZERO (REGCNT) 0.00 17.25 r
U5/REGCNT_ZERO (CONTROL) 0.00 17.25 r
U5/U230/Z (ND2) 0.64 17.88 f
U5/U232/Z (XOR2) 2.77 19.65 f
U5/U236/Z (IVA) 1.75 21.15 r
U5/U193/Z (ND4) 1.38 22.53 f
U5/Y_CONTROL[1] (CONTROL) 0.00 22.53 f
U4/OPERATION[1] (Y) 0.00 22.53 f
U4/core/MUXOUT[1] (Y_core) 7.24 29.77 r
U4/MUXOUT[1] (Y) 0.00 29.77 r
U2/DATA[12] (UPC) 0.00 29.77 r
. . . . . . . . . .
U2/U62/Z (AN2) 1.92 38.90 f
U2/OUTPUT_reg[2]/D (FD1) 0.01 38.91 f
Ti mi ng Repor t Ex er c i se (c ont )
How many levels of
hierarchy does this
path traverse?
How many levels of
hierarchy does this
path traverse?
Do any cells appear
to have a relati vely
large delay?
Do any cells appear
to have a relati vely
large delay?
8-28
Timing Anal ysis
Ti mi ng Repor t Ex er c i se (c ont )
clock uncertainty 0.00 30.00
U2/OUTPUT_reg[2]/CP (FD1) 30.00 r
---------------------------------------------------------------
---------------------------------------------------------------
slack (VIOLATED) -9.71
clock uncertainty 0.00 30.00
U2/OUTPUT_reg[2]/CP (FD1) 30.00 r
---------------------------------------------------------------
---------------------------------------------------------------
slack (VIOLATED) -9.71
Does the path meet timing?
Does the path meet timing?
What is the percentage vi olation?
What is the percentage vi olation?
8-29
Timing Anal ysis
Summar y
clock period
slack
operating condition used
wire load model used
network delay
skew
setup/hold times
partitions
net delay
net names
Use report_timing to get detailed information
about the critical path:
9-1
DC Tcl - Introduction
Agenda: Day 2
DAY
2 22 2
Timing and Area 5
Topic Lab Unit
Timing Analysis 8
9-2
Use online help to determine the syntax of a
command
Define data types supported by DC-Tcl
Use DC-Tcl to assign a value to variables
Write a simple DC-Tcl script to automate common
DC tasks, including:
Reading in Designs
Constraining a Design
Compiling a Design
9-3
Ti r ed of Wor k i ng?
Man, I'm tired of sitting at
this terminal.
I sure wish I could have my
compile done automatically.
DC-Tcl
script!!
9-4
What i s Tc l ?
Tcl = Tool Command Language
An "open", industry-standard language
Developed at UCA Berkeley
Offers many powerful C-shell style features
References:
Tcl and the Tk Toolkit, J ohn K. Ousterhout
Practical Programming in Tcl and Tk, Brent B. Welch
Visual Tcl, David Young
www.scriptics.com
9-5
Why Tc l ?
Tcl is becoming an industry standard for tools
Tcl is more powerful than dc_shell
much more extensive online help
lists AND arrays are supported
user-defined procedures
case construct, string manipulation and comparison, file
manipulation
more
Synopsys tools that use Tcl for consistency:
Design Compiler
Formality
PrimeTime
Physical Compiler
Chip Architect, etc
9-6
Conver t i ng f r om dc _shel l t o dc _shel l -t
UNIX% dc-transcript my_script.scr my_script.tcl
For users who wish to migrate from " old" dc_shell to DC-Tcl,
an automated program has been written
Will convert most commands in existing scripts to Tcl
Only goes from DCSH to DC-Tcl
Called from the UNIX prompt
9-7
There are two ways to execute commands in DC-Tcl:
Interactively from DC-Tcl:
Execute from UNIX:
dc_shell-t> source my.tcl
dc_shell-t> source my.tcl
Ex ec ut i ng DC-Tc l Sc r i pt
UNIX% dc_shell-t -f my.tcl | tee my.log
UNIX% dc_shell-t -f my.tcl | tee my.log
UNIX% dc_shell-t -f my.tcl
UNIX% dc_shell-t -f my.tcl
UNIX% dc_shell-t -f my.tcl > my.log
UNIX% dc_shell-t -f my.tcl > my.log
9-8
Get t i ng Hel p
dc_shell-t> help
Procedures:
Builtins:
after, alias, append, apropos, array, break, catch,
cd, clock, close, concat, continue,
create_command_group, define_proc_attributes, echo,
eof, error, error_info, eval, exec, exit, expr,
fblocked, fconfigure,
. . .
Default Command Group:
add_module, add_to_collection, all_clocks,
all_cluster_cells, all_clusters, all_connected,
all_critical_cells, all_critical_pins, all_designs,
all_inputs, all_outputs, all_registers, analyze,
balance_buffer, balance_registers, bc_check_design,
. . .
dc_shell-t> help
Procedures:
Builtins:
after, alias, append, apropos, array, break, catch,
cd, clock, close, concat, continue,
create_command_group, define_proc_attributes, echo,
eof, error, error_info, eval, exec, exit, expr,
fblocked, fconfigure,
. . .
Default Command Group:
add_module, add_to_collection, all_clocks,
all_cluster_cells, all_clusters, all_connected,
all_critical_cells, all_critical_pins, all_designs,
all_inputs, all_outputs, all_registers, analyze,
balance_buffer, balance_registers, bc_check_design,
. . .
To Get a Basic Summary of all DC-Tcl Commands
9-9
Get t i ng Hel p (c ont )
dc_shell-t> help *clock
clock # Builtin
create_clock # create_clock
create_test_clock # create_test_clock
remove_clock # remove_clock
remove_propagated_clock # remove_propagated_clock
report_clock # report_clock
set_propagated_clock # set_propagated_clock
dc_shell-t> help *clock
clock # Builtin
create_clock # create_clock
create_test_clock # create_test_clock
remove_clock # remove_clock
remove_propagated_clock # remove_propagated_clock
report_clock # report_clock
set_propagated_clock # set_propagated_clock
Use a Wildcard to Find a Command
9-10
Mor e Hel p!
dc_shell-t> help -verbose set_input_delay
set_input_delay # set_input_delay
[-clock clock_name] (relative clock)
[-clock_fall] (delay is relative to falling edge of clock)
[-level_sensitive] (delay is from level-sensitive latch)
[-rise] (specifies rising delay)
[-fall] (specifies falling delay)
[-max] (specifies maximum delay)
[-min] (specifies minimum delay)
[-add_delay] (don't remove existing input delay)
delay_value (path delay)
port_pin_list (list of ports and/or pins)
Use help -verbose for command syntax information:
Use man command (from either the UNIX prompt or
dc_shell-t) for the entire UNIX manpage on a command
Use man command (from either the UNIX prompt or
dc_shell-t) for the entire UNIX manpage on a command
9-11
Comment s i n DC-Tc l
# Comments in Tcl are line-oriented
# If you wish to comment on the same line, be sure to use
# a semicolon before the comment:
set header_str Output Header; # Same line comment
# Comments in Tcl are line-oriented
# If you wish to comment on the same line, be sure to use
# a semicolon before the comment:
set header_str Output Header; # Same line comment
This semicolon is
required!
Comment a line in a DC-Tcl
script using the # character
9-12
Commands are nested using square brackets:
Nest i ng Commands and Quot i ng
dc_shell-t> set_output_delay 5 -clock CLK [all_outputs]
dc_shell-t> set_output_delay 5 -clock CLK [all_outputs]
Two ways of quoting text:
weak quoting with
dc_shell-t> set a 5
dc_shell-t> set s temp = data[$a]
temp = data[5]
dc_shell-t> set a 5
dc_shell-t> set s temp = data[$a]
temp = data[5]
rigid quoting with { }
dc_shell-t> set s {temp = data[$a]}
temp = data[$a]
dc_shell-t> set s {temp = data[$a]}
temp = data[$a]
9-13
Usi ng Wi l dc ar ds
Tcl supports two wildcard characters:
? will match exactly one character (PrimeTime only)
* will match zero to n characters
Examples:
dc_shell-t> help create*
dc_shell-t> set_input_delay 5 -clock CLK \
[get_ports BUS*]
9-14
Tc l Dat a Types
DC-Tcl supports the following data types:
Real
Integer
String
Lists
Collections
Tcl also supports arrays containing one or
more of these data types
9-15
Usi ng Var i abl es
Variables are created and assigned using the Tcl set
command
dc_shell-t> set my_var 10
dc_shell-t> set my_var 10
To reference a variable, it must be preceded with a $
To print variables
dc_shell-t> set my_New_Var $my_var
dc_shell-t> set my_New_Var $my_var
To remove variables
dc_shell-t> echo $my_var
dc_shell-t> echo $my_var
dc_shell-t> unset my_var
dc_shell-t> unset my_var
9-16
Usi ng Var i abl es: Ex er c i se
dc_shell-t> set clock_period 10
10
dc_shell-t> echo clock_period
______________________
dc_shell-t> echo clock period = $clock_period
______________________
dc_shell-t> echo Frequency = 1/$clock_period
______________________
dc_shell-t> set clock_period 10
10
dc_shell-t> echo clock_period
______________________
dc_shell-t> echo clock period = $clock_period
______________________
dc_shell-t> echo Frequency = 1/$clock_period
______________________
What will be the result of executing the following commands?
9-17
dc_shell-t> set period 10.0
10.0
dc_shell-t> set freq [expr (1 / $period)]
0.1
dc_shell-t> echo Freq = [expr $freq * 1000] MHz
Freq = 100.0 MHz
dc_shell-t> set_load [expr [load_of cba_core/and2a0/A] * 5] \
[all_outputs]
dc_shell-t> set period 10.0
10.0
dc_shell-t> set freq [expr (1 / $period)]
0.1
dc_shell-t> echo Freq = [expr $freq * 1000] MHz
Freq = 100.0 MHz
dc_shell-t> set_load [expr [load_of cba_core/and2a0/A] * 5] \
[all_outputs]
necessary whitespace
Ar i t hmet i c Ex pr essi ons
Tcl is string-oriented
To evaluate arithmetic expressions, use the expr command
9-18
Usi ng Li st s i n dc _shel l -t
Lists are a component of Tcl
A list is one string, containing items separated by white space
dc_shell-t> set L1 {el1 el2 el3}
el1 el2 el3
dc_shell-t> echo $L1
el1 el2 el3
dc_shell-t> set Num_of_List_Elements [llength $L1]
3
dc_shell-t> set L1 {el1 el2 el3}
el1 el2 el3
dc_shell-t> echo $L1
el1 el2 el3
dc_shell-t> set Num_of_List_Elements [llength $L1]
3
dc_shell-t> set link_library {*}
*
dc_shell-t> lappend link_library tc6a.db opcon.db
* tc6a.db opcon.db
dc_shell-t> echo $link_library
* tc6a.db opcon.db
dc_shell-t> set link_library {*}
*
dc_shell-t> lappend link_library tc6a.db opcon.db
* tc6a.db opcon.db
dc_shell-t> echo $link_library
* tc6a.db opcon.db
9-19
Def i ni t i ons: Obj ec t s and At t r i but es
Recall that designs consist of objects
designs, cells, references, ports, pins, clocks, and nets
In order to keep track of circuit functionality and timing,
DC attaches many attributes to each of these objects
ports can have the following attributes:
direction driving_cell
max_capacitance others. . .
designs can have the following attributes:
area operating_conditions_max
max_area others
Standard Tcl data formats (lists, strings) are not
adequate to keep track of circuit elements and their
attributes!
9-20
Def i ni t i ons: Col l ec t i on & Col l ec t i on Handl e
Collection:
A set of design objects which DC internally stores and
refers to by a name, the collection handle
Collections are created by a get_ or all_ commands
Collection handle:
A handle, or pointer, to a collection
In order to keep track of circuit objects and their attributes,
DC-Tcl contains an extension to standard Tcl -- collections
9-21
Cr eat i ng Col l ec t i ons
get_cells # Create a collection of cells
get_clocks # Create a collection of clocks
get_designs # Create a collection of designs
get_libs # Create a collection of libraries
get_nets # Create a collection of nets
get_pins # Create a collection of pins
get_ports # Create a collection of ports
all_clocks # Create a collection of all_clocks
all_designs # Create a collection of all_designs
all_inputs # Create a collection of all_inputs
all_outputs # Create a collection of all_outputs
all_registers # Create a collection of all_registers
get_cells # Create a collection of cells
get_clocks # Create a collection of clocks
get_designs # Create a collection of designs
get_libs # Create a collection of libraries
get_nets # Create a collection of nets
get_pins # Create a collection of pins
get_ports # Create a collection of ports
all_clocks # Create a collection of all_clocks
all_designs # Create a collection of all_designs
all_inputs # Create a collection of all_inputs
all_outputs # Create a collection of all_outputs
all_registers # Create a collection of all_registers
Here is a partial list of DC-Tcl commands that create collections:
9-22
Col l ec t i ons Ar e Ref er enc ed by a Handl e
dc_shell-t> set mylist {a b hello world}
a b hello world
dc_shell-t> llength $mylist
4
dc_shell-t> set foo [all_inputs]
{"Clk", "Reset", "Crnt_Instrn[31]", ... "Crnt_Instrn[0]"}
dc_shell-t> llength $foo
1
dc_shell-t> echo $foo
_sel5
dc_shell-t> sizeof_collection $foo
34
dc_shell-t> query_objects $foo
dc_shell-t> set mylist {a b hello world}
a b hello world
dc_shell-t> llength $mylist
4
dc_shell-t> set foo [all_inputs]
dc_shell-t> llength $foo
1
dc_shell-t> echo $foo
_sel5
dc_shell-t> sizeof_collection $foo
34
dc_shell-t> query_objects $foo
Collection Handle
9-23
Mani pul at i ng Col l ec t i ons
dc_shell-t> help *collection*
add_to_collection # Add object(s)
compare_collections # compares two collections
copy_collection # Make a copy of a collection
filter_collection # Filter a collection, resulting
in a new collection
foreach_in_collection # Iterate over a collection
index_collection # Extract object from collection
remove_from_collection # Remove object(s) from a
collection
sizeof_collection # Number of objects in a
collection
sort_collection # Create a sorted copy of a
collection
dc_shell-t> help *collection*
add_to_collection # Add object(s)
compare_collections # compares two collections
copy_collection # Make a copy of a collection
filter_collection # Filter a collection, resulting
in a new collection
foreach_in_collection # Iterate over a collection
index_collection # Extract object from collection
remove_from_collection # Remove object(s) from a
collection
sizeof_collection # Number of objects in a
collection
sort_collection # Create a sorted copy of a
collection
9-24
Mani pul at i ng Col l ec t i ons (c ont )
Add objects to a collection using
add_to_collection
Remove objects from a collection using
remove_from_collection
dc_shell-t> set pci_ports [get_ports DATA*]
dc_shell-t> set pci_ports [add_to_collection $pci_ports \
[get_ports CTRL*]]
dc_shell-t> set all_inputs_except_clk \
[remove_from_collection [all_inputs]
[get_ports CLK]]
dc_shell-t> set pci_ports [get_ports DATA*]
dc_shell-t> set pci_ports [add_to_collection $pci_ports \
[get_ports CTRL*]]
dc_shell-t> set all_inputs_except_clk \
[remove_from_collection [all_inputs]
[get_ports CLK]]
9-25
Col l ec t i on Usage: Ex ampl e
# Constrain a design for timing, using a time budget
set CLK_PER 10.0; # clock period (ns)
set time_budget 40.0; # percentage of clock period
# allowed for input/output logic
# calculate intermediate variables
set IO_DELAY [expr ( (1-$time_budget/100.0) * $CLK_PER)]
set all_except_clk [remove_from_collection \
[all_inputs] [get_ports CLK] ]
# constrain the design for timing
create_clock -period $CLK_PER -name MY_CLOCK [get_ports Clk]
set_input_delay $IO_DELAY -max -clock MY_CLOCK \
$all_except_clk
set_output_delay $IO_DELAY -max -clock MY_CLOCK \
[all_outputs]
set CLK_PER 10.0; # clock period (ns)
set time_budget 40.0; # percentage of clock period
# allowed for input/output logic
set IO_DELAY [expr ( (1-$time_budget/100.0) * $CLK_PER)]
[all_inputs] [get_ports CLK] ]
create_clock -period $CLK_PER -name MY_CLOCK [get_ports Clk]
$all_except_clk
[all_outputs]
9-26
Fi l t er i ng Col l ec t i ons
Use the filter_collection command
Use -filter option
filter_collection [get_cells] ref_name == AN2
filter_collection [get_cells] ref_name == AN2
filter_collection [get_cells] is_mapped == true
filter_collection [get_cells] is_mapped == true
set fastclks [get_clocks -filter @period < 10]
set fastclks [get_clocks -filter @period < 10]
get_cells -filter @dont_touch == true
get_cells -filter @dont_touch == true
1
3
2
4
9-27
Runni ng dc _shel l -t I nt er ac t i vel y
Show the history of commands entered:
dc_shell-t> ___
Repeat last command:
dc_shell-t> ___
Execute command no. 7 from the history list:
dc_shell-t> ___
Execute the last report_ command:
dc_shell-t> ___
Show the history of commands entered:
dc_shell-t> ___
Repeat last command:
dc_shell-t> ___
Execute command no. 7 from the history list:
dc_shell-t> ___
Execute the last report_ command:
dc_shell-t> ___
What are the commands for these tasks?
Name common UNIX commands can you run in dc_shell-t?
dc_shell-t> ___ ; ___ ; ___
dc_shell-t> ___ ; ___ ; ___
9-28
LAB
Create two generic Tcl scripts
60 min
constraints.tcl runit.tcl
create_clock
set_input_delay
. . .
read_db ...
source constraints.tcl
compile
report_constraint
write . . .
unmapped
PRGRM_CNT_TOP.db
10-1
Timing Revisited
Agenda: Day 3
DAY
3 33 3
Timing Revisited 10
Topic Lab Unit
Optimization 11
Compile Strategies 12
DC Tcl - Procedures 14
Compiling a Hierarchical Design 13
10-2
Timing Revisited
Model non-ideal clock effects
Create and use virtual clocks
Constrain a multiple clock design (synchronous clocks)
Constrain a multiple clock design (asynchronous clocks)
10-3
Timing Revisited
Area & Timing Goals
Simulate
OK?
Met
Constraints?
Analysis
Yes
Rewrite
Yes
Netlist
No
Major
Violations?
No
Yes
No
Write RTL
HDL Code
Synthesize
HDL Code
To Gates
10-4
Timing Revisited
Rec al l Ti mi ng Const r ai nt s Fr om Uni t 5
Method:
1. Define the clock
2. Define the I/O timing relative to the clock
( period)
( period )
( period )
set_input_delay set_output_delay
create_clock
create_clock
create_clock
D Q
QB
D Q
QB
D Q
QB
D Q
QB
Clk
TO_BE_SYNTHESIZED
FF1
FF2
FF3
FF4
M
N
X
S
T
10-5
Timing Revisited
Ti mi ng Goal s: Par t Tw o
Multiple Clocks - Synchronous
Multiple Clocks - Asynchronous
Modeling Real-Life Clocks
10-6
Timing Revisited
Model i ng Cl oc k Tr ees
Design Compiler is NOT used for synthesis of the clock tree.
Clock tree synthesis is usually done by the vendor, based on
physical placement data.
CLK
FF2
D Q D Q
FF1
D_In
Logical Circuit
CLK
FF2
D Q
D Q
FF1
D_In
Post-Layout Circuit
What design considerations need to be taken into
account by the synthesis tool, prior to layout?
10-7
Timing Revisited
Model i ng Unc er t ai nt y on Cl oc k Edges
To account for varying delays between the clock
network branches (commonly called clock skew):
T
U
CLK
FF2
D Q
D Q
FF1
D_In
Post-Layout Circuit
set_clock_uncertainty T
U
[get_clocks CLK]
Default clock skew is zero
placed on clock objects
10-8
Timing Revisited
set _c l oc k _unc er t ai nt y and Set up Ti mi ng
Example:
set_clock_uncertainty 0.5 [get_clocks CLK]
Max allowable
delay for block
X
FF1 Data Launch Edge
(No uncertainty!)
Assume lib
setup = 0.2ns
0 9.5 5 9.3 10
D
FF1
Q
D
FF2
Q
X
/ /
FF2 setup check at:
10 - 0.5 - 0.2 = 9.3
10-9
Timing Revisited
CLK
D Q
CLK
YOUR_DESIGN
Network Latency
Source Latency
Origin of Clock
create_clock -per 10 [get_ports CLK]
set_clock_latency -source 3 CLK
set_propagated_clock CLK
3ns 1ns
Model Sour c e Lat enc y
Source latency is the propagation time from the actual
clock origin to the clock definition point in the design
Use for either ideal or propagated clocks
10-10
Timing Revisited
Pr e/Post Layout Cl oc k
create_clock -p 30 -n MCLK Clk
set_clock_uncertainty 0.6 MCLK
set_clock_latency -source 4 MCLK
set_propagated_clock MCLK
pre-layout
post-layout
latency
uncertainty transition
[ jitter 0.2 + skew 0.4 ]
!"#$%
ideal clock
10-11
Timing Revisited
Mul t i pl e Cl oc k s: Sync hr onous
10-12
Timing Revisited
What do we do now?
What is different?
A: Multiple clock sources
All derived from the same clock source
Some clocks do not have a corresponding clock port
on our design
Multiple constraints on a single port
CLKA
CLKC
CLKB
CLKE
CLKD
D Q
QB
D Q
QB
TO_BE_SYNTHESIZED
FF2
FF3
N
X
S
Sync hr onous Mul t i pl e Cl oc k Desi gns
10-13
Timing Revisited
What are virtual clocks?
A: Clocks in the environment of the design to be
synthesized that:
Are defined clock objects within Design Compilers
memory
Do not clock any sequential devices within the
current_design
Serve as references for input or output delays
Answ er : Use Vi r t ual Cl oc k s!
10-14
Timing Revisited
Cr eat i ng a Vi r t ual Cl oc k
How do I create a virtual clock?
A: Its the same as defining a clock, but dont
specify a clock pin or port
You must name your virtual clock, since theres
no clock port for the virtual clock
Example:
create_clock -name vTEMP_CLK -period 20
No source pin or port!
Must be named
10-15
Timing Revisited
Ti mi ng Goal s f or Mul t i pl e Cl oc k Desi gns
Method is the same as that for single clock designs:
1. Define the clock(s), using virtual clocks if necessary
2. Specify I/O delays relative to the clock(s)
Design Compiler will determine which clock imposes the
most restrictive constraint on the design
CLKA
(33 Mhz)
CLKC
(50 Mhz)
CLKE
(100 Mhz)
CLKD
(75 Mhz)
D
TO_BE_SYNTHESIZED
FF2
FF3
N
X
S
300 MHz
CLKA
CLKD
& && &9
& && &4
Q D Q
CLKE
& && &3
& && &6
CLKC
10-16
Timing Revisited
Mul t i pl e Cl oc k I nput Del ay: Ex ampl e
create_clock -period 30 -name CLKA
create_clock -period 20 [get_ports CLKC]
set_dont_touch_network [get_clocks CLKC]
set_input_delay 5.5 -clock CLKA -max [get_ports IN1]
create_clock -period 30 -name CLKA
set_input_delay 5.5 -clock CLKA -max [get_ports IN1]
0.5 ns
CLK-Q
5.5 ns
TO_BE_SYNTHESIZED
IN1
CLKC
300
MHz
CLKC
CLKA
& && &9
& && &6
5 ns
N
t
N
10-17
Timing Revisited
For the example shown, input logic cloud of
TO_BE_SYNTHESIZED must meet:
t
N
< 10 - 5.5 - t
setup
CLKC
CLKA
0 10
20 30 40 50 60
10 ns
& && &6
300 MHz
CLKA
CLKC
& && &9
Example -Waveforms
Mul t i pl e Cl oc k I nput Del ay
10-18
Timing Revisited
Mul t i pl e Cl oc k Out put Del ay: Ex ampl e
create_clock -period [expr (1.0/75*1000)] -name CLKD
create_clock -period 10 -name CLKE
set_output_delay -max 2.5 -clock CLKD [get_ports OUT1]
set_output_delay -max 4.5 -clock CLKE -add_delay [get_ports OUT1]
2ns
4 ns
CLKD
0.5 ns
SETUP
4.5 ns
2.5 ns
0.5 ns
SETUP
CLKE
OUT1
TO_BE_SYNTHESIZED
CLKC
& && &4
300
MHz
CLKC
CLKD
CLKE
& && &6
& && &3
S
t
S
10-19
Timing Revisited
Mul t i pl e Cl oc k Out put Del ay
For the example shown, output logic cloud of
TO_BE_SYNTHESIZED must meet:
t
S
< 10 - 4.5
CLKC
CLKD
& && &4
300
MHz
CLKC
CLKD
CLKE
& && &6
& && &3
CLKE
0 10
20 30
40
t
S
< 6.7 - 2.5
AND
6.7
10
Example -Waveforms
10-20
Timing Revisited
Hi nt s f or Mul t i pl e Cl oc k Desi gns
By definition, all clocks used with Design Compiler
are synchronous
You can not create asynchronous clocks with the
create_clock command.
DC will determine every possible data launch/data
capture time, and synthesize to the most conservative
DC builds a common base period for all clocks
10-21
Timing Revisited
Mul t i pl e Cl oc k s: Async hr onous
10-22
Timing Revisited
Async hr onous Mul t i pl e Cl oc k Desi gns
CLKA
CLKC
CLKB
CLKE
CLKD
D Q
QB
D Q
QB
TO_BE_SYNTHESIZED
FF2
FF3
N
X
S
What do we do now?
What is different?
A: Multiple clock sources & sinks
All Asynchronous
Clocks do not have a corresponding clock
port on our design
10-23
Timing Revisited
Synt hesi zi ng w i t h Async hr onous Cl oc k s
It is the users responsibility to account for the
metastability
Instantiate double-clocking, metastable-hard Flip-Flops
dual-port FIFO
etc..
The user must then disable timing-based synthesis on
any path which crosses an asynchronous boundary
This will prevent DC from wasting time trying to get the
asynchronous path to meet timing
10-24
Timing Revisited
The set _f al se_pat h c ommand
How do we disable timing-based synthesis
for asynchronous paths?
A: Use the set_false_path command
A false path is a path for which we wish to ignore
timing constraints
set_false_path can be used to disable timing-
based synthesis on a path-by-path basis
Useful for:
Constraining asynchronous paths
Constraining logically false paths
10-25
Timing Revisited
current_design TOP
/* Make sure register-register paths meet timing */
create_clock -period 10 [get_ports CLKA]
create_clock -period 10 [get_ports CLKB]
/* Dont optimize logic crossing clock domains */
set_false_path -from [get_clocks CLKA] -to [get_clocks CLKB]
compile
set _f al se_pat h: Ex ampl e
CLKA
(100 Mhz
from OSC1)
CLKB
(100 Mhz
from OSC2)
D
N
X
Des_B Des_A Des_A
TOP
D
D
Q Q
Q
10-26
Timing Revisited
Ti mi ng Goal s Summar y
Exceptions to single-cycle
behavior:
set_false_path
Define input arri val
time relati ve to clock
set_input_delay
Define clock source
create_clock
set_dont_touch_network
Models skew on
clock source
set_clock_uncertainty
set_output_delay
Defines output timing
requirements
LOGIC CLOUD
LOGIC CLOUD
10-27
Timing Revisited
dc_shell-t> check_timing
dc_shell-t> check_timing
c hec k _t i mi ng
Paths which are not completely or properly
constrained may not appear in violation reports
Analysis should flag unconstrained paths so the
problems can be corrected, e.g., by adding
constraints
10-28
Timing Revisited
LAB
Add skew and run timing reports
45 min
Run timing reports
compile
mapped
PRGRM_CNT_TOP.db
constraints.tcl runit.tcl
Timing Report Timing Report Timing Report Timing Report
default pins nets min
10-29
Timing Revisited
Appendi x
Multicycle Paths
10-30
Timing Revisited
Mul t i -Cyc l e Behavi or
Choose one of the following options:
1. Add pipeline stage(s) to divide the logic into single-cycle paths
2. Ease off the single-cycle requirement: allow more clock cycles
CLK
FF4
SYSTEM_SYNCH_SET
DATA
64 x 64
MULTIPLIER
FF2 FF1
Situation: Not all paths operate at the target frequency of the design
10-31
Timing Revisited
dc_shell-t> set_multicycle_path 2 -from A -to B
setup check
default
hold
check
T
p
<delay <2T
p
2-cycle example
0 1 2
Ti mi ng Chec k s on Mul t i c yc l e Pat hs
The hold check is related to the setup check
The default hold check is one edge before the setup
10-32
Timing Revisited
Mul t i c yc l e Pat h: Ex ampl e
set_multicycle_path 2 -setup -from [get_cells FF1] -to [get_cells FF2]
CLK
FF1
FF2
FF3 FF4
BIG_LOGIC
AD
set_multicycle_path 1 -hold -from [get_cells FF1] -to [get_cells FF2]
We want Design Compiler to allow two clock cycles for BIG_LOGIC:
11-1
Optimization
Agenda: Day 3
DAY
3 33 3
Timing Revisited 10
Topic Lab Unit
Optimization 11
11-2
Optimization
List the three phases of optimization
List three architecture-level optimizations
List two types of logic-level optimizations
Identify the two gate-level optimizations
11-3
Optimization
Thr ee Phases of Opt i mi zat i on
Optimization can occur at each of three levels:
HDL Description
or unmapped db
mapped db
Optimized Netlist
Structure
Gate-Level
Logic-Level
Architectural
High-Level
Synthesis
& Flatten
Mapping
11-4
Optimization
Ar c hi t ec t ur al Opt i mi zat i on
HDL Description
or unmapped db
mapped db
Optimized Netlist
Structure
Gate-Level
Logic-Level
Architectural
& Flatten
Mapping
DesignWare Implementation
Selection
Sharing Common Subexpressions
Resource Sharing
Reordering Operators
11-5
Optimization
Ar i t hmet i c Oper at or s
For the code:
if (int0)
y <= busA + busB;
else
y <= busC + busD;
What type of circuit is implied by the + sign?
What type of adder should be synthesized?
How many adders will appear in the final circuit?
11-6
Optimization
Desi gnWar e I mpl ement at i on Sel ec t i on
Multiple architectures for each macro allow DC to evaluate
speed/area tradeoffs and choose the best implementation
HDL
Operator
+
smallest
fastest
Carry Look-Forward
Carry Look-Ahead
Ripple Carry
Z <= A + B;
Brent-Kung
Conditional
Sum Synthesis
DW
Foundation
DW
Basics
Ripple Carry Select
11-7
Optimization
Desi gnWar e Foundat i on
AND Gates,
OR Gates,
Flip-Flops...
Technology
Library
target_library
Adders,
Multipliers,
Comparators...
DesignWare
Library
synthetic_library
set synthetic_library dw_foundation.sldb
Hardcoding of {standard.sldb} is implicit to always
provide basic implementations of +, -, *, >=, <, <= etc
The synthetic_library variable points to a list of
synthetic library database files (.sldb):
11-8
Optimization
Ot her Hi gh-Level Opt i mi zat i ons
Sharing Common Subexpressions
Resource Sharing
Operator Reordering
11-9
Optimization
Shar i ng Common Sub-Ex pr essi ons
DC can share common mathematical sub-expressions
SUM1 <= A + B + C;
SUM2 <= A + B + D;
SUM3 <= A + B + E;
E
SUM1
A
+
+
B C
SUM2
A
+
+
B D
SUM3
A
+
+
B E
Implies
Share
SUM1
A
+
+
+ +
B C D
SUM2 SUM3
E
11-10
Optimization
Codi ng To For c e Shar i ng
Remember HDL coding can force a specific topology to
be synthesized
temp := A + B;
SUM1 <= temp + C;
SUM2 <= temp + D;
SUM3 <= temp + E;
To force a shared topology directly:
SUM1
A
+
+ + +
B C D E
SUM2 SUM3
11-11
Optimization
Resour c e Shar i ng: Ex ampl e
Given the following HDL
description, two different
structures might be
synthesized:
if (SEL = 1) then
SUM <= A + B;
else
SUM <= C + D;
end if;
Implied implementation:
+
+
SUM
A
B
C
D
SEL
+
A
C
B
D
SUM
SEL
More area-efficient implementation:
11-12
Optimization
*
+ -
> >= < <=
Resour c e Shar i ng
A resource is a DesignWare Component
The following HDL operators imply resources that
can be shared:
11-13
Optimization
Oper at or Reor der i ng
Design Compiler can automatically reorder arithmetic
operators to produce the fastest designs
Example:
Z <= A + B + C + D (where Z is time constrained)
+
+
+
A
B
C
D
Z
Initial ordering is left to right:
11-14
Optimization
Reor der i ng Oper at or s f or Fast Desi gn
If inputs arrive at the
same time, Design
Compiler will create
a balanced tree
architecture
If signal A is late
arriving, Design
Compiler may
reorder the
operators
+
+
+
Z
B
C
D
Late A
Remember: Coding style can force a particular order
Z = ( (B+C) + D) + Late_A;
+
+
+
A
B
C
D
Z
11-15
Optimization
Hi gh-Level Synt hesi s I s Const r ai nt -Dr i ven
High-level synthesis is based on design constraints and
coding style
Very important to specify realistic constraints
Design Compiler makes high-level synthesis decisions
to produce area-efficient results that meet timing
High-Level Synthesis takes place only when optimizing
an unmapped design
It will not occur when reoptimizing a gate-level netlist
EXCEPTION: DesignWare incremental implementation
selection can recur after mapping to gates
11-16
Optimization
Logi c -Level Opt i mi zat i on
Gate-Level
Logic-Level
Architectural-Level
HDL Description
or unmapped db
mapped db
High-Level
Synthesis
Mapping
Structure
Flatten
Optimized Netlist
11-17
Optimization
1. Structuring
2. Flattening
Logi c -Level Opt i mi zat i on (c ont )
After high-level optimization, circuit function is
represented by GTECH parts
Two optimization processes can occur during
Logic- Level optimization:
11-18
Optimization
What I s St r uc t ur i ng?
The use of intermediate terms to create a multilevel
implementation of a design that satisfies constraints
Useful for speed optimization as well as area optimization
This is the default logic-level optimization strategy
C
B
A
D
STR
11-19
Optimization
What I s Fl at t eni ng?
A
B
C
D
SOP
The reduction of combinational logic paths to a two-level,
sum-of-products (SOP) circuit
Useful for speed optimization; may be very area-intensive
set_flatten true -effort low | medium | high
11-20
Optimization
St r uc t ur i ng vs. Fl at t eni ng
A
B
C
D
Flattening
Removes intermediate structures
reduces design to SOP
Is done independent of constraints
Can be very area-intensi ve
No guarantee that flattening will
actually map to a two-level SOP
(possible library limitations)
vs.
C
B
A
D
Structuring
Creates intermediate structures
to implement design
Is constraint-based
Can help both area and speed of
a design
set_structure true | false set_flatten true | false
11-21
Optimization
Thr ee Phases of Opt i mi zat i on
Optimization can occur at each of three levels: Architectural, Logical, and Gate
Gate-Level
Logic-Level
Architectural-Level
Optimized Netlist
HDL Description
or unmapped db
mapped db
Phases of Gate-Level
Optimization:
1. Delay
2. DRC I
3. DRC II
4. Area
Structure
High-Level
Synthesis
& Flatten
Combinational
and Sequential
Mapping
11-22
Optimization
Combi nat i onal Mappi ng
The process of using gates from the target library to
generate a design that meets timing and area goals
g
A
B
C
A
B
A
SLOW
B
Q
A
B
C
G
F
g
A
B
A
B
A
B
SLOW
Q
C
G
F
A
B
C
11-23
Optimization
Sequent i al Mappi ng
Process by which Design Compiler maps to sequential
cells from the technology library
Tries to save speed and area by using a more complex
sequential cell
A
D
ENA
A
SEL
SEL
CLK
0
1
CLK
11-24
Optimization
Design Compiler tries to fix all
design rule violations without
affecting area or speed
If no other way can be found, Design
Compiler fixes design rule violations at the
expense of timing and area
Fi x i ng Desi gn Rul e Vi ol at i ons
Technology libraries contain vendor-specific
design rules for each cell, e.g. max_capacitance
During mapping, Design RuleConstraints (DRCs) are checked
Phases of Gate-Level Optimization:
1. Delay
2. DRC I
3. DRC II
4. Area
Design Compiler inserts buffers and resizes cells to correct
design rule violations
11-25
Optimization
Summar y
HDL Description
or unmapped db
mapped db
Structure
Gate-Level
Logic-Level
Architectural
High-Level
Synthesis
& Flatten
Mapping
Optimized Netlist
12-1
Compile Strategies
Agenda: Day 3
DAY
3 33 3
Timing Revisited 10
Topic Lab Unit
Optimization 11
12-2
Compile Strategies
Interrupt compilation
List the default priority of constraints
Enable DC to work harder on the critical path
Explain the difference between a compile and
an incremental compile
Fix hold time violations
12-3
Compile Strategies
Compi l e Compl et i on
Compile Completion
Compile Strategies
12-4
Compile Strategies
Compi l e Compl et e
Compiling stops when:
All constraints are met
Design Compiler reaches a point of
diminishing returns
User interrupt
12-5
Compile Strategies
User I nt er r upt
Please type in one of the following option:
1 to Write out the current status of the design
2 to Abort optimization
3 to Kill the process
4 to Continue optimization
Please enter a number:
Please type in one of the following option:
1 to Write out the current status of the design
2 to Abort optimization
3 to Kill the process
4 to Continue optimization
Please enter a number:
Typing a Ctrl-C during delay optimization will
result in the following menu appearing:
Pressing Ctrl-C three times kills the dc_shell process
12-6
Compile Strategies
Sum of all
timing
violations
Compi l e Repor t
Critical Path
timing violations
Beginning Delay Optimization Phase
----------------------------------
ELAPSED WORST NEG TOTAL NEG DESIGN
TIME AREA SLACK SLACK RULE COST ENDPOINT
--------- --------- ------- --------- --------- -------------------
0:10:04 2761.7 1.38 3.20 18.1 Zro_Flag_reg/D
0:10:05 2761.7 1.38 3.20 18.1 Zro_Flag_reg/D
0:10:08 2761.7 1.28 3.10 18.1 Zro_Flag_reg/D
0:10:12 2761.7 1.26 3.06 18.1 Zro_Flag_reg/D
12-7
Compile Strategies
Compi l e St r at egi es
Compile Completion
Compile Strategies
12-8
Compile Strategies
Const r ai nt and Ti mi ng Anal ysi s
You have performed a default compile.
The reports indicate remaining violations.
report_constraint -all_violators
Reports all constraints which have been violated in
the design
Includes design rules, setup, hold and area
report_timing -delay max
Reports the worst timing path for each path group
for setup time constraints
report_timing -delay min
Reports the worst timing path for each path group
for hold time constraints
good
starting
point
12-9
Compile Strategies
Thi ngs t o Look f or
How large is the worst negative slack (WNS)?
Do you have design rule violations?
Do you have hold time violations?
How many paths are violating timing?
During constraint / timing analysis, what should
you look for?
12-10
Compile Strategies
Bi g Vi ol at i ons
dc_shell> report_constraint -all
Information: Updating design information... (UID-85)
****************************************
Report : constraint
-all_violators
Design : RISC_CORE
Version: 1999.05
Date : Thu Nov 11 09:38:42 1999
****************************************
max_delay/setup ('Clk' group)
Required Actual
Endpoint Path Delay Path Delay Slack
---------------------------------------------------------------------------
RESULT_DATA[1] 1.20 2.84 r -1.64 (VIOLATED)
A rather big
violation
12-11
Compile Strategies
What Shoul d I Do Nex t ?
Check the constraints
Check the partition
Re-compile the optimized netlist
Re-compile using a higher effort
Change the HDL source code
12-12
Compile Strategies
Use Re-Compi l e
HDL
Optimized Netlist
Gate-Level
Logic-Level
Architectural
Entire design will be returned
to a GTECH representation
Logic-level optimization will be
performed
Gate-level optimization will be
performed
DesignWare Implementations
may still be changed
A successive compile will
probably not help, unless you
change something!
Modify the constraints
Change the set_structure or
set_flatten options
Change the map effort of
compile
dc_shell-t> compile
12-13
Compile Strategies
Controls how hard DC works on the critical path during
gate-level optimization
low:
Do NOT use for production work or as starting point for other
optimizations
medium:
Default
Should produce good results most of the time
high:
Activates additional algorithms
Very CPU intensive
Always start with medium compile effort
Change t he Ef f or t Level
compile -map_effort (low | medium | high)
12-14
Compile Strategies
St ar t f r om a Changed HDL Sour c e
Runs through all levels
of optimization
Takes changes in the
HDL source fully into
account
HDL
Optimized Netlist
Gate-Level
Logic-Level
Architectural
Caveat: The source code might
not be available or cannot be
changed anymore.
12-15
Compile Strategies
Smal l Vi ol at i ons
Information: Updating design information... (UID-85)
****************************************
Report : constraint
-all_violators
Design : RISC_CORE
Version: 1999.05
Date : Thu Nov 11 09:38:42 1999
****************************************
Required Actual
---------------------------------------------------------------------------
Assuming your
constraints and
partitions are correct,
what should you do?
12-16
Compile Strategies
Use I nc r ement al Mappi ng
Optimized Netlist
Gate-Level
Logic-Level
Architectural
compile -incremental_mapping
Only gate-level optimization is
done
The design is not taken back to
GTECH
No logic-level optimization
DesignWare Implementations
may still be changed
Incremental is much faster
than regular compile
12-17
Compile Strategies
I nc r ement al Mappi ng (c ont )
compile -inc -map high
Algorithm only accepts
solutions that reduce
critical path slack
The design will most likely
get better or stay the same
Optimized Netlist
Gate-Level
Logic-Level
Architectural
critical path
12-18
Compile Strategies
The set _c r i t i c al _r ange Command
set_critical_range 2 current_design()
This command causes DC to optimize all violating
paths within 2ns of the critical path
Very CPU and memory intensive. Use with caution!
timing
paths
2ns
12-19
Compile Strategies
When You Have Desi gn Rul e Vi ol at i ons
Design rule violations may cause timing violations
Use the following report commands
report_constraint -all_violators
report_net -connections -verbose
report_timing -net (for fanout)
D Q
QB
FF2
N
CLK
A
set_max_capacitance 0.1 A Added buffer to fix DR
compile -only_design_rule
D Q
QB
FF2
N
A
CLK
12-20
Compile Strategies
What i f You Have Hol d Ti me Vi ol at i ons?
My design works fine for
worst case conditions, but
when I check it for best
case, I have minimum
delay violations!
12-21
Compile Strategies
Hol d Ti me Vi ol at i ons
D Q
QB
D Q
QB
FF2
FF3
N
X
S
CLK
What is the minimum
delay requirement
from FF2 to FF3?
(assume 0.5 ns hold
requirement on FF3)
Hold
FF2/CLK
FF3/CLK
FF3/D VALID
0 0.5
12-22
Compile Strategies
Let s Compl i c at e t he Pi c t ur e
Hold time requirements are affected by
Skew on the clock tree network
Operating Conditions
What is the minimum
delay requirement now?
D Q
QB
D Q
QB
FF2
FF3
N
X S
CLK
0.5
Hold
FF2/CLK
FF3/CLK
FF3/D
0 0.5 1.0
VALID
FF Hold Time
12-23
Compile Strategies
Chec k i ng f or Hol d Ti me Vi ol at i ons
Typically, you will fix hold time violations after layout
Clock tree timing is not accurate until layout
Fixing phantomhold time violations may cause setup
violations and increase area
Often, pre-layout hold violations are fixedwhen real net
delays are used for hold time analysis
Best-Case operating conditions may assume zero net delay!
Sometimes you may need to fix hold time violations
before layout
12-24
Compile Strategies
Use Si mul t aneous Mi n-Max
Simultaneous Min-Max Optimization
Environment and timing constraints supported for BOTH
min and max values
Fixes hold time without violating setup time constraints
What constraints should you specify before
analyzing and fixing hold time violations?
Specify min and max technology library
set_min_library max_library -min_version min_library
set_clock_uncertainty -hold
set_input_delay -min
set_output_delay -min
set_operating_conditions -min -max
12-25
Compile Strategies
Appl y set _i nput _del ay f or Hol d Ti me
D Q D Q
D Q
QB
D Q
QB
Clk
TO_BE_SYNTHESIZED
FF1
FF2
FF3
FF4
M
N
X
S
T
set_input_delay -min describes the fastest arrival time
of the external logic on the input ports
set_input_delay -min 0.3 -clock Clk $all_in_ex_clk
set_input_delay -min 0.3 -clock Clk $all_in_ex_clk
min 0.3ns
If FF2 has T
HOLD
= 1ns:
What is the min delay allowed for N?
12-26
Compile Strategies
Appl y set _out put _del ay f or Hol d Ti me
D Q D Q
D Q
QB
D Q
QB
Clk
TO_BE_SYNTHESIZED
FF1
FF2
FF3
FF4
M
N
X
S
T
set_output_delay -min describes the hold time
requirement of the external logic on the output ports
0.3ns
0.5ns
Hold Time
Requirement
If FF has T
HOLD
= 0.5ns and T
T
= 0.3ns:
What is the min output delay?
12-27
Compile Strategies
Cal c ul at i on of set _out put _del ay
set_output_delay -min (0.3-0.5) -clock Clk [all_outputs]
D Q
D Q
QB
Clk
FF3
FF4
T S
set_output_delay -max (T
max
+ FF4
setup
)
set_output_delay -min (T
min
- FF4
hold
)
setup = 0.8
hold = 0.5
T
min
0.3ns
-0.2
12-28
Compile Strategies
Fi x i ng Hol d Vi ol at i ons
set_fix_hold [all_clocks]
By default, DC does NOT fix hold time violations
Use set_fix_hold to tell DC to fix hold time violations
Use compile -only_design_rule
DC only adds buffers or resizes cells
DC fixes only design rule and hold time violations
12-29
Compile Strategies
Summar y: Ex ampl e Sc r i pt
read_db Top_meetsSetup.db
source TimingConstraints_max.tcl
set_operating_conditions -max WORST -min BEST
set ALL_IN_EX_CLOCK [remove_from_collection \
[all_inputs] [get_ports Clk]]
set_input_delay -min 0.2 -clock Clk $ALL_IN_EX_CLOCK
set_output_delay -min -0.1 -clock Clk [all_outputs]
set_clock_uncertainty -hold 0.5 [get_clocks Clk]
# Fix min timing violations
redirect top.rpt {report_constraint -all_violators}
read_db Top_meetsSetup.db
source TimingConstraints_max.tcl
set_operating_conditions -max WORST -min BEST
set ALL_IN_EX_CLOCK [remove_from_collection \
[all_inputs] [get_ports Clk]]
set_input_delay -min 0.2 -clock Clk $ALL_IN_EX_CLOCK
set_output_delay -min -0.1 -clock Clk [all_outputs]
set_clock_uncertainty -hold 0.5 [get_clocks Clk]
# Fix min timing violations
redirect top.rpt {report_constraint -all_violators}
12-30
Compile Strategies
LAB
45 min
Practice
Optimization
Techniques
source
calculation.v
calculation.vhd
source
converter.v
converter.vhd
13-1
Compiling a Hierarchical Design
Agenda: Day 3
DAY
3 33 3
Topic Lab Unit
Optimization 11
Timing Revisited 10
13-2
List two methods of resolving multiple instances
List one advantage and one disadvantage of using
each method
13-3
Compi l i ng a Hi er ar c hi c al Desi gn
Resolving Multiple Instances
Compiling a Hierarchical Design-
Under The Hood
13-4
Compi l i ng a Hi er ar c hy
D_design
U1 U2
U3
Bdes
Y= A+B
Ades
Cdes
Y= A+B
Y= A+B
Designs in the hierarchy are mapped to gates in
two phases
13-5
Fi r st Phase of Compi l e
The first phase of compile maps all blocks to gates without
regard to constraints.
Hierarchy is Preserved
During a Compile
D_design
U1
U2
U3
Y=A+B
Y=A+B
Ades
Bdes
Cdes
D_design
U1 U2
U3
Y=A+B
Ades
Bdes
Cdes
D_design
U1 U2
U3
Ades
Bdes
Cdes
13-6
D_Design
U1
U2
U3
Bdes
Ades
Cdes
What if a design is instantiated more than once?
Sec ond Phase of Compi l e
During the second phase, Design Compiler
optimizes logic to meet timing and area constraints
fixes violations caused by the surrounding blocks
13-7
Resol vi ng Mul t i pl e I nst anc es
Resolving Multiple Instances
Compiling a Hierarchical Design-
Under the Hood
13-8
Desi gns I nst ant i at ed Mor e Than Onc e
In this example, Ades is used in two different locations
Only one copy of the Ades exists in DC memory
D_design
U1 U2
Bdes
Y=A+B
Ades
U3
Ades
Ades
Design Compiler Memory
Bdes
Y=A+B
Y=A+B
Y=A+B
Y=A+B
Which environmental attributes and constraints
should DC use for Ades during compile?
13-9
dc_shell-t> check_design
dc_shell-t> check_design
compile terminates if multiple instantiations are not resolved!
c hec k _desi gn
Returns warnings if your current design:
has multiple instantiations
has unconnected pins
13-10
Met hods t o Resol ve Mul t i pl e I nst anc es
1.uniquify
2.compile + dont_touch
You must resolve multiple instances using one of these methods!
D_design
U1 U2
Bdes
Y=A+B
Ades
U3
Ades
Ades
Bdes
Y=A+B
Y=A+B
Y=A+B
Y=A+B
13-11
Met hod #1: uni qui f y
uniquify makes a copy of each multiply-instantiated design
(one copy for each instance)
Each instance gets a unique design name
DC can now map each instance to its own specific environment
D_Design
U2
Bdes
Y=A+B
U3
Ades_1
Y=A+B
U1
Ades_0
Y=A+B
Bdes
Y=A+B
Ades_0
Y=A+B
Ades_1
Y=A+B
13-12
Met hod #1: uni qui f y (c ont )
D_Design
U2
Bdes
Y=A+B
U3
Ades_1
Y=A+B
U1
Ades_0
Y=A+B
current_design D_design
source D_constraints.tcl
uniquify
compile
13-13
Met hod 2: c ompi l e + dont _t ouc h
1. Constrain and compile Ades
2. Place a dont_touch attribute on the compiled Ades
3. Compile D_design
dont_touch
D_design
U1 U2
Bdes
Y=A+B
Ades
U3
Ades
Ades
Bdes
Y=A+B
Y=A+B
Y=A+B
Y=A+B
13-14
Met hod 2: c ompi l e + dont _t ouc h
read_db unmapped/A_des.db
current_design Ades
link
source Aconstraints.tcl
compile
read_db unmapped/D_design.db
set_dont_touch [get_designs Ades]
source Dconstraints.tcl
compile
read_db unmapped/A_des.db
current_design Ades
link
compile
read_db unmapped/D_design.db
compile U1 U2
Bdes
Y=A+B
Ades
U3
Ades
D_design
13-15
Usi ng set _dont _t ouc h
U1 U2
Bdes Ades
U3
Ades
D_design
set_dont_touch can be assigned to design objects
It prevents modification of that design object
Caution: If placed on an unmapped design, the design will
remain unmapped
To resolve the multiple instantiation, set_dont_touch
on the design Ades
Prevents any further optimization of instances U1 and U3
13-16
uniquify dont_touch
Which solution would be easier
to implement? _________ __________
Which could take more time to compile? _________ __________
Which would offer you better results? _________ __________
uni qui f y vs. c ompi l e + dont _t ouc h
D_design
U1 U2
Ades
Bdes
Ades
U3
D_design
U1 U2
U3
Ades Bdes
Ades
13-17
Summar y
Use uniquify unless you are concerned about:
compile run times (large blocks or tightly constrained blocks)
memory limitations (large blocks or many instances)
laying out the block only once
uniquify
compile
Method #1
Method #2
current_design Ades
compile
compile
13-18
LAB
45 min
unmapped
STACK_TOP.db
mapped
STACK_TOP_
UNIQUIFY.db
uniquify
mapped
STACK_TOP_
DONT_TOUCH.db
dont_touch
14-1
DC Tcl - Procedures
Agenda: Day 3
DAY
3 33 3
Timing Revisited 10
Topic Lab Unit
Optimization 11
14-2
DC Tcl - Procedures
Use Tcl commands to build loops and control
flows
Write procedures for a DC-Tcl script for
constraining a design
14-3
DC Tcl - Procedures
Cont r ol Fl ow : Ex ampl es
if [file exists My_Design.db] {
read_db My_Design.db
} else {
echo Could not read My_Design.db
}
if [file exists My_Design.db] {
read_db My_Design.db
} else {
echo Could not read My_Design.db
}
set FTYPE [file type My_Design.db]
switch $FTYPE {
file {read_db My_Design.db}
link {echo db file is a symbolic link}
default {echo File is not a valid type for reading}
}
set FTYPE [file type My_Design.db]
switch $FTYPE {
file {read_db My_Design.db}
link {echo db file is a symbolic link}
default {echo File is not a valid type for reading}
}
must be on same line as else!
14-4
DC Tcl - Procedures
Loopi ng St r uc t ur es
# foreach loop example - iterates over
# elements of a list:
set MYlist {Hello World}
foreach list_element $MYlist {
echo $list_element
}
# foreach loop example - iterates over
# elements of a list:
set MYlist {Hello World}
foreach list_element $MYlist {
echo $list_element
}
# while loop example
set idx 0
set clk_per 10.0
# Create divided clocks on ports CLK0 - CLK9
while {$idx < 10} {
create_clock -period $clk_per [get_ports CLK$idx]
incr idx
set clk_per [expr (2 * $clk_per)]
}
# while loop example
set idx 0
set clk_per 10.0
# Create divided clocks on ports CLK0 - CLK9
while {$idx < 10} {
create_clock -period $clk_per [get_ports CLK$idx]
incr idx
set clk_per [expr (2 * $clk_per)]
}
Results shown in the Notes section
14-5
DC Tcl - Procedures
I t er at i ng over a Col l ec t i on: Ex ampl e
read_db mapped/PRGRM_CNT_TOP.db
set CellColl [get_cells *]
set Count 1
# Print a list of all cells in the Design
foreach_in_collection SingleCell $CellColl {
set CellName [get_object_name $SingleCell]
echo Cell $Count is $CellName
incr Count
}
read_db mapped/PRGRM_CNT_TOP.db
set CellColl [get_cells *]
set Count 1
# Print a list of all cells in the Design
foreach_in_collection SingleCell $CellColl {
set CellName [get_object_name $SingleCell]
echo Cell $Count is $CellName
incr Count
}
Results shown in the Notes section
14-6
DC Tcl - Procedures
Tc l Pr oc edur es
Tcl allows the user to write their own built-in
commands
Commands are written using a Tcl procedure
Powerful capabilities of procedures:
Allow you to define your own commands
Allow any number of arguments
user can define default values
Can have variable number of arguments
14-7
DC Tcl - Procedures
Tc l Pr oc edur e Synt ax
proc CALC_PERIOD {Clock_Freq} {
# Convert clock frequency (Mhz) to period (ns)
return [expr ( (1.0 / $Clock_Freq) * 1000)]
}
proc CALC_PERIOD {Clock_Freq} {
}
dc_shell-t> source myproc.tcl
dc_shell-t> CALC_PERIOD 125.0
8.0
dc_shell-t> create_clock \
-period [CALC_PERIOD 125.0] \
[get_ports Clk]
dc_shell-t> source myproc.tcl
dc_shell-t> CALC_PERIOD 125.0
8.0
dc_shell-t> create_clock \
-period [CALC_PERIOD 125.0] \
[get_ports Clk]
myproc.tcl
necessary whitespace same line
14-8
DC Tcl - Procedures
Sc ope of Var i abl es
Variables created in a procedure only live for the
duration of the procedure, (local scope)
Any variable defined outside any procedure is a
global variable
Global variables are not visible to a procedure
unless the global scope keyword is used when
defining the variables in the procedure
dc_shell-t> proc SP {} {
global search_path
set search_path $search_path ./scripts
}
dc_shell-t> SP
dc_shell-t> echo $search_path
{... slow_core.db ./scripts}
dc_shell-t> proc SP {} {
global search_path
set search_path $search_path ./scripts
}
dc_shell-t> SP
dc_shell-t> echo $search_path
{... slow_core.db ./scripts}
14-9
DC Tcl - Procedures
Pr oc edur e I nf or mat i on
Display the procedures in memory
Display the contents of a procedure
dc_shell-t> info procs
. . . CALC_PERIOD
dc_shell-t>
dc_shell-t> info procs
. . . CALC_PERIOD
dc_shell-t>
dc_shell-t> info body CALC_PERIOD
dc_shell-t>
dc_shell-t> info body CALC_PERIOD
dc_shell-t>
14-10
DC Tcl - Procedures
Tc l Pr oc edur e: Ex ampl e
proc TimeBudget {clock_freq time_budget} {
# clock_freq <real> clock frequency in Mhz
# time_budget <real> percentage of clock period allowed
# for delay of input/output logic
# in design being constrained
set CLK_PER [expr ((1/$clock_freq) * 1000)]
set MY_IO_CONSTRAINT [expr ($CLK_PER*($time_budget/100.0)) ]
set IO_DELAY [expr ($CLK_PER - $MY_IO_CONSTRAINT)]
[all_inputs] [get_ports Clk*] ]
procs.tcl
14-11
DC Tcl - Procedures
Tc l Pr oc edur e: Ex ampl e (c ont )
# create clock on clock port
create_clock -period $CLK_PER -name MY_CLOCK \
[get_ports Clk*]
# constrain the inputs
$all_except_Clk
# constrain the outputs
[all_outputs]
}; # end of TimeBudget
14-12
DC Tcl - Procedures
Tc l Pr oc edur e: Ex ampl e (c ont )
source procs.tcl
read_db PRGRM_CNT_TOP.db
current_design PRGRM_CNT_TOP
# constrain design for Timing
# using a clock period of 100 Mhz
# and 40% of the clock period for IO timing
TimeBudget 100.0 40.0
# constrain design for environmental attributes
14-13
DC Tcl - Procedures
LAB
Create two generic Tcl procedures
30 min
myprocs.tcl runit.tcl
proc TimeBudget
proc LoadBudget
read_db ...
TimeBudget
LoadBudget
compile
report_constraint
write...
unmapped
PRGRM_CNT_TOP.db
14-14
DC Tcl - Procedures
Chec k f or er r or s
check_error -verbose
check_error -reset
dc_shell-t> check_error -reset
dc_shell-t> source my_script.tcl
dc_shell-t> check_error -v
0
dc_shell-t>
0
dc_shell-t>
{CMD-010}
dc_shell-t> error_info
{CMD-010}
dc_shell-t> error_info
15-1
Compiling a Large Design
Compiling a Large Design 15
Topic Lab Unit
Design Exploration 16
Synthesizing for Test 17
Conclusion 18
Agenda: Day 4
DAY
4 44 4
15-2
Execute a top-down compile
Execute a bottom-up compile
Determine a second-pass compile strategy
Execute the characterize command
15-3
Tec hni ques f or Compi l i ng a Hi er ar c hi c al Desi gn
Techniques for Compiling a
Hierarchical Design
Techniques for the
Second-Pass Compile
characterize
15-4
Hi er ar c hi c al Compi l e Tec hni ques: Types
There are two strategies for compiling a large
hierarchical design:
Top-down
Bottom-up
15-5
Top-Dow n Compi l e Met hodol ogy
1. Read in the entire design
2. Resolve multiple instances
3. Apply top-level constraints
4. Compile
5. Assess results
6. Save design
top-down.tcl
analyze -format vhdl {alu.vhd reg_file.vhd ... risc_core.vhd }
elaborate RISC_CORE
uniquify
source scripts/top_level.tcl
compile
report_constraint -all
write -format db -hierarchy -output mapped/RISC.db
quit
PRGRM_CNT_TOP
RISC_CORE
ALU
DATA_PATH
INSTRN_LAT
STACK_TOP
REG_FILE
15-6
Advant ages of Top-Dow n
" push-button" approach
Intermodule dependencies are taken care of
automatically
Fewer man-hours spent driving the tool
Most productive approach when practical
15-7
analyze -format vhdl {alu.vhd... risc_core.vhd}
elaborate RISC_CORE
source scripts/top_level.tcl
/* Do NOT execute uniquify */
set_simple_compile_mode true
compile
set_simple_compile_mode false
Si mpl e Compi l e Mode
For designs without aggressive timing constraints
Run time can be reduced
Multiple instantiations are mapped once during compile
At the end of optimization, you get an automatically
uniquified netlist
15-8
Hi er ar c hi c al Compi l e Tec hni ques
There are two strategies for compiling a large
hierarchical design:
Top-down
Bottom-up
15-9
Bot t om-Up Compi l e Met hodol ogy
REG_FILE
1. Constrain and compile
subblocks independently
2. Make sure all subblocks
meet their initial
constraints
3. Read in the entire
compiled design and
apply top-level
constraints
4. Check constraint report:
if your design passes,
youre are done!
ALU PRGRM_CNT_TOP
. . .
RISC_CORE
15-10
analyze -format vhdl {PRGRM_CNT.vhd ... PRGRM_CNT_TOP.vhd}
elaborate PRGRM_CNT_TOP
compile
report_constraint -all > reports/PRGRM_CNT_TOP.rpt
/* MAKE SURE timing has been met! If not, recode or recompile */
write -format db -hier -output mapped/PRGRM_CNT_TOP.db
analyze -format vhdl {PRGRM_CNT.vhd ... PRGRM_CNT_TOP.vhd}
elaborate PRGRM_CNT_TOP
compile
report_constraint -all > reports/PRGRM_CNT_TOP.rpt
/* MAKE SURE timing has been met! If not, recode or recompile */
write -format db -hier -output mapped/PRGRM_CNT_TOP.db
Bot t om-Up Compi l e Met hodol ogy
Compile each subblock to meet their respective budget
15-11
Bot t om-Up Compi l e Met hodol ogy (c ont )
read_vhdl source/RISC_CORE.vhd
/* Bring in compiled .db files */
link
/* SYSTEM-LEVEL Constraints */
source Top_level.tcl
/* Check for timing violations */
report_constraint -all > reports/RISC_CORE.rpt
write -format db -hier -output mapped/RISC_CORE.db
read_vhdl source/RISC_CORE.vhd
/* Bring in compiled .db files */
link
/* SYSTEM-LEVEL Constraints */
source Top_level.tcl
/* Check for timing violations */
report_constraint -all > reports/RISC_CORE.rpt
write -format db -hier -output mapped/RISC_CORE.db
Perform top-level integration and constraint analysis
15-12
Pr os & Cons of Bot t om-Up Compi l e
Large designs are compiled with the divide and
conquer approach
Not limited by available memory
Advantages:
May require iterations until block-to-block
interfaces are stable
Requires careful revision control
Disadvantages:
15-13
Summar y
Use top-down for smaller designs
Use bottom-up for all other designs
An overnight compile is considered a reasonable
compile run time
Make time and load budgets as accurate and
conservative as possible
15-14
Tec hni ques f or t he Sec ond-Pass Compi l e
Hierarchical Design
Techniques for the
Second-Pass Compile
characterize
15-15
Pr obl ems Af t er t he Fi r st -Pass Compi l e
What if there were still timing violations after the
first-pass top-down compile?
What if there were timing violations during top-level
integration after the bottom-up compile?
RISC_CORE
ALU
CONTROL
DATA_PATH
PRGRM_CNT_TOP
15-16
Use r epor t _c onst r ai nt -al l
***************************
Report : constraint
-all_violators
Design : RISC_CORE
Version: 1999.05
Date : Fri Nov 12 11:57:30 1999
***************************
Required Actual
----------------------------------------------------------------------
I_ALU/Zro_Flag_reg/D0 9.34 10.78 r -1.44 (VIOLATED)
I_ALU/Neg_Flag_reg/D0 9.31 10.39 f -1.09 (VIOLATED)
I_ALU/Lachd_Result_reg[15]/D0 9.31 10.31 f -1.00 (VIOLATED)
OUT_VALID 1.20 2.16 r -0.96 (VIOLATED)
I_ALU/Lachd_Result_reg[14]/D0 9.31 9.89 f -0.59 (VIOLATED)
The violationis roughl y 15% of
the timing constraints.
15-17
Use r epor t _t i mi ng
Point Incr Path
--------------------------------------------------------------------------
clock Clk (rise edge) 0.00 0.00
I_DATA_PATH/Oprnd_B_reg[3]/CLK (fdmf1a2) 0.00 0.00 r
I_DATA_PATH/Oprnd_B_reg[3]/Q (fdmf1a2) 0.85 0.85 f
I_DATA_PATH/Oprnd_B[3] (DATA_PATH) 0.00 0.85 f
I_ALU/Oprnd_B[3] (ALU) 0.00 0.85 f
I_ALU/add_72/plus/A[3] (ALU_DW01_add_16_1) 0.00 0.85 f
I_ALU/add_72/plus/U124/Y (inv1a0) 0.34 1.19 r
I_ALU/add_72/plus/U79/Y (inv1a2) 0.32 1.51 f
I_ALU/add_72/plus/U180/Y (nor2a2) 0.20 1.71 r
I_ALU/U564/Y (ao3e1) 0.60 9.61 r
I_ALU/U509/Y (mx2d2) 0.28 9.89 f
I_ALU/Lachd_Result_reg[14]/D0 (fdm1a1) 0.00 9.89 f
All of the combinational logic causing the

violation is full y contained in ALU.
15-18
Nex t St eps
A more aggressive second-pass top-down compile
compile -incremental -map_effort high
Compile only top-level violations
Check the partitions
Build a new design budget for the design ALU
15-19
Compi l e onl y Top-Level Vi ol at i ons
compile -top
Fixes timing violations on top-level paths only
Less memory and CPU intensive than a top-level
compile -incremental
A good compile strategy to fix integration problems due to
small discrepancies in design budgets
What if after bottom-up compile we have timing
violations at the top-level?
15-20
Chec k Your Par t i t i ons
PRGRM_CNT
DATA_PATH
ALU
CONTROL
data_bus
32
30 k gates
100 k gates
Glue
5 k
20 k gates
RISC_CORE
40 k gates
How would you compile this design?
15-21
Top-Level Par t i t i ons
Compile top-down on as large a design as is reasonable
for compile run times and floorplan issues
Motivation: Often produces better results in less time than a design
budgeting/bottom-up strategy
Partition at register outputs for timing-critical paths and
major hierarchical blocks
Generating design budgets is greatly simplified
Design Compiler will not optimize logic across hierarchical
boundaries
To repartition change your HDL source or use group/ungroup.
15-22
How can we automate the process of
generating new design budgets?
Bui l d a New Desi gn Budget
Design Budgeting!
Tighten the budget for time, load, and drive budgets
for each block to meet
Compile each block to meet that budget
Integration at top level should cause no problems if:
All blocks compiled and met their budget
Budget was accurate and sufficiently constrained the design
15-23
c har ac t er i ze
Hierarchical Design
Techniques for the
Second-Pass Compile
characterize
15-24
The c har ac t er i ze Command
current_design TOP
characterize -constraints find(cell, U2)
current_design B
compile -inc -map high
TOP U1
A
B
C
U2
U3
characterize calculates the actual attributes and
constraints imposed on a design by its surroundings
characterize then places those constraints
on the design
Output Load and
Delay Constraints
Input Delay Times
and Dri ve on Inputs
15-25
Vi ew i ng t he Resul t s of c har ac t er i ze
write_script outputs a script containing all of the
constraints that have been set on the current_design
/******************************************************
Created by write_script() on Mon Oct 12 18:44:54 1998
******************************************************/
/* Set the current_design */
current_design ALU
create_clock -name "my_clock" -period 10 -waveform {0 5} find(port,"Clk")
set_dont_touch_network find(clock, "my_clock")
set_input_delay 2.2439 -max -rise -clock "my_clock" find(port,"Latch_Flags")
set_input_delay 2.28963 -max -fall -clock "my_clock" find(port,"Latch_Flags")
set_output_delay 5.77132 -max -rise -clock "my_clock" find(port,"Carry_Flag")
set_output_delay 5.80142 -max -fall -clock "my_clock" find(port,"Carry_Flag")
set_load -pin_load 0.343 find(port, "Reset")
set_wire_load "tc6a120m2" -library "cba_core" -port_list find(port, "Reset")
set_driving_cell -lib_cell buf1a4 -pin "Y" -no_design_rule find(port,"Reset")
set_max_capacitance 2.4 find(port, "Reset")
15-26
Rec ompi l e HDL Sour c e af t er characterize
TOP U1
A C
U2
U3
B
Create a script to
characterize and
recompile design B
current_design TOP
O OO O characterize -cons U2
O OO O current_design B
O OO O write_script > B_w.tcl
O OO O remove_design -hier B
O OO O read -f verilog B.v
O OO O current_design B
O OO O source B_w.tcl
O OO O compile
OO OO OO OO write -hier -o B.db
OO OO OO OO current_design TOP
OO OO OO OO report_constraints
15-27
c har ac t er i ze Li mi t at i ons
characterize can only be used when all blocks are
mapped to gates
characterize can NOT be used to derive first-pass
compile design budgets
characterize can only be done one block at a time
Once a block has been characterized and recompiled, there
are newcells driving/loading other subblocks
characterize pushes away any margin that may
exist on block-block interface
15-28
Summar y
Use the Top-Down methodology if feasible
The second-pass compile strategy depends on the
kind of violations in the design
characterize allows to generate detailed block-
level constraints from the interblock requirement
15-29
This exercise is a review of the last few labs, so spend
some time thinking about the various compile steps.
RISC_CORE
ALU
CONTROL
DATA_PATH
LAB 60 min
Resolve
Timing
Violations
PRGRM_CNT_TOP
15-30
Appendi x
Design Budgeter
15-31
Desi gn Budget er
Designs Best Suited for Budgeting
Hierarchical Designs
Large Designs
Designs with subblocks that are not fully registered
Compile
U1
Compile
U5
Allocate Budgets
U1 U4 U5
Reassemble Modules
Verify Timing
Compile
U4
15-32
Build initial
constraints
budgeter
constraints
budgeter
refined
constraints
compile
-inc
Desi gn Budget er Met hodol ogy
Pass Zero
Pass One
Pass Two
GTECH
database
compile
compile
compile
compile
compile
compile
RTL
remove false_path
bottom-up compile
15-33
create_clock -period n -name vclock;
create_clock -period n -name reg2reg clk_ports;
set_input_delay -clock vclock 0.35*n \
$all_inports_except_clockports;
set_output_delay -clock vclock 0.65*n [all_outputs];
set_false_path -from reg2reg -to reg2reg;
35 65
Bui l d t he I ni t i al Ti mi ng Const r ai nt s
Do not use the -max or -min options !
virtual clock
15-34
Timing Model
allocate_budget -write_context {U1 U4 U5}
dont_touch
U4
U5
U1
U2
U3
Ex ampl e
15-35
Command Fl ow
Pass Zero
budget_shell> read_db mapped/TOP.db
budget_shell> allocate_budgets -check_only
budget_shell> allocate_budgets -write_context {U1 U4 U5}
budget_shell> sh ls
U1.ptsh U4.ptsh U5.ptsh
budget_shell> read_db unmapped/U1.db
budget_shell> source U1.ptsh
budget_shell> compile
budget_shell> allocate_budgets -write_context U1
budget_shell> write -f db -hier -out mapped/U1.db
Pass One
budget_shell> current_design U1
budget_shell> source U1.ptsh
budget_shell> compile -inc
budget_shell> write -f db -hier -out mapped/U1.db
Pass Two
critical design
15-36
How t o Ac c ess Desi gn Budget er ?
PrimeTime (Tcl)
Design Budget Shell (Tcl)
budget_shell> allocate_budgets
pt_shell> allocate_budgets
Note: allocate_budget is not supported in dc_shell-t;
use the budget_shell instead.
16-1
Design Exploration
Agenda: Day 4
DAY
4 44 4
Topic Lab Unit
Conclusion 18
16-2
Design Exploration
Perform a Design Exploration compile
Fine-tune the Design Constraints
Build user-defined Path Groups
16-3
Design Exploration
Cl assi c Si x -Mont h Desi gn Fl ow
Test Insertion
Physical Design
Gate-Level Analysis & Signoff
Synthesis
Yes
HDL
Coding
Functional
Simulation
Functionally
Correct?
No
Plan: Three Months for
Coding and Simulating
Plan: Three Months for
Implementing the
Design
Code Freeze
How Long Has it Taken
You to do it This Way?
16-4
Design Exploration
Tr adi t i onal Reac t i ve Fl ow
Couldnt meet timing
(inefficient RTL code)
Fault Coverage <10%
(uncontrollable reset)
Unroutable
(too congested)
Couldnt meet timing
after place and route
Test Insertion
Physical Design
Final Analysis & Signoff
Synthesis
Yes
HDL
Coding
Functional
Simulation
Functionally
Correct?
No
Failed
Failed
Failed
Failed
Bad budgets painted
you into a corner
Traditional Flows address problems reactively, after they occur
16-5
Design Exploration
I dent i f y and Resol ve Pr obl ems Ear l y!
Cost
$
$$$$$$
Degrees of Freedom
Library, Algorithm, Architecture
System-Level Constraints
Code, Partitions, BOA, HLO
DC switches, BRT
LBO/FPM
Layout
$$$$$$$$$$$$
$$$$
Proacti ve Design Exploration
Discover and resol ve performance issues early in the flow
Fix problems at the source code level whenever possible
Plan for the speed and area impact of scan insertion
Anticipate the problems of slow top-level interconnects
16-6
Design Exploration
The Pr oac t i ve Desi gn Met hodol ogy
Implement
Design
Compile Major Subblocks
Integrate Chip
Reoptimize Design
Final Analysis & Signoff
Place & Route
Create Custom WLM
Floorplan
ECO P&R
Logical Design Physical Design
Validate
Design
Code RTL
Check WLMs
Functional Simulation
Design Exploration
Create Custom WLM
Check Tool Flow
Early Floorplan / P&R
Code Freeze?
16-7
Design Exploration
Desi gn Ex pl or at i on
A quick, exploratory synthesis run to gauge design
performance against goals
When is Design Exploration performed?
In parallel with functional simulation, not at the end!!!
Any time code changes enough to impact performance
On small blocks of code where the problem is self-contained
and easily fixable
Logical Design
Code RTL
Functional Simulation
Design Exploration
16-8
Design Exploration
Desi gn Ex pl or at i on Goal s
Use the fastest, default-effort compiles possible to:
Verify that code is synthesizable
Verify that code is close to meeting
constraints (10-15%)
Verify that constraints are realistic and sufficient
Identify and declare timing exceptions
Identify partitioning problems
Identify testability problems
Account for the impact of inserting scan cells
Ensure that your wire load models are reasonable
16-9
Design Exploration
You are simply validating that you are close to meeting
timing with the code you have, so you dont have to
recode later.
You are performing exploration on code that may not be stable yet.
Why 10% and Not 0%?
Design Compiler was not meant to fix bad code
Garbage In ==> Garbage Out
You can reasonably expect advanced compile
strategies to fix violations that are 10-15% over
timing
More efficient HDL code (better algorithms and
architectures) is often required to fix larger violations
16-10
Design Exploration
What I s t he Desi gn Ex pl or at i on Fl ow ?
Test-ready compile
Analyze
timing, partitioning,
& test rule
violations
Initial Floorplan,
Create custom wire
load model
Analyze timing
violations
GOOD
FIX
FIX
Design Exploration
GOOD
Constrain
Continue
Simulation
New
HDL code
Recode HDL
Repartition
Design
16-11
Design Exploration
Typi c al Const r ai nt Sc r i pt (Basi c )
# Define clock
set_dont_touch_network [all_clocks]
# Delay and drive strength on input ports
set all_inputs_but_clk [remove_from_collection [all_inputs] CLK]
set_input_delay $clk_to_q -clock CLK $all_inputs_but_clk
set_driving_cell -lib_cell $my_register $all_inputs_but_clk
# Delay and load on output ports
set_output_delay [expr 5 - $clk_to_q] -clock CLK [all_outputs]
set_load [expr $pessimistic_load * 3] [all_outputs]
# Describe environment
set_operating_conditions WCCOM
set_wire_load_model -name 100k_WLM -mode top
my_block_constraints.tcl
A
B
Y
CLK
16-12
Design Exploration
Det ai l ed Model i ng of Ex t er nal Loads
set pessimistic_load [expr load_of(TECH_LIB/inv1a1/A)]
# Account for Pin Load and Wire Load on Outputs
set_load [expr $pessimistic_load * 3] [all_outputs] # pins
set_port_fanout_number 3 [all_outputs] # wires
# Account for Pin Load and Wire Load on Inputs too!
set_load $pessimistic_load $all_inputs_but_clk # pins
set_port_fanout_number 1 [all_inputs] # wires
MY_BLOCK
A
A
A A
A
inv1a1
16-13
Design Exploration
Spec i al WLM f or Por t s (Gl obal Net s)
# Describe different WLMs for internal nets vs. global nets
set_wire_load_mode top 100k_WLM
set_wire_load_model -name GLOBAL_NET_WLM [get_ports *]
BLOCK_1
BLOCK_3 BLOCK_4
BLOCK_2
TOP
16-14
Design Exploration
Desi gn Rul e Const r ai nt s
DC respects design rules as highest priority of all
Certain design rules may exist on library cell pins
max_capacitance
max_transition
max_fanout
You can apply design rules to entire designs to:
Anticipate the interface environment your block will see
Prevent the design from operating cells close to their limits,
where performance degrades rapidly
16-15
Design Exploration
set _max _c apac i t anc e
# Find the max capacitive load allowed on your expected driver
set DRIVE_PIN TECH_LIB/inv1a27/Y
set MAX_CAP [get_attribute $DRIVE_PIN max_capacitance]
3.600
# Add some margin so DC wont fully load the driver
set CONSERVATIVE_MAX_CAP [expr $MAX_CAP / 2.0]
1.800
set_load 1.2 [get_ports IN1]
set_max_capacitance $CONSERVATIVE_MAX_CAP [get_ports IN1]
# max internal load DC can put on IN1 is [1.8 - 1.2 = 0.6pf]
A
inv1a27
my_dr_cons.tcl
Y
1.2pf
IN1
16-16
Design Exploration
set _max _t r ansi t i on
# Find the max transition allowed on your expected driver
set DRIVE_PIN TECH_LIB/inv1a27/Y
set MAX_TRANS [get_attribute $DRIVE_PIN max_transition]
0.400
# Add some margin so DC wont fully load the driver
set CONSERVATIVE_MAX_TRANS [expr $MAX_TRANS / 2.0]
0.200
set_max_transition $CONSERVATIVE_MAX_TRANS [get_ports IN1]
# DC accounts for the driving_cell type and external load on it,
# limits internal loads placed on IN1 to meet your design rule
A
inv1a27
my_dr_cons.tcl
Y
1.2pf
IN1
16-17
Design Exploration
set _max _f anout
set_max_fanout 6 [get_ports IN1]
Is the max_fanout design
rule on port IN1 met?
How many cells might
port IN1 have to drive?
Does it matter what
the cell type is?
get_attribute TECH_LIB/inv1a1/A fanout_load
0.25
# DC might load port IN1 with 6 / 0.25 = 24 inv1a1 cells!
get_attribute TECH_LIB/inv1a27/A fanout_load
3.00
# DC can only load port IN1 with 6 / 3.00 = 2 inv1a27 cells!
IN1
A
inv1a27
Y
inv1a1
inv1a1
inv1a1
inv1a27
16-18
Design Exploration
Fanout Loads
set_max_fanout uses fanout_load, NOT absolute fanout number!
Sum of fanout_load on a port must be less than max_fanout
design rule constraint
Some cell/pins have no fanout_load attribute
DC then checks library for default_fanout_load attribute
If neither exists, DC assumes a value of zero
This may allow infinite fanout on an input port!
IN1
A
inv1a27
Y
inv1a1
inv1a1
inv1a1
inv1a27
= 0.25
= 0.25
= 0.25
= 3.00
= 3.00
16-19
Design Exploration
Cont r ol l i ng Por t Fanout
How can I force port fanout to only one real
load?
# Easiest case
set_max_fanout 1 [all_inputs]
# Trickier case
set SMALL_CELL TECH_LIB/buf1a1/A
set SMALL_FOL get_attribute $SMALL_CELL fanout_load
0.5000
set_max_fanout $SMALL_FOL [all_inputs]
Does my library have the necessary attribute?
get_attribute TECH_LIB default_fanout_load
0.0000
# Uh-oh!
If not, how can I set it?
set_attribute TECH_LIB default_fanout_load 1.0 \
-type float
1.0000
16-20
Design Exploration
Typi c al Compi l e Sc r i pt (Basi c )
# Read in source files and build initial Gtech design
if (You_are_using_VHDL) {
analyze -format vhdl {file1.vhd file2.vhd file3.vhd TOP.vhd}
elaborate TOP
} else {
read_verilog {file1.v file2.v file3.v TOP.v}
}
# Constrain the Gtech design
source my_block_constraints.tcl
source my_dr_cons.tcl
# Optimize and map the design
compile
# Save the design and exit
write -format db -hierarchy -output my_block.db
quit
compile_flow.tcl
16-21
Design Exploration
Fast est Runt i mes f or Desi gn Ex pl or at i on
current_design MY_BLOCK
reset_design
source time_and_load_budget_constraints.tcl
remove_attribute MY_BLOCK max_area
if (You_Have_DesignWareFoundation_and_Plan_To_Use_It) {
set synthetic_library dw_foundation.sldb
append link_library $synthetic_library
}
set_simple_compile_mode true
set compile_dw_simple_mode true
set_scan_configuration -style multiplexed_flip_flop
compile -area_effort none -scan
16-22
Design Exploration
Addi t i onal Runt i me Speed-ups
New in v2000.05: Presto RTL code reader
Average 6x faster Verilog elaboration than in v1999.10
Prestos VHDL support due in v2000.10 release
Average 35% less memory usage
Supports additional Verilog language constructs
New in v2000.05: New Verilog netlist reader
Average 3x faster than v1999.10
Average 3x memory reduction compared to v1999.10
dc_shell-t> set enable_verilog_netlist_reader true
dc_shell-t> read_verilog -netlist mapped.v
dc_shell-t> set hdlin_enable_presto true
16-23
Design Exploration
Sc enar i os: Ex pl or i ng Subdesi gns
What Compile Technique Should I Use
During Design Exploration?
What Constraints Should I Consider
During Design Exploration?
16-24
Design Exploration
SUBDESIGN_As RTL code just became available
It is a very critical block, and you want to evaluate its
performance without waiting for the other blocks
SUBDESIGN_A is a small block
Its parent block will eventually be compiled top-down
Its inputs and outputs might not be registered
Desi gn Ex pl or at i on on SUBDESI GN_A
SUBDESIGN_A (40 K gates)
10K
PRGRM_CNT
20K
DATA_PATH
10K
CONTROL
IN_BUS [31:0]
CLK
OUT_BUS [31:0]
ZERO_FLAG
16-25
Design Exploration
How To Const r ai n SUBDESI GN_A
MAJOR_BLOCK_1 (140 K gates)
IN_BUS [31:0]
CLK
OUT_BUS [31:0]
SUBDESIGN_A
(40K gates)
SUBDESIGN_B
(30K gates)
SUBDESIGN_C
(50K gates)
SUBDESIGN_D
(20K gates)
D Q
MAJOR_BLOCK_1 will be compiled top-down later...
after code for A, B, C, D becomes available and stable
Inputs and outputs of subdesigns might not be registered
How do we constrain SUBDESIGN_A for a standalone
compile at this level?
16-26
Design Exploration
How To Const r ai n SUBDESI GN_A (c ont )
How do we constrain SUBDESIGN_A for a standalone
compile at this level?
Use what you know
Clock period
Operating Conditions
Estimate what you dont know
Input drives, Output loads, Wire load model, Time Budget
set_operating_conditions SLOW_COMMERCIAL
set_wire_load_model -name 140Kgates -mode top
set_driving_cell -lib_cell NAND2 -pin Y $all_in_ex_clk
set_load [expr [load_of TECH_LIB/NAND2/A] * 4] $all_in_ex_clk
set_load [expr [load_of TECH_LIB/NAND2/A] * 6] [all_outputs]
16-27
Design Exploration
How To Const r ai n SUBDESI GN_A: I /O
What about I/O timing?
Are your inputs driven by blocks with registered-outputs?
Are your outputs registered?
Do you have purely combinational paths in your design?
DRIVING_BLOCK
MAJOR_BLOCK_2
SUBDESIGN_A
RECEIVING_BLOCK
A
B
C
D
CLK
W
X
Y
Z
?
?
?
?
32
32
32
32 32
32
32
32
16-28
Design Exploration
I /O Ti mi ng Const r ai nt Opt i ons
# Assume every block has registered outputs, same 10ns clock
set_input_delay -max $clk_to_q -clock CLK $all_in_ex_clk
set_output_delay -max [expr 10 - $clk_to_q] -clock CLK [all_outputs]
D Q
QB
D Q
QB
FF1
FF2
MY_DESIGN
A
CLK
Z D Q
QB
FF3
RECEIVING_BLK
D Q
QB
FF0
DRIVING_BLK
# Assume every block has registered outputs, same 10ns clock
set_input_delay -max [expr $CLK_PER * 0.1] -clock CLK $all_in_ex_clk
set_output_delay -max [expr $CLK_PER * 0.9] -clock CLK [all_outputs]
16-29
Design Exploration
I /O Ti mi ng Const r ai nt Opt i ons (c ont )
# Assume blocks do not have registered outputs; split delay equally among both sides
# This is the typical case when exploring smaller, lower-level blocks
set_input_delay -max [expr $CLK_PER * 0.5] -clock CLK $all_in_but_clk
D Q
QB
D Q
QB
FF1
FF2
MY_DESIGN
A
CLK
Z D Q
QB
FF3
RECEIVING_BLK
D Q
QB
FF0
DRIVING_BLK
How much margin is built into these constraints?
16-30
Design Exploration
Ex pl or i ng Combi nat i onal Pat hs
D Q
QB
D Q
QB
FF1
FF2
MY_DESIGN
A
CLK
Z
How do these constraints affect the
combinational path from B to Y?
Do they affect optimization of MY_DESIGN?
COMBO B
Y
set_input_delay -max [expr $CLK_PER * 0.5] -clock CLK $all_in_ex_clk
16-31
Design Exploration
User -Def i ned Pat h Gr oups
D Q
QB
D Q
QB
FF1
FF2
A
CLK
Z
COMBO B
Y
Custom path groups allow more control over optimization
Each path group is optimized independently
Worst violator in one path group doesnt prevent optimization in another
Path groups can be given different priorities
Output
Paths
Input
Paths
Combinational Paths
Register-to-Register Paths
16-32
Design Exploration
Cr eat i ng Cust om Pat h Gr oups
DO IN A LAB! Use group_path to group paths of interest
group_path -name OUTPUTS -to [all_outputs]
group_path -name INPUTS -from [all_inputs]
In which path group will register-to-register timing paths be?
In which path group will combinational timing paths be?
How does this affect a compile?
How can you remove the user defined path groups?
group_path -name COMBO -from [all_inputs] -to [all_outputs]
16-33
Design Exploration
Tw o Pat h Gr oup Opt i ons
# Avoid getting stuck on one path in the reg-reg group
group_path -name INPUTS -from [all_inputs]
group_path -name OUTPUTS -to [all_outputs]
group_path -name COMBO -from [all_inputs] -to [all_outputs]
group_path -name clk -critical_range 0.3
D Q
QB
D Q
QB
FF1
FF2
A
CLK
Z
COMBO B
Y
16-34
Design Exploration
Pat h Gr oups vs Cr i t i c al Range
Path Group
Path Groups will allow path improvements in a given
group which degrade another groups worst violator, IF the
overall cost function is improved
Adding a path group can INCREASE the worst violator in
a design
Critical Range
Critical Range will not allow improvements to near-critical
paths that worsen the worst violator in a path group
To optimize all critical endpoints in a design, giving each
endpoint its own path group usually runs faster than using
a very large critical_range, but runtime can be excessive
for either case if many paths are involved
16-35
Design Exploration
When Do I Ex i t Desi gn Ex pl or at i on?
Timing violations less than 10% of actual goals
Good design partitioning
No test rule violations
Accurate wireload models
Single-cycle timing exceptions identified
Additional, user-defined criteria
Completion Criteria for all major subblocks
16-36
Design Exploration
Uni t Revi ew
Perform design exploration
Validate your tool flow
Floorplan early
Check accuracy of wire
load models
Be Proactive!
Anticipate Problems as early as possible.
17-1
Synthesizing for Test
Agenda: Day 4
DAY
4 44 4
Topic Lab Unit
Conclusion 18
17-2
List at least two benefits of using the compile -
scan command
State the command that checks a design for
testability violations
State the command that shows the estimated fault
coverage of your circuit
17-3
Chi p Def ec t s: Theyr e Not My Faul t !
My chip was well designed and functionally
correct. It simulated and synthesized just
fine, but when the chip was manufactured,
it didnt work!
WHY?
.
17-4
Manuf ac t ur i ng Def ec t s
Silicon Defects
Photolithography Defects
Mask Contamination
Process Variations
Defective Oxide
Physical Defects
Shorts (Bridging Faults)
Opens
Transistor Stuck On/Open
Resistive Short/Open
Changes in Threshold Voltage
Electrical Effects
Logic Stuck-at-0/1
Slower Transitions (Delay Fault)
AND-bridging, OR-bridging
Logical Effects
17-5
Why Test f or Manuf ac t ur i ng Def ec t s?
The manufacturing test is created to detect
manufacturing defects and reject those parts
before shipment
Debug manufacturing process
Improve process yield
17-6
DUT
I
n
p
u
t
s
O
u
t
p
u
t
s
How I s Manuf ac t ur i ng Test Per f or med?
Automatic Test Equipment (ATE) applies input stimulus
to the Device Under Test (DUT) and measures the output
response
If the ATE observes a response different from the
expected response, the DUT fails the manufacturing test
The process of generating the input stimulus and
corresponding output response is known as
Automated Test Pattern Generation (ATPG)
17-7
Output
Stuck At
Logic 1
(SA1)
I nput
Stuck At
Logic 0
(SA0)
Stuck-At Fault (SAF):
A logical model representing the effects of an
underlying physical defect.
The St uc k -At Faul t Model
17-8
U1
A
Z
B
C
D
SA0
If this SA0 fault is present
then U1/Y stays at logic 0
If not present, then U1/Y is
driven to its normal value
We can exploit this either/or behavior to detect the fault.
Al gor i t hm f or Det ec t i ng a SAF
17-9
U1
0
1/ 0
Cont r ol l abi l i t y
The ability to set internal nodes to a specific value
17-10
Enabling Input
Observable
Discrepancy
0
U1
1
0
0
0
1/ 0
0/ 1
1/ 0
Obser vabi l i t y
The ability to propagate the fault effect from an internal
node to a primary output port
17-11
Faul t Cover age
Fault coverage =
number of detectable faults
total number of possible faults
High fault coverage correlates to high defect coverage
17-12
Test i ng a Mul t i st age, Pi pel i ned Desi gn
Can create a lot more complications for you
Each fault tested requires a predictive means for both controlling the
input and observing the results downstream from the fault.
Test for SA0 fault here
1
0
0
1
Need to set input pins to specific
values so that nets within pipeline can
be set to values which test for a fault
Need to observe
results at the output of
the design.
17-13
Sc an Chai ns Hel p
Scan chain initializes nets within the design (adds
controllability)
Scan chain captures results from within the design (adds
observability)
Inserting a scan chain involves replacing all Flip-Flops with
scannable Flip-Flops
What effect will the mux and scan chain have on circuit timing?
Test for SA0 fault here.
1
0
0
1
Scan
Flip-Flop
Scan_In
Scan_Ena
17-14
Non-Scan
Register
Multiplexed Scan Register Chain
Additional fanout and
capacitive loading
DO
TI
DI
TE
CLK
0
1
1
0
CLK
Larger setup time
requirement
Larger area than non-scan registers;
optimistic wire load model selection
TI
DI
If you plan to include internal scan, you must account for the
impact of scan registers on a design early in the design cycle
I nac c ur ac y Due t o Sc an Repl ac ement s
17-15
Accurate area, timing, and loading modeled
up front
Easier synthesis flow -- scan cell insertion
performed in one compilation step
DO
DI
TI
1
0
TO
Scan Register Used During Initial Compile
Benefits
Use One-Pass Sc an Synt hesi s
Regular registers are replaced with scannable ones, but
not chained
Include the scan style in the constraint script file
set_scan_configuration -style multiplexed_flip_flop
Perform one-pass test scan compile
compile -scan
17-16
Resul t of Test -Ready Compi l e: Ex ampl e
dc_shell> compile -scan
D
TI
TE
Q
0
0
A
B
CLK
D
E
Scan cells inserted during compile
D
TI
TE
Q
Loading effect of scan chain modeled
17-17
DFT Chec k i ng: Ex ampl e
If a warning or error is returned, it is up to the user to correct
the circuit so that there are no scan design rule violations.
dc_shell> check_test
Warning: Clock/enable pin CP of cell u0 (FD1) has multiple sources (TEST-126)
Information: A source of the violation is port IN2 (TEST-182)
Information: A source of the violation is pin Q of cell u0 (TEST-180)
Information: A source of the violation is port CLK (TEST-182)
Information: Test design rule checking completed with 1 warning(s) and 0
error(s)
D Q
17-18
Test abi l i t y Vi ol at i on: Ex ampl e
What would happen in the circuit above, if, during
test, a 1 were shifted into the Flip-Flop?
A: We would never be able to clock the Flip-Flop!
The Flip-Flop, therefore, cannot be allowed to be part of a
scan chain. Logic in N cannot be tested (controlled).
The above circuit:
Violates good design for testpractices
Reduces the fault coverage
D Q
17-19
dc_shell> create_test_patterns -dft -sample 11
Warning: Violations occurred during test design rule checking. (TEST-124)
Building test generation network
Non-collapsed Collapsed
No. of detected faults 1423 1356
No. of abandoned faults 2 2
No. of tied faults 4 4
No. of redundant faults 2 2
No. of untested faults 0 0
Total no. of faults 1431 1364
Fault coverage 99.86 99.85
No. of test patterns 174
Runni ng ATPG
create_test_patterns activates the ATPG function of DC
Execute ATPG after compile -scan and check_test
17-20
Design-for-Test
Compiler
(DFTC)
DFTC enables designers
to do constraint-based
scan synthesis!
compile scan-ready logic blocks
check synthesized logic for scan compliance
insert scan chains, top-down or bottom-up
preview fault coverage on a scanned block
DFTC bundles together expert logic-synthesis capability plus
all the design-for-test features you need to:
What I s DFTC?
17-21
DFTC Methodology for a Typical Block:
Pre-Scan
DRC
Insert Scan
Scan-Ready
Synthesis
HDL
Post-Scan
DRC
Run
ATPG
check_test check_test insert_scan compile -scan
Constraints:
Scan style,
speed, area
Technology
Library:
Gates, flip-flops,
scan equivalents
Constraint-Based
Scan Synthesis:
Routing, balancing,
gate-level
optimization
DFTC Fl ow at a Gl anc e
17-22
Test Tool s Summar y
compile -scan
check_test
create_test_patterns -dft (coverage)
insert_scan
create_test_patterns (ATPG)
write_test (for ATE and gate-level sim)
DC-XP
X
X
X
X
Test Compiler
X
X
X
X
X
X
17-23
Synt hesi zi ng f or Test Summar y
Test is a design methodology
It has its own testability design rules
Most problems associated with test can be
anticipated and corrected in advance, during the
initial compile of the HDL code
18-1
Conclusion
Agenda: Day 4
DAY
4 44 4
Topic Lab Unit
Conclusion 18
18-2
Conclusion
List at least four steps to take before compiling a
design
18-3
Conclusion
Some Thought s on Codi ng
Spend more time writing good HDL code so you spend
less time optimizing the design
If youve written your code so that the critical path is
reduced to a single gate, and the design still does not
meet the timing, then it is not your code thats wrong
Poor
Start
Point
Better
Start
Point
Best
Start
Point
Goal
18-4
Conclusion
Synt hesi s Qual i t y Depends on Al gor i t hms!
Solution to a design problem is typically based on a
particular algorithm
From that algorithm, you specify a hardware
architecture to solve the problem
Your high-level design decisions provide the starting
point for DCs translation, optimization, and mapping
DCs HLO techniques can NOT change the algorithm or
architecture you choose to implement!
Single-cycle vs. Pipelined over several cycles
Serial vs. parallel
FIR vs. IIR, etc
18-5
Conclusion
Choose the algorithm, architecture, and implementation
to match the performance goals of your design.
Like circuits, algorithms also invol ve tradeoffs between speed,
area, memory, code size/complexity, etc...
Cl assi c Al gor i t hms, Ar c hi t ec t ur es, & Tr adeof f s
Frequency Analysis: DFT vs. FFT
Sorting Algorithms: Bubblesort vs. Quicksort
Sine wave generator: Difference Equation vs. Counter
+ Lookup Table
Finite State Machines: 1-hot encoding vs. Binary
Microprocessor Design: RISC vs. CISC
18-6
Conclusion
Ref l ec t i ons on Synt hesi s
There is no golden script for synthesis
Physics dictates what will fit between two registers
The random setting of optimization switches and
constraints to meet your speed goals is not a
credible methodology
Most timing problems are not caused by wrong
compile switches!
Compile switches are a vehicle to fix compile problems
late in the design cycle
18-7
Conclusion
Pr e-Compi l e Chec k l i st
Good Synthesizable HDL Code
Good Synthesis Partitioning
Realistic Constraints & Attributes
False Paths Identified
Wireloads Reflect Physical Placement
(discussed in Advanced CHIP)
18-8
Conclusion
What Do You Do Fi r st ?
1. Satisfy the items on the checklist. Use what you
have learned in this workshop.
2. If adding margin, do not overconstrain by more
than 10%.
3. Always, always, always (always!) start with the
default compile.
compile <-scan>
18-9
Conclusion
Compi l e St r at egy
Done!
Yes
compile
No
Repartition
Block
Rewrite
HDLCode
Modify Flatten &
Structure Options
Good
Results
?
Anal yze and Elaborate HDL
Appl y Constraints
compile
-map high
-incremental
Start
compile
-map high
Anal yze to
identify problem,
then ...
Anal yze to
identify problem,
then ...
Specify
critical_range
Characterize
Block
= Small Violations (10-25%)
= Larger Violations
18-10
Conclusion
u_int/U68/Q (INVB)
Incr Path
clock (input port clock) (rise edge)
0.00 0.00
addr31 (in) 0.00 22.40 f
u_proc/address31 (proc) 1.08 23.48 f
u_proc/u_dcl/int_add[7] (dcl) 0.00 23.48 f
u_proc/u_dcl/U159/Q (NAND3H) 0.62 24.10 r
u_proc/u_dcl/U160/Q (NOR3F) 0.75 24.85 f
u_proc/u_dcl/U186/Q (AND3F) 1.33 26.18 f
u_proc/u_dcl/U135/Q (NOR3B)
1.36 28.17 f
u_proc/u_dcl/U95/Q (BF) 0.44 29.98 f
u_proc/u_dcl/U96/Q (BF) 0.45 30.43 r
u_proc/u_dcl/ctl_rs_N (dcl) 0.00 32.21 r
u_proc/u_ctl/ctl_rs_N (ctl) 0.00 32.21 r
u_proc/u_ctl/U126/Q (NOR3B) 1.78 33.98 f
u_proc/u_ctl/U120/Q (NAND2B) 1.07 35.06 r
u_proc/u_ctl/U99/Q (NBF) 0.88 35.94 r
u_proc/u_ctl/U122/Q (OR2B) 10.72 46.67 r
u_proc/u_ctl/read_int_N (ctl) 0.00 46.67 r
u_proc/int_cs (proc) 0.00 46.67 r
u_int/readN (int) 0.00 46.67 r
u_int/U39/Q (NBF) 1.29 47.95 r
u_int/U17/Q (INVB) 1.76 49.71 f
u_int/U16/Q (AOI21F) 2.49 52.20 r
u_int/U60/Q (AOI22B) 1.43 53.63 f
1.81 55.44 r
u_int/int_flop_0/D (DFF) 0.00 55.44 r
Point
Ti mi ng Anal ysi s t o Di agnose t he Pr obl em
Spot the whales in the timing report: Where are they? What are they? And why?
Six buffers back
to back?!
Rather late arrival for
a 30 ns period!
11 ns delay for an OR gate
is not good.
Four hierarchical
partitions.
18-11
Conclusion
Look Bac k at t he Past Sever al Days
Setup, Libraries, GUI, Coding for Synthesis (Day 1)
Describing the synthesis environment (Day 2)
Optimization and Compile Techniques (Day 3)
Design Exploration and DFT (Day 4)
18-12
Conclusion
1-800-793-3448
www.synopsys.com/services/education
Need Mor e Tr ai ni ng?
VHDL Coding Styles for Synthesis
Verilog Coding Styles for Synthesis
Advanced Chip Synthesis Workshop
PrimeTime Workshops
Advanced Verilog & VHDL Workshops
And more...
18-13
Conclusion
Advanc ed Chi p Synt hesi s
Place&Route
compile
Ultra
create_wire_load
Ultra
reoptimize_design
PrimeTime
Floorplanner
GDSII
PrimeTime
Lib
WLM
RTL
.db
.db
.db
RTL
CLWM
Forward-
Annotate
Placement
PDEF
Actual
Data
RC
SDF
PDEF
RC
SDF
PDEF
Computed
Data
DC
DC
DC
ECO
Iterate
Iterate
.db
.v, .vhdl, .sdf, etc.
18-14
Conclusion
Codi ng St yl es f or Synt hesi s
A_Temp = A;
Count = 8;
for (Level=0; Level<=2; Level= Level+1)
begin
Count = Count >> 1; // Divide by 2
for (K = 0; K <= (Count - 1); K = K + 1)
A_Temp[K] = A_Temp[K * 2] + A_Temp[(K * 2) + 1];
end
Sum_Out = A_Temp[0];
reg [7:0] Count;
always @(posedge Clock)
begin
if (Reset)
Count <= 8'b0;
else
Count <= Count + 1;
end
always @(Count)
begin
And_Bits = &Count;
Or_Bits = |Count;
Xor_Bits = ^Count;
end
process (In_A, In_B)
begin
if In_A = '1' then
Out_Z <= '0';
else
if In_B = '1' then
Out_Z <= '1';
else
Out_Z <= '-';
end if;
end if;
end process;
18-15
Conclusion
Need Mor e I nf or mat i on or Hel p?
Synopsys on the Web:
SOLD
solv-Net
Technical Articles
Application Notes
Release Notes
ESNUG
Services:
Workshops
Support Center
Application
Consultants
18-16
Conclusion
Synopsys on t he Wor l d Wi de Web
Synopsys Web Server
www.synopsys.com
Next SNUG
City:___________
Date:___________
18-17
Conclusion
How t o Use sol v-NET
Web Page:
www.synopsys.com
Follow the solv-NET link
Enter your solv-NET ID
18-18
Conclusion
Human Sour c es f or I nf or mat i on and Hel p
Contact the Support Center:
Web Click Enter A Callon the Synopsys Web page
E-mail support_center@synopsys.com
Phone 1-800-245-8005
Application Consultants:
Process and tool expertise available worldwide
Contact your sales representative for more details
Consultants
Available for in-depth, on-site, dedicated, custom consulting
Contact your sales representative for more details
18-19
Conclusion
Ot her Sour c es f or I nf or mat i on and Hel p
ESNUG
Independent Email Synopsys Users Group
Customer problems, workarounds, cool scripts
Updates on J ohn Cooleys love life, housecleaning, etc
jcooley@world.std.com www.deepchip.com
www.eda.org
Links to VHDL, Verilog Archives
Links to EDA companies
Links to other EDA sites
Newsgroups:
comp.cad.synthesis
comp.lang.verilog
comp.lang.vhdl
comp.lsi.cad
comp.arch.fpga
18-20
Conclusion
That s al l Fol k s!

Chip Synthesis Workshop 1392

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31833-000-S16B i Synopsys Chip Synthesis Workshop

All of the combinational logic causing the

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