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) required to produce N
Level
N
SW
= 4S.. (ii)
From above two equations
= 2S+1.
Let, Total number of switches required = N
SW
Number of levels of MLI = N
level
Then,
N
SW
=
+ 7
2
.. (3)
This equation can be used to find number of switches
required to produce voltage of particular level.
The Fig.1 shows seven voltage sources are connected in
cascade. R1 R7 are the resistances connected in series
with each source respectively. These resistances are
internal resistances of each source. When switch SW5 is
turned on voltage level is zero. Equation 3 shows that by
adding one switch two more voltage level can be
obtained. The specifications for the proposed 15 level
inverter is given below:
V1=V2=V3=V4=V5=V6=V7=Vdc=100V
R1=R2=R3=R4=R5=R6=R7=0.01
Internal resistance of controlled switches
(SW5,SW6,SW7,SW8,SW9,SW10,SW11)=0.001
Internal resistance of H bridge switches = 0.01 .
Fig. 1: Circuit diagram of fifteen levels Cascaded
proposed MLI
4. MULTICARRIER VARIABLE
SWITCHING FREQUENCY PHASE
DISPOSITION SINUSOIDAL PWM
(PDSPWM)
Several PWM techniques have been employed
successfully to multilevel inverters till today.
SPWM technique is most widely used for industrial
purpose because of its simplicity in control
algorithm. In PDSPWM technique a triangular
carrier wave is continuously compared with
reference sinusoidal wave. In case of N-level Phase
Disposition multilevel inverter, (N-1) level shifted
carrier signals having same magnitude and same
frequency are used and compared with a sinusoidal
modulating signal. Zero voltage of reference signal
is positioned at the middle of the carrier set.
Different logic circuits have been developed for
different levels to generate gating signal to the
switches at proper instants of time[6]-[8].
Here, inverter performance has been analyzed with
variable frequency multi carrier waveform of 1KHz,
2KHz, 4KHz. These high frequency carrier waves
continuously compared with 50 Hz reference wave.
The frequency of carrier wave should be selected
such that it is integer multiple of the frequency of
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reference wave so as to synchronize these two
waveforms.
Fig 2. (a) reference sinusoidal voltage (b) gating signal
for SW1 & SW2 (c) gating signal for SW3 & SW4 (d)
gating signal for SW7 (e) gating signal for SW6 (f)
gating signal for SW5
5. EXPERIMENTAL RESULTS
A comparative study of the proposed cascaded MLI for
different levels (5-level,7-level,9-level,11-level,13-
level,15-level) at different carrier frequencies
(1KHz,2KHz,4KHz) have been shown in this paper. The
performance has been analyzed in MATLAB simulink
environment.
5.1. Five Level Inverter
Fig.3 (a) shows the circuit diagram of five level inverter
with reduced number of switches and a multi conversion
cell having two voltage sources.
Fig.3(a) Circuit Diagram of Five Level Inverter
Fig. 3(b) Output Voltage Waveform of Five level
inverter
The output voltage waveform in Fig. 3(b) shows five
different voltage levels attained following the switching
status of Table II.
Fig. 3(c) % THD of output voltage of five level inverter
at carrier frequency 4kHz
% THD of output voltage of five level inverter has been
evaluated using FFT tool in MATLAB simulink. From
Fig. 3(c) it has been observed that the % THD for five
level inverter is 21.95% at carrier frequency 4kHz.
International Journal of Emerging Technologies and Engineering (IJETE)
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5.2. Seven Level Inverter
Fig. 4(a) Circuit Diagram of Seven Level Inverter
Fig. 4(a) shows the circuit diagram of seven level
inverter with reduced number of switches and a multi
conversion cell having three voltage sources.
Fig. 4(b) Output Voltage Waveform of Seven level
inverter
The output voltage waveform in Fig. 4(b) shows seven
different voltage levels attained following the switching
status of Table II.
% THD of output voltage of seven level inverter has
been evaluated using FFT tool in MATLAB simulink.
From Fig. 4(c) it has been observed that the % THD for
seven level inverter has been reduced to 15.22% at
carrier frequency 4kHz.
Fig. 4(c) % THD of output voltage of seven level
inverter at carrier frequency 4kHz
5.3. Nine Level Inverter
Fig.5 (a) shows the circuit diagram of nine level inverter
with reduced number of switches and a multi conversion
cell having four voltage sources.
Fig. 5(a) Circuit Diagram of Nine Level Inverter
The output voltage waveform in Fig. 5(b) shows nine
different voltage levels attained following the switching
status of Table II.
International Journal of Emerging Technologies and Engineering (IJETE)
Volume 1 Issue 5, June 2014, ISSN 2348 8050
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Fig. 5(b) Output Voltage Waveform of Nine level
inverter
Fig. 5(c) % THD of output voltage of Nine level
inverter at carrier frequency 4kHz
% THD of output voltage of nine level inverter has been
evaluated using FFT tool in MATLAB simulink. From
Fig. 5(c) it has been observed that the % THD for nine
level inverter has been reduced to 11.66% at carrier
frequency 4kHz.
5.4. Eleven Level Inverter
Fig. 6(a) Circuit Diagram of Eleven Level Inverter
Fig. 6(a) shows the circuit diagram of eleven level
inverter with reduced number of switches and a multi
conversion cell having five voltage sources.
Fig. 6(b) Output Voltage Waveform of Eleven level
inverter
Fig. 6(c) % THD of output voltage of Eleven level
inverter at carrier frequency 4kHz
% THD of output voltage of eleven level inverter has
been evaluated using FFT tool in MATLAB simulink.
From Fig. 5(c) it has been observed that the % THD for
eleven level inverter has been reduced to 10.44% at
carrier frequency 4kHz.
5.5. Thirteen Level Inverter
Fig. 7(a) Circuit Diagram of Thirteen Level Inverter
International Journal of Emerging Technologies and Engineering (IJETE)
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Fig.7 (a) shows the circuit diagram of thirteen level
inverter with reduced number of switches and a multi
conversion cell having six voltage sources.
Fig. 7(b) Output Voltage Waveform of thirteen level
inverter
The output voltage waveform in Fig. 7(b) shows thirteen
different voltage levels attained following the switching
status of Table II.
Fig. 7(c) % THD of output voltage of thirteen level
inverter at carrier frequency 4kHz
% THD of output voltage of thirteen level inverter has
been evaluated using FFT tool in MATLAB simulink.
From Fig. 7(c) it has been observed that the % THD for
thirteen level inverter has been reduced to 8.26% at
carrier frequency 4kHz.
5.6. Fifteen Level Inverter
Fig. 8(a) Circuit Diagram of Fifteen Level Inverter
Fig.8 (a) shows the circuit diagram of fifteen level
inverter with reduced number of switches and a multi
conversion cell having seven voltage sources.
Fig. 8(b) Output Voltage Waveform of fifteen level
inverter
The output voltage waveform in Fig. 8(b) shows fifteen
different voltage levels attained following the switching
status of Table II.
International Journal of Emerging Technologies and Engineering (IJETE)
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Fig. 8(c) % THD of output voltage of fifteen level
inverter at carrier frequency 4kHz
% THD of output voltage of fifteen level inverter has
been evaluated using FFT tool in MATLAB simulink.
From Fig. 8(c) it has been observed that the % THD for
fifteen level inverter has been reduced to 6.39% at
carrier frequency 4kHz.
Table I: Comparison of number of switches required in
proposed MLI with that of conventional MLI for
different levels
LEVEL
(
)
NO. OF
VOLTAGE
SOURCES
REQUIRED
(S)
NO. OF
SWITCHE
S
REQUIRE
D IN
PROPOSE
D MLI
(
)
NO. OF
SWITCH
S
REQUIR
D
INCONV
TIONAL
H-
BRIDGE
CASCAD
E MLI
(
= +
=
= +
=
=
5 2 6 8
7 3 7 12
9 4 8 16
11 5 9 20
13 6 10 24
15 7 11 28
Table II: Switch Status
LEVEL OF
MLI
VOLTAGE
LEVEL
SWITCH STATUS (ON
SWITCHES)
5 LEVEL +200V SW1,SW2
+100V SW1,SW2,SW6
0V SW1,SW2,SW5/SW3,SW
4,SW5
-100V SW3,SW4,SW6
-200V SW3,SW4
7 LEVEL
+300V SW1,SW2
+200V SW1,SW2,SW7
+100V SW1,SW2,SW6
0V SW1,SW2,SW5/
SW3,SW4,SW5
-100V SW3,SW4,SW6
-200V SW3,SW4,SW7
-300V SW3,SW4
9 LEVEL +400 SW1,SW2
+300V SW1,SW2,SW8
+200V SW1,SW2,SW7
+100V SW1,SW2,SW6
0V SW1,SW2,SW5/
SW3,SW4,SW5
-100V SW3,SW4,SW6
-200V SW3,SW4,SW7
-300V SW3,SW4, SW8
-400V SW3,SW4
11 LEVEL
11 LEVEL
+500V SW1,SW2
+400V SW1,SW2,SW9
+300V SW1,SW2,SW8
+200V SW1,SW2,SW7
+100V SW1,SW2,SW6
0V SW1,SW2,SW5/
SW3,SW4,SW5
-100V SW3,SW4,SW6
-200V SW3,SW4, SW7
-300V SW3,SW4, SW8
-400V SW3,SW4, SW9
-500V SW3,SW4
13 LEVEL
VOLTAGE
LEVEL
SWITCH STATUS (ON
SWITCHES)
+600 SW1,SW2
+500V SW1,SW2, SW10
International Journal of Emerging Technologies and Engineering (IJETE)
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+400V SW1,SW2, SW9
+300V SW1,SW2,SW8
+200V SW1,SW2,SW7
+100V SW1,SW2,SW6
0V S1,SW2,SW5/
SW3,SW4,SW5
-100V SW3,SW4,SW6
-200V SW3,SW4, SW7
-300V SW3,SW4, SW8
-400V SW3,SW4, SW9
-500V SW3,SW4, SW10
-600V SW3,SW4
15 LEVEL +700V SW1,SW2
+600V SW1,SW2,SW11
+500V SW1,SW2, SW10
+400V SW1,SW2,SW9
+300V SW1,SW2,SW8
+200V SW1,SW2,SW7
+100V SW1,SW2,SW6
0V SW1,SW2,SW5/
SW3,SW4,SW5
-100V SW3,SW4,SW6
-200V SW3,SW4, SW7
-300V SW3,SW4, SW8
-400V SW3,SW4, SW9
-500V SW3,SW4, SW10
-600V SW3,SW4, SW11
-700V SW3,SW4
Table III: Comparison of RMS Voltage & % THD of
output voltage of different levels at different carrier
frequencies
VOLTAGE
MAGNITUDE
(RMS)
%THD OF OUTPUT
VOLTAGE
Carrier
Freq.
Level
of MLI
1K
Hz
2K
Hz
4K
Hz
1KHz
2KHz
4KHz
5
147
.3
145
.7
146
.4
22.84 20.96 20.23
7
209
.8
211
.5
212
.3
17.61 16.31 15.22
9
282
.8
281
.7
283
.4
13.50 12.57 11.80
11
13
426 426
.9
420
.2
8.74 8.6 8.09
15
503
.8
492
.1
501
.6
8.08 8.11 6.39
Table I shows number of switches required in proposed
MLI with that of conventional MLI for different levels.
Table II shows the ON switch combinations at different
MLI and voltage levels. Comparison of RMS Voltage
with that of % THD of output voltage at different
voltage levels and carrier frequencies has been shown in
Table III.
6. CONCLUSIONS
This paper presented a reduced switch MLI. As the
number of controlled switches is reduced, the cost is
reduced. It also reduces the complexity of gate signal
generation circuit. It has been observed that with the
increase in output voltage level output quality improves
and overall THD of output voltage is reduced. It has also
been seen that the overall THD of output voltage varies
with variation in multicarrier wave frequency. The
output voltage THD improves with the increase in
multicarrier wave frequency.
7. REFERENCES
Journal Papers:
[1] M. Kavitha, A. Arunkumar , NGokulnath3, S. Arun,
New Cascaded H-Bridge Multilevel Inverter Topology
with Reduced Number of Switches and Sources, IOSR
Journal of Electrical and Electronics Engineering
(IOSR-JEEE), 2(6), 2012, 26-36.
[2] Dr. Jagdish Kumar, THD Analysis for Different
levels of Cascade Multilevel Inverters for Industrial
Applications, International Journal of Emerging
Technology and Advanced Engineering, 2(10), 2012, 37
-44
[3] Jos Rodrguez, Jih-Sheng Lai and Fang Zheng Peng,
Multilevel Inverters: A Survey of Topologies,Controls
and Applications, IEEE transactions on industrial
electronics,49(4),2002,724-738.
[4] D.Mohan and Sreejit B. Kurub,
A Comparative Analysis of Multi Carrier SPWM
Control Strategies using Fifteen Level Cascaded H
bridge Multilevel Inverter , International Journal of
Computer Application, 41(21), 2012, 7 - 11.
[5] Gobinath.K, Mahendran.S, Gnanambal.I, New
cascaded h-bridgeMultilevel inverter with
International Journal of Emerging Technologies and Engineering (IJETE)
Volume 1 Issue 5, June 2014, ISSN 2348 8050
156
www.ijete.org
Improved efficiency, International Journal of Advanced
Research in Electrical, Electronics and Instrumentation
Engineering,2(4), 2013,1263 1271
[6]. Vadhiraj S, K. Narayana Swamy and B.P. Divakar,
Generic SPWM Technique for Multilevel Inverter, IEEE
, 2013.
[7] K. Gopalakrishnan, M. Sundar Raj and T. Saravanan,
Harmonic Evaluation of Multicarrier Pwm Techniques
for Cascaded Multilevel Inverter, Middle-East Journal
of Scientific Research 20 (7), 2014, 819 824.
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