Modeling of Non-Volatile

Memories With Silvaco

Dragica Vasileska
Professor
Arizona State University
Content
Introductory Concepts
Non-Volatile Memories
Explanation of Various Effects
Different Effects Implementation in Silvaco
Simulation Example
Market Shares by Product
Discretes & Opto 12.9%
0.5% Bipolar
Analog
14.9%
Logic 16.3%
Microprocessor 15.4%
Microcontroller 6.2%
DSP 3.1%
Microperipheral 5.7%
Memory
25%
Discretes & Opto 12.9% Discretes & Opto 12.9%
0.5% Bipolar
Analog
14.9%
Logic 16.3%
Microprocessor 15.4%
Microcontroller 6.2%
DSP 3.1%
Microperipheral 5.7%
Memory
25%
Semiconductor Memory
Classification
Read-Write Memory
Volatile
Read-Write
Memory
Non-Volatile
Read-Only Memory
Non-Volatile
EPROM
E
2
PROM
FLASH
Random
Access
Non-Random
Access
SRAM
DRAM
Mask-Programmed
Programmable (PROM)
FIFO
Shift Register
CAM
LIFO
Non-Volatile Memories
A non-volatile memory is a memory that can hold its
information without the need for an external voltage supply.
The data can be electrically cleared and rewritten
Examples:
Magnetic Core
Hard-disk
OTP: one-time programmable (diodes/fuses)
EPROM: electrically programmable ROM
EEPROM: electrically erasable and programmable ROM
Flash
IC memory classification
SRAM DRAM ROM
EPROM
PROM
EEPROM
FLASH EEPROM
Volatile memories
Lose data when power down
Non-volatile memories
Keep data without power supply
Stand-alone versus
embedded memories
This lecture: stand-alone
Non-volatile memory comparison
Cost-Performance Drivers
C
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(
$
)
10k
1k
100
10
1
0.1
0.01
1 10 100 1 10 100 1 10
ns s ms
Logic
SRAM
Logic in 1980
DRAM
ROM
Flash
EEPROM
HDD
HDD in
1980
Access
time
DRAM in 1980
10k
1k
100
10
1
0.1
0.01
1 10 100 1 10 100 1 10
ns s ms
Logic
SRAM
Logic in 1980
DRAM
ROM
Flash
EEPROM
HDD
HDD in
1980
Access
time
DRAM in 1980
Characteristics of
State-of-the-art NVM
MOSFET operation (very basic)
C
V
depletion depletion accumulation
V
fb
accumulation
V
fb
inversion
V
T
inversion
V
T
Current through the MOS transistor
I
V
gs
MOS transistor - simplistic
V
T
I
V
gs
MOS transistor - real
V
T
inversion inversion
Channel charge: Q ~ (V
gs
V
T
)
Channel current: I ~ (V
gs
V
T
)
Concept of the floating-gate memory
cell
MOS transistor: 1 fixed threshold voltage
Flash memory cell: V
T
can be changed by
program/erase
I
d
V
gs
MOS transistor Floating gate transistor
I
d
V
gs
programming
V
T
erasing
Floating gate transistor: principle
V
T
is shifted by injecting electrons into the floating gate;
It is shifted back by removing these electrons again.
CMOS compatible technology!
Control
gate
Floating
gate
Channel charge in floating gate
transistors
Control gate
Floating gate
silicon
Control gate
Floating gate
unprogrammed programmed
To obtain the same channel charge, the programmed gate needs a
higher control-gate voltage than the unprogrammed gate
Logic 0 and 1
I
d
V
gs
V
T
= -Q/C
pp
V
read
1 I
read
>> 0
0 I
read
= 0
Reading a bit means:
1. Apply V
read
on the control gate
2. Measure drain current I
d
of the
floating-gate transistor
When cells are placed in a matrix:
Control
gate
lines
drain lines
Programming and erasing the floating
gate
Control
gate
Floating
gate
Floating gate
Control gate
SiO
2
Si
3
N
4
Polysilicon
Band diagram (over-simplified!)
Program/erase of a floating gate
transistor
Floating gate is surrounded by insulating
material.
How to drive charge in and out of it?
Injection/ejection mechanisms:
Fowler-Nordheim tunneling (FN)
Channel Hot Electron Injection (CHE)
Irradiation (most common: UV, for EPROMs)
Conduction through SiO
2
V
D
V
G
Dominant current components:
Intrinsic quantummechanical conduction
Fowler-Nordheim tunneling
Direct Tunneling
Defect-related:
Trap-assisted tunneling
(via a molecular defect)
Current through large defects
(e.g. pinholes)
Intrinsic current is defined by geometry & materials
Defect-related current can be suppressed by engineering V
B
Gate oxide conduction - example
-2 -1 0 1 2 3 4 5
10
-14
10
-13
10
-12
10
-11
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3
V
G
(V)
|
I
G
|

(
A
)

Hard
breakdown
Unstressed oxide
SILC
Soft
breakdown
4 nm oxide
Program/erase mechanisms
Flash program and erase methods
CHE: Hot electron programming
Pinch-off high electric fields near drain hot carrier injection through SiO
2
Note: < 1% of the electrons will reach the floating gate power-inefficient
Hot holes
Hot electrons
Hole substrate current
Field kinetic energy overcome the barrier
Programming: Channel Hot Electron Injection
CHE: properties
Works only to create a positive V
T
shift
High power consumption: ~300 A/cell
(most electrons get to the drain: lost effort)
Moderate programming voltages
Risky: hot carriers can damage materials
May lead to fixed charge, interface traps, bulk
traps
Results in degradation of the cell (see later)
Fowler-Nordheim tunneling
Uniform tunneling through entire dielectric is
possible
V
T
-shift can be positive as well as negative
Can be used for program and erase
Requires high voltage and high capacitances
Little power needed (~10 nA/cell)
Risks of this technique:
Charge trapping in oxide
Stress-induced leakage current
Defect-related oxide breakdown
FN FN
Uniform or drain-side FN tunneling
Non-uniform: only for erasing; less demanding for the dielectric
Alternative: tunnel through interpoly
oxide
(erasing, combined with CHE program)
Less demanding for the tunnel oxide
Therefore less SILC and better retention
More demanding for interpoly oxide
Uses high voltage and low power
NOR and NAND flash technology
Flash reliability issues and scaling
Flash reliability concerns:
The regular reliability concerns of CMOS
Oxide breakdown
Interconnect problems (electromigration)

Specific for Flash:
Retention
Endurance
Scaling:
Can we make the flash cell more compact?
Dominant problem: scaling the dielectrics
Reliability issues
Specific problems in non-volatile memories:
Fast programming and erasing (~10
-6
s) is done by
controlled tunnelling, leads to oxide degradation (trapping)
Functional requirements
no charge leaking in stand by situation
(up to 3
.
10
8
s)
distinguish 0 and 1 even after intensive use
In a 10 MB memory, should every single bit be OK?
Trade-off: reliability error detection & correction
( )
)
`

)
`

+ =
kT
E
t V V V t V
a
th th th th
exp exp ) 0 ( ) (
0 0

Retention
Ability to retain valid data for a prolonged period of time
under storage conditions (non-volatile).
Single Cell:
time before change of 0.1% change in stored data while not
under electrical stressIntrinsic retention
Array of Cells:
retention of the worst cell in the array before and after
cyclingdefect related = Extrinsic retention
Alzheimers Law:
Data retention prohibits tunnel
oxide scaling
7-8 nm is the bare minimum
Retention: summary
Retention = the ability to hold on to the charge
Loss > 5 electrons per day is killing in the long run
Mostly limited by defects in the tunnel oxide
Retention can be compromised with error
correction
For thin oxides < 7 nm, the retention of Flash is
intrinsically insufficient
To test retention, measure at different T and field
Endurance (uithoudingsvermogen)
Ability to perform even after a large number of
program/erase cycles
Showstoppers:
Oxide breakdown
Loss of memory window
Shift in operating margin
Endurance: oxide breakdown
A dielectric will break down when a certain amount of charge
has crossed it: this amount is Q
BD
.
Typical for good SiO
2
material: Q
BD
= 10 C/cm
2
.
Simple relation:
n
pe
the number of program/erase cycles until breakdown
V
fg
the shift between the 0 and 1 state
Good engineering gives a grip on Q
BD
then, no problem
C V
A Q
n
fg
inj bd
pe

=
Endurance: window closing
Program/erase cycles
Fixed charges appear
in the tunnel oxide after
program/erase cycles
ITRS 2007: long-term vision on NVM
Retention vs. alterability
Device Simulator Needs
If one needs to investigate, verify, and optimize designs for nonvolatile
memories, such as EPROMs, EEPROM s, and Flash EEPROMs then you
need a device simulator to account for a variety of physical effects such
as
band-to-band tunneling,
Fowler-Nordheim tunneling,
impact ionization, and
floating gates.
Self-consistent descriptions of these effects (not just
postprocessing approximations) are required.
Both steady-state and time-domain transient simulation
capabilities are desirable.
Time-domain capabilities provide self-consistent (rather than
less accurate quasi-static) calculations of programming and
erasing operations
Silvaco Capabilities
These capabilities are incorporated in the robust general
purpose device simulators HFIELDS-2D and S-Pisces 2B.
Charge boundary conditions,
Fowler-Nordheim tunneling and
band-to-band tunneling are all self-consistently simulated.
In addition, a newly developed numerical algorithm that greatly
reduces the mesh sensitivity of calculated gate current is used.
This mesh sensitivity limits the accuracy and reliability of some
other programs that seek to simulate nonvolatile memory
devices.
Cross-sections of NVM cells
Explanation of Various Effects
Fowler-Nordheim Tunneling
Lucky Electron Model
Band to Band Tunneling
Some General Comments
For sub-micrometer devices, due to smaller oxide thickness, there is
significant conductance being measured on the gate contact. The finite
gate current gives rise to the following effects:
Negative => degradation in the device operating characteristics with
time due to oxide charging; larger off-state power dissipation
Positive => non-volatile memories utilize the gate current to program
and erase charge on the floating contact FLASH, FLOTOX,
EEPROM
There are two different types of conduction mechanisms to the insulator
layer:
Tunneling: Fowler-Nordheim or direct tunneling process
Hot-carrier injection: lucky electron model or Concannon model
Electron is emitted into the oxide
when it gains sufficient energy to
overcome the insulator/semicon-
ductor barrier.
Similar to the lucky electron model, but
assumes non-Maxwellian high energy tail on
the distribution function.
Requires solution of the energy balance
equation for carrier temperature.
Oxide Charging
Electrons at the drain end of the
channel have sufficient energy
to overcome the barrier at the
Si/SiO
2
interface and be
trapped in the oxide
Since the effect is cumulative, it
limits the useful life of the
device
(LDD regions are used to
reduce oxide charging)
The various oxide charging
mechanisms, that lead to
threshold voltage shift, are
summarized in the figure on the
right
Figure from textbook by Sze:
Semiconductor device theory
Tunneling Currents
Three types of tunneling processes are schematically shown below
(courtesy of D. K. Schroder)
For t
ox
40 , Fowler-Nordheim (FN) tunneling dominates
For t
ox
< 40 , direct tunneling becomes important
I
dir
> I
FN
at a given V
ox
when direct tunneling active
For given electric field: - I
FN
independent of oxide thickness
- I
dir
depends on oxide thickness

B
V
ox
>
B
V
ox
=
B
V
ox
<
B
FN FN/Direct Direct
t
ox

B
V
ox
>
B
V
ox
=
B
V
ox
<
B
FN FN/Direct Direct
t
ox
Significance of Gate Leakage
10
-16
10
-14
10
-12
10
-10
10
-8
10
-6
10
-4
0 50 100 150 200 250
C
u
r
r
e
n
t

(
A
/

m
)
Technology Generation (nm)
I
on
I
G
I
off
As oxide thickness decreases, the gate current becomes more
important. It eventually dominates the off-state leakage current (I
D
at
V
G
= 0 V)
The drain current I
D
as a function of technology generation is shown
below (courtesy of D. K. Schroder)
Fowler-Nordheim Tunneling
0
E
F

B
0
E
F

B
a
No applied bias With applied bias
- eEx
x-axis
The difference between the Fermi level and the top of the barrier is
denoted by
B
According to WKB approximation, the tunneling coefficient through this
triangular barrier equals to:
(

a
dx x T
0
) ( 2 exp
where: ( ) eEx
m
x
B
=
2
* 2
) (

Fowler-Nordheim Tunneling
(contd)
The final expression for the
Fowler-Nordheim tunneling
coefficient is:
Important notes:
The above expression
explains tunneling process
only qualitatively because
the additional attraction of
the electron back to the plate
is not included
Due to surface
imperfections, the surface
field changes and can make
large difference in the results
(
(

eE
m
T
B
3
* 2 4
exp
2 / 3
Calculated and experimental tunnel
current characteristics for ultra-thin oxide
layers.
(M. Depas et al., Solid State Electronics, Vol.
38, No. 8, pp. 1465-1471, 1995)
Silvaco Implementation
In Silvaco ATLAS, the Fowler-Nordheim tunneling currents are
calculated using the following expressions:
where:
E => magnitude of the electric field in the oxide
F.AE, F.BE, F.AH and F.BH => model parameters that can be
defined via the MODEL statement
There are two different ways in which Fowler-Nordheim tunneling is
implemented within the solution procedure:
As a post-processing option => specify FNPP on the MODEL
statement
Within the self-consistent scheme => specify FNORD on the
MODEL statement
( )
( ) E E J
E E J
FP
FN
/ exp
/ exp
2
2
F.BH F.AH
F.BE F.AE
=
=
Silvaco Implementation (contd)
The actual implementation scheme is as follows:
Each electrode/insulator and each insulator/SC interface is divided
into segments based upon the mesh
For each SC/insulator segment, the tunneling current expressions
given in the previous slide, are used to calculate J
FN
and J
FP
The as-calculated tunneling currents are then added to the metal-
insulator segment using the following two criteria:
Model one (default) => The segment that receives the current
has to be on the path of the electric field vector at the SC/oxide
interface.
Model two (NEARFLG parameter on the MODEL statement)
=> The electrode/insulator segment that is nearest to the
insulator/SC segment receives all the current
Lucky Electron Model Explained
oxide
p-type SC substrate
n
+
n
+
S D
Gate
P
1
P
2
P
3
P
4
K.E. P
1
P
2
P
3
P
4
substrate oxide gate

B
x
0
P
1
=> probability that the electron gains sufficient energy from the electric field to
overcome the potential barrier
P
2
=> probability for redirecting collision to occur, to send the electron towards the
SC/insulator interface
P
3
=> probability that the electron will travel towards the interface without loosing
energy
P
4
=> probability that electron will not scatter in the image potential well
Description from:
K. Hasnat et al., IEEE TED 43, 1264 (1996).
Mathematical Description
The various probabilities described in the previous slide are calculated
using:
=> scattering mean-free path

r
=> redirection mean-free path

B
=> barrier height at the SC-oxide interface

ox
=> mean-free path in the oxide (3.2 nm)
The total gate current is then given by:
|
|

\
|

=
|

\
|

= |

\
|

=
|
|

\
|

=
ox
B
r x x
x
P
y
P P d
E E
P
0
4 3 2 1
exp , exp , 1
2
1
, exp
1

3 / 2 2 / 1
0 ox ox B B
E E =
Zero-field barrier
height
Barrier lowering due
to image potential
Accounts for probability
for tunneling
4 3 2 1
) , ( P P P P y x J d dxdy I
B
n g

=

Silvaco Implementation
Assumes non-Maxwellian distribution function, which requires solution
of the energy balance equations for the carrier temperature.
The model is specified with the parameters N.CONCANNON and
P.CONCANNON on the MODELS statement.
Two other parameters of the MODEL statement, which affect the
numerical integration of the current, are definable by the user:
ENERGY.STEP (default 25 meV) and INFINITY parameter (upper limit
of integration).
The Concannons injection model
In the Silvaco ATLAS implementation of the lucky-electron model, the
probabilities P
1
and P
2
have actually been merged together.
(see description of the model and the various parameters that need to
be specified on pages 3-76 to 3-79 via the MODEL statement).
It is activated via the MODEL statement by the parameters HEI (hot
electron injection) or HHI (hot hole injection)
The implementation of the model is similar to the Fowler-Nordheim
tunneling (see slide 9 for details).
More on Silvaco Implementation
The specification of one or more electrodes as floating is
accomplished via the parameter FLOATING on the CONTACT
statement
Modeling of the correct coupling capacitance between the FG
(floating gate) and the CG (control gate) is accomplished via the
parameters:
FLG.CAP additional capacitance per unit length between FG and CG
ELE.CAP specifies the index of the (wider) control gate
on the CONTACT statement
During the write or erase cycles, the gate currents arise because of:
hot-electron injection (HEI or N.CONCANNON)
hot-hole injection (HHI or P.CONCANNON)
Fowler-Nordheim tunneling (FNORD)
band-to-band tunneling (BBT)
Gate current assignment can be:
- in the direction of highest contributing field (drift current)
- geometrically closest electrode for diffusion current (NEARFL)
More on Silvaco Implementation
(contd)
Additional parameters that has been specified in the EPROM example,
in conjunction with the METHOD statement include:
AUTONR Automated Newton-Richardson procedure that attempts to
reduce the number of LU-decompositions per bias point
PR.TOL Absolute tolerance for Poisson equation
PX.TOL Relative tolerance for Poisson equation (P.TOL)
CR.TOL Absolute tolerance for continuity equation
CX.TOL Relative tolerance for continuity equation (C.TOL)
Parameters specified in the EPROM example in conjunction with the
SOLVE statement include:
PREVIOUS Use previous solution as initial guess
PROJECT Extrapolation from the last two solutions will be used
as an initial approximation (guess)
Q<n> Specifies charge on an electrode n
QSTEP Charge increment to be added to one or more
electrodes
QFINAL Final charge for a set of bias increments
Different Effects Implementation in Silvaco
Erase Cycle
Band to Band Tunneling
Threshold Voltage Shift
Role of Control Voltage
Programming Characteristics
Silvaco Example for Modeling Memories
The following EEPROM
simulations were generated
using S-Pisces 2B to illustrate
the effect of varying the tunnel
oxide thickness from 75 to 120
Figure 1). The device structure
was generated by SSuprem4.
The channel length is 0.7
microns and the gate oxide
thickness is 200 A.
Erase Characteristics
Figure 2. EEPROM device
simulation showing erase
characteristics associated with
different
tunneling oxide thicknesses.
Importance of BBT
Figure 3 illustrates the
importance of accounting for
band-to-band tunneling
during erasure. The substrate
current behavior during
erasure cannot be
determined accurately
without accounting for
tunneling effects in the
model..
Threshold Voltage Shift
Figure 4 shows threshold
voltage shift as a function of
the charge on the floating
gate.
Gate Current Dependence on Control Voltage
Figure 5 shows gate
current dependence on
the control voltage.
Programming Characteristics
Figure 6, transient
programming
characteristics for
different drain voltages,
clearly demonstrates the
strong dependence of
programming times on
drain-source voltage
Simulation Example
Problem Statement
Listing of the Code
Simulation Results
Example:
Write and Erase of an EPROM
Threshold Voltage Before Programming
Programming Cycle
Threshold Voltage Shift = Q Tox/L Eox
Erase cycle with Drain contact disconnected by
adding a very large resistor in series
The source electrode is ramped to 12.5 V
Floating gate Memory
Threshold voltage before
programming
# Set workfunction for the poly gates,

contact name=fgate n.polysilicon floating
contact name=cgate n.polysilicon
#Define some Qss...
interface qf=3e10
models srh cvt hei fnord print nearflg
impact selb
######### This is the Vt Test before programming #############
##############################################################
solve init
method newton trap maxtraps=8 autonr
log outf=eprmex01_2.log
solve vdrain=0.5
solve vstep=0.5 vfinal=25 name=cgate comp=5.5e-5 cname=drain
# plot idvg
tonyplot eprmex01_2.log -s eprmex01_2.set
# extract vt
extract name="initial vt" ((xintercept(maxslope(curve(v."cgate",i."drain"))))-abs(ave(v."drain"))/2.0)
######### This is the Programming/Writing Transient ###########
###############################################################
# use zero carriers to get vg=12v solution
models srh cvt hei fnord print nearflg
method carriers=0
log off
solve init
solve vcgate=3
solve vcgate=6
solve vcgate=12
# now use 2 carriers
models srh cvt hei fnord print nearflg
impact selb
method newton trap maxtraps=8 carriers=2
solve prev
log outf=eprmex01_3.log master
# ramp up drain voltage
solve vdrain=5.85 ramptime=1e-9 tstep=1e-10 tfinal=1e-9 proj
# keep voltages constant and perform transient programming
solve tstep=1e-9 tfinal=5.e-4
# plot programming curve
tonyplot eprmex01_3.log -set eprmex01_3.set
# save the structure
save outf=eprmex01_2.str
Ramping the
Control gate
Voltage with
Zero carriers
Doing the programming while
Keeping the voltages the same
######### This is the Vt Test After Programming ###########
###########################################################
method newton trap maxtraps=8 autonr
log outf=eprmex01_4.log master
solve init
solve vdrain=0.5
solve vstep=0.5 vfinal=25 name=cgate comp=5.5e-5 cname=drain
# plot new idvg overlaid on old one
tonyplot -overlay eprmex01_2.log eprmex01_4.log -set eprmex01_4.set
# extract vt and vt shift
extract name="final vt" ((xintercept(maxslope(curve(v."cgate",i."drain"))))-abs(ave(v."drain"))/2.0)
extract name="vt shift" ($"final vt" - $"initial vt")
######## This is the Erasing Test ######################
########################################################
go atlas
# select erasing models

models cvt srh fnord bbt.std print nearflg \
F.BE=1.4e8 F.BH=1.4e8
impact selb
contact name=fgate n.poly floating
contact name=cgate n.poly
interface qf=3e10
method carr=2
# get initial zero carrier solution
solve init
# ramp the floating gate charge
method newton trap maxtraps=8
solve prev
solve q1=-1e-16
solve q1=-5e-16
solve q1=-1e-15
solve q1=-2e-15
solve q1=-3.5e-15
solve q1=-5e-15
# put a resistor on drain
contact name=drain resistance=1.e20
# do Erasing transient
method newton trap maxtraps=8 autonr c.tol=1.e-4 p.tol=1.e-4
log outf=eprmex01_5.log master
solve vsource=12.5 tstep=1.e-14 tfinal=4.e-1
tonyplot eprmex01_5.log -set eprmex01_5.set
Erasing Cycle
Source current