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APPLICATION NOTE
One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 Tel: 781/329-4700 Fax: 781/461-3113 www.analog.com
INTRODUCTION
This application note describes the AD9889s EDID and
HDCP controller and is intended to assist the system
designer to specify the system software functions
necessary to properly incorporate EDID and HDCP
handling procedures when using the AD9889 HDMI
transmitter.
AD9889 EDID/HDCP SUPPORT FEATURES
The AD9889s EDID and HDCP controller performs four
main functions to support the systems EDID and HDCP
handling. These features are outlined here. A block
diagram is illustrated in Figure 1.
EDID and HDCP Controller Users Guide for the AD9889
by Del Jones
1. Reads EDID segment 0 from the display as soon as
Hot Plug is detected.
The 256-byte EDID segment is stored in internal
RAM and can be read via I
2
C

and has its own

I
2
C address. The I
2
C slave address of the EDID
memory can be programmed in the EDID ID
register (0x43). The default value for this regis-
ter is 0x7E.
2. Reads additional EDID segments on demand.
These segments are stored in the same location
as the rst segment. Therefore, the controller
should store the rst segment prior to initializ-
ing another EDID segment download.
3. Implements the HDCP transmitter state machine
including handling of downstream repeaters.
4. Includes robust error reporting to report various
error conditions to the system rmware.

I
2
C SLAVE BUS
SIGNALS TO/FROM OTHER
PARTS OF THE AD9889

DDC BUS
Figure 1. AD9889 HDCP Controller Block Diagram
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STARTUP SEQUENCE PERFORMED BY AD9889
The AD9889s EDID and HDCP controller is a state machine
which is implemented in the AD9889s hardware. The
following list of instructions illustrates the sequence in
which the state machine performs the EDID and HDCP
handling.
Note that in the following sequence, the term System
always refers to the software that is in control of the
system and is responsible for conguring the AD9889
through the I
2
C port. The term User refers to the end
user of a product using an AD9889.
0. The AD9889 HDCP controller stays in reset until HPD
is high.
1. When HPD is high, the AD9889 reads EDID segment
0 and sends an EDID Ready interrupt to the system.
The EDID Ready ag (0xC5[4]) is set once the
EDID has been read successfully.
2. After reading the EDID the AD9889 waits for the HDCP
Desired bit (0xAF[7]) to go high.
3. System software evaluates the EDID, congures the
AD9889 by setting the appropriate video and audio
modes, and then sets the HDCP Desired bit to high
(the status of this bit is also reected in 0xC6[3]).
The Frame Encode bit (0xAF[4]) should also be set
to 1
1
. The HDMI/DVI bit (0xAF[1]) should not be
changed after setting the HDCP Requested bit.
4. Once HDCP Requested is high, the AD9889 initializes
the HDCP system.
The receivers BKSV is reported in the BKSV
registers (0xBF to 0xC3) and the BKSV ag is
set (0x97[6]) (generates an interrupt) and the
BKSV count (0xC7[6:0]) is set to 0.
The BKSV ag is also reected in 0xC7[7].
5. The system must check the BKSV against the revoca-
tion list and clear the BKSV Flag (write 1 to 0x97[6])
interrupt if it is not on the revocation list.
If not OK then the system should report this to the
user in the video stream and not send protected
content.
Revocation lists are provided as part of the
source media (i.e., on the DVD).
6. Once the BKSV ag is cleared, the AD9889 begins
HDCP encryption and checks if the receiver is a
repeater.
The AD9889 checks the receivers DDC register
bit which indicates if it is a repeater.
If not a repeater, then HDCP initialization is com-
plete and the AD9889 begins HDCP management.
The status of the HDCP encryption can be veried
by reading 0xB8[6].
If the receiver is a repeater, the AD9889 must complete
the HDCP repeater authentication:
7. AD9889 reads up to 13 KSVs from the downstream
repeater (the AD9889 can only process 13 at a time).
8. AD9889 signals a BKSV Flag interrupt with the BKSV
count (can be up to 13).
9. System rmware reads the BKSVs from the EDID
memory and checks them against the revocation list.
Note that the EDID and HDCP handling share
the AD9889s internal memory. EDID is reread
at the end of HDCP initialization.
System rmware clears the BKSV Flag interrupt.
10. AD9889 calculates the SHA-1 hash of the KSVs.
If more KSVs remain (there are more than 13
downstream devices), then go back to Step 8.
All of the SHA-1 hash values from each
iteration (each set of 13 KSVs) are added before
the comparion is done in Step 11.
11. AD9889 compares downstream SHA-1 hash to internal
hash to verify KSV list.
12. Once all KSVs have been verified, the AD9889
begins HDCP management and protected content can
now be transmitted.
1
In some applications, it may be desirable to initiate HDCP without encrypting the data (for example, if an unencrypted DVD is played). In this case, the Frame
Encode bit does not need to be set.
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7.
A) READ
DOWNSTREAM
KSVs
8.
B) SET BKSV
FLAG
C) REPORT KSV
COUNT
9.
READ BKSVs
FROM AD9889
AND EVALUATE
YES NO
BKSV FLAG = 0
BKSV INT
HDCP REQ = 1
EDID READY
INTERRUPT
HPD = 1
IF HDCP REQ = 0
2
HPD = 0
1
HPD = 0
NO
ERROR INTERRUPT
YES
NO
BKSV FLAG = 0
ERROR INTERRUPT
(IF STATE > 6)
NO
YES
GO TO STATE 1
YES
NO
NOTES:
1. ANY OCCURANCE OF HPD = 0
WILL RESET THE AD9889
EDID/HDCP CONTROLLER.
2. IF BKSV IS REVOKED, THE
SYSTEM SHOULD CLEAR THE
HDCP REQUEST FLAG TO
ENABLE A REAUTHENTICATION.
3. DENOTES FUNCTIONS
CONTROLLED BY THE
AD9889.
4. DENOTES FUNCTIONS
CONTROLLED BY THE
SYSTEM SOFTWARE.
NO. OF BKV'S
YES
11.
SHA-1 HASH
MATCH?
MORE KSVs?
10.
AD9889
CALCULATES
SHA-1 HASH
VALUE
FOR KSVs
BKSVs
REVOKED?
A) REPORT TO
USER
B) DO NOT SEND
PROTECTED
CONTENT
REPEATER?
12.
BEGIN HDCP
MANAGEMENT
(PROTECTED
CONTENT CAN
NOW BE
SENT)
0. RESET
1.
A) READ EDID
B) EDID RDY = 1
2.
WAIT FOR HDCP
REQUEST
4.
A) INITIATE HDCP
B) SET BKSV
FLAG
C) WRITE BKSV
REGISTERS
3.
A) EVALUATE
EDID
B) CONFIGURE
A/V OF AD9889
C) SET HDCP
REQUEST
6. BEGIN HDCP
ENCRYPTION
A) REPORT TO
USER
B) DO NOT SEND
PROTECTED
CONTENT
5.
READ BKSV
FROM AD9889
BKSV
REVOKED?
ERROR INTERRUPT
(IF STATE </= 6)
GO TO STATE 1
Figure 2. AD9889 EDID and HDCP Controller Functional Flow
EDID and HDCP Handling Flow Chart
The EDID and HDCP handling sequence can also be summarized by the ow chart in Figure 2.
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HDCP Management
Once the authentication is complete, the AD9889 will
manage the ongoing HDCP link authentication. Every 128
frames, the Ri on the receiver is checked against the Ri
on the transmitter. Ri is the video transmit and receive
synchronization verication value. This informs the user
that the transmitter and receiver are synchronized. A
failure will generate an HDCP/EDID Controller Error inter-
rupt and restart the HDCP authentication.
If the receiver supports HDCP 1.1, the AD9889 will check
Pj on the receiver against Pj on the transmitter every
16 frames. Pj is the link synchronization verication
value computed every 16 frames xored with the rst
pixel. This also informs the user that the transmitter
and receiver are synchronized. A failure will generate
an HDCP/EDID Controller Error interrupt and restart the
HDCP authentication.
The system firmware should periodically check the
state of the Encryption On status bit (0xB8 [6]) while
sending protected audio or video to ensure that HDCP
is enabled. This should be checked with a frequency of
no less than once every two seconds. Checking this bit
protects against third party meddling with the AD9889s
register settings to defeat HDCP.
In the case where a BKSV is revoked, the system soft-
ware still needs to periodically try to reauthenticate. To
do this, clear the HDCP request bit, enable the EDID inter-
rupt, and clear the BKSV ag. Once the AD9889 reaches
state 1 (0xC8[3:0] = 2), set the HDCP request ag back
to 1. This will allow the AD9889 to try reauthenticating
(transition from Step 12 to Step 4).
Handling a BKSV Flag Interrupt
Table I lists the interrupt conditions that are generated
by the AD9889s HDCP controller engine. The appropriate
system software response and other comments are also
noted.
Additional HDCP Controls
Frame Encrypt Bit (0xAF [4])
The Frame Encode bit can be used to temporarily disable
HDCP encryption while maintaining HDCP synchroniza-
tion. When this bit is set to 0, encryption is disabled.
Setting it back to 1 will re-enable encryption. While
disabled, the status is reported by the Encryption On
bit (0xB8 [6]), which goes low while Frame Encrypt = 0.
Synchronization checks continue if receiver supports
that feature.
AV Mute Bits (0x45 [7:6])
The AV Mute may be used to keep HDCP synchronization
during a TMDS clock frequency change (if, for example,
the user wants to change from 480 p to 720 p or from 480 p
to 480 p with 2x pixel repetition).
To use the AV Mute function:
1. Set the Set AV Mute bit (0x45 [6]) to 1 and the
Clear AV Mute bit (0x45 [7]) to 0.
2. Enable the General Control Packet (set 0x40 [7]
to 1).
3. Wait for at least 15 video elds to be sent.
4. Change to the new video mode.
5. Wait for at least 1 video eld to be sent.
6. Set the Set AV Mute bit to 0 (0x45 [6]) and the Clear
AV Mute bit to 1 (0x45 [7]).
7. Wait for 4 Vsyncs to be sent.
8. Set Clear AV Mute bit to 0 (0x45 [7]).
Table I. HDCP Interrupt Conditions
Interrupt Condition System Software Response Notes
If BKSV Count (reg. 0xC7 [6:0]) equals 0 Read the BKSV register (0xBF to 0xC3) and
check against revocation list
If BKSV Count is greater than 0 Read the BKSVs from the EDID memory Each BKSV is 5 bytes so you must read
at address 0 5 BKSV Count bytes
If a BKSV is on the revocation list May be result of I
2
C error so reset AD9889 After checking the BKSV(s), the system
and restart HDCP (set HDCP requested to 1) should clear the BKSV Flag interrupt so the
AD9889 can continue HDCP authentication
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State Register
The current state of the HDCP controller can be read from
the HDCP Controller State I
2
C register (0xC8 [3:0]). The
codes for this register are shown in Table II.
Table II. HCDP Controller Status
Reg 0xC8 [3:0] HDCP Controller State
0000 In Reset (No Hot Plug Detected)
0001 Reading EDID
0010 IDLE (Waiting for HDCP Requested)
0011 Initializing HDCP
0100 HDCP Enabled
0101 Initializing HDCP Repeater
Error Reporting
If an error occurs, the AD9889 will set the error ag (0xC5[7]),
causing an interrupt. An error code is then reported in the
HDCP Controller Error register (0xC8 [7:4]). Table III lists
the possible error conditions and the corresponding 4-bit
error code.
Table III. Error Code Denitions
Error Code Error Condition
0000 No Error
0001 Bad Receiver BKSV
0010 Ri Mismatch
0011 Pj Mismatch
0100 I
2
C Error (usually a no-ack)
0101 Timed Out Waiting for Downstream
Repeater DONE
0110 Max Cascade of Repeaters Exceeded
0111 SHA-1 Hash Check of KSV List Failed
1000 Too Many Devices Connected to
Repeater Tree
Error Handling
The AD9889s HDCP engine will automatically restart
the authentication process on any error. As long as the
HDCP requested bit remains high, the HDCP engine will
continue to reauthenticate the HDCP link. The system
should not set the HDCP requested bit low as an HDCP
error could be caused by the receiver not being enabled
or selected.
It should be noted that on two-port display, a disabled
port may not acknowledge an HDCP request until the
user selects that input port to be active.
Other Notes
The system software should always clear the HDCP
Error interrupt after it has been serviced so that
subsequent errors will generate a new interrupt.
The error code always shows the last error even if
the error interrupt has been cleared. In other words,
the error code is only cleared by a power-on reset or
replaced by a new error code.
ADDITIONAL EDID CONTROL
EDID Denitions
Extended EDID (E-EDID) supports up to 256 segments.
A segment is a 256-byte segment of EDID containing one
or two EDID blocks. A normal HDMI system will have
only two EDID blocks and so will only use segment 0.
The rst EDID block is always a base EDID 1.3 structure;
the second EDID block is usually CEA 861B block dened
for HDMI systems.
EDID Tries Register (0xC9 [3:0])
The number of times the HDCP/EDID controller will try
to read the EDID is limited by the EDID Tries register.
Each time an EDID read fails, this value is decremented.
The default start-up value of this register is 3. Once the
EDID Tries register is 0, the controller will not attempt
to read the EDID until this register is set to something
other than 0.
EDID Segment Register (0xC4)
If it is necessary to read a segment other than 0, the
system software should set the EDID Segment register
to the desired segment and wait for the EDID Ready ag
to return to high. This will generate an interrupt.
EDID/HDCP Shared Memory
The EDID and HDCP controllers use shared memory
space. During HDCP Repeater initialization, the EDID
memory is overwritten and the EDID Ready ag goes
low. After initialization, the EDID is reread and the EDID
Ready ag is set to 1. The setting of EDID Ready ag
to 1 will cause an interrupt if this interrupt is enabled.
If an interrupt is not desired, the EDID interrupt should
be disabled after the EDID has been processed by the
system software.
The I
2
C slave address of the EDID memory can be pro-
grammed in the EDID ID register (0x43). The default
value for this register is 0x7E.
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2
C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I
2
C
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2
C system, provided that the system conforms to the I
2
C Standard Specication as dened by Philips.
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