DAC 2006

Reliability Challenges
for 45nm and Beyond
J. W. McPherson, PhD, TI Senior Fellow
Texas Instruments, Inc.
Dallas, Texas 75243
1
Outline
Transistor Performance with Scaling
Gate Dielectric Scaling
Interconnect Scaling
Reliability Trends with Continued Scaling
--- Leakage --- NBTI --- ESD --- SM
--- TDDB --- CHC --- EM --- Joule Heating
Defect Issues with Continued Scaling
Conclusions/Summary
2
Lightly Doped Drain (LDD)
Channel Region
Source/Drain
Sidewall Spacer
Polysilicon Gate
Gate Oxide
Salicide
Cladding
Silicon
Substrate
GATE SOURCE DRAIN
MOSFET Scaling : More Evolutionary than Revolutionary for 25 years
3
LighlyDoped Drain (LDD)
Channel Region
Source/Drain
SidewallSpacer
PolysiliconGate
Gate Oxide
Salicide
Cladding
Silicon
Substrate
MOSFET Scaling: More Evolutionary than Revolutionary
( )
dd ct Interconne Gate Junction
drive
V C C C
I
FOM
+ +
=
1.00E-14
1.00E-12
1.00E-10
1.00E-08
1.00E-06
1.00E-04
1.00E-02
-0.2 0 0.2 0.4 0.6 0.8 1 1.2
Vgs (V)
I
d
s

(
A
)
Subthreshold slope remains
nearly constant from
technology node to node:
Vt must be reduced to
maintain good Idrive at
lower Vdd
Ioff increases with lower Vt due to
constant subthreshold slope
Transistor I
drive
Versus I
off
Trends
Increased transistor I
drive
usually implies increased I
off
4
Strained-Silicon Performance Enhancement
Raised S/D
PMD liner
STI liner
Implant S/D
strain
Recess S/D epi
Acti ve
area epi
Substrate
orientation
Capped poly
Strained
channel
Normal Si lattice Strained Si latti ce
Improved
mobili ty
Raised S/D
PMD liner
STI liner
Implant S/D
strain
Recess S/D epi
Acti ve
area epi
Substrate
orientation
Capped poly
Strained
channel
Normal Si lattice Strained Si latti ce
Improved
mobili ty
Significant Ion/Ioff improvement
1. Strained Si can produce an increase in I
on
without a degradation in I
off
.
2. Stress-induced defects can occur in the
silicon if the stress is not applied properly.
Defect in Silicon
-6
I
o
f
f
l
o
g

(
A
/

m
)
Ion (A/m)
35 % improvement
40 nA/m
680 A/m
-10
-9
-8
-7
300 500 700
Reference
SiGe
-6
I
o
f
f
l
o
g

(
A
/

m
)
Ion (A/m)
35 % improvement
40 nA/m
680 A/m
-10
-9
-8
-7
300 500 700
Reference
SiGe
I
o
f
f
l
o
g

(
A
/

m
)
Ion (A/m)
35 % improvement
40 nA/m
680 A/m
-10 -10
-9
-8
-7
300 500 700
Reference
SiGe
5
Impact of Scaling on Gate-Dielectric Leakage
EOT ()
0 5 10 15 20 25 30
G
a
t
e

L
e
a
k
a
g
e

(
A
/
c
m
2
)
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
10
4
High Performance
Low Power
SiO
2
Trendline
Nitrided oxide
Gate leakage approaching 1000A/cm2. Nitrided oxides a little less.
6
Impact of High-k on Gate-Dielectric Leakage
EOT ()
5 10 15 20 25
J
g

@

(
|
V
f
b
|
+
1
)

(
A
/
c
m
2
)
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
10
4
nMOSCAP HfSiON
pMOSCAP HfSiON
NMOS SiO
2
Trendline
nMOSCAP HfON
Gate Leakage
SiO
2
Trendline
HfSiON
k high
k high
SiO
thickness
k
k
EOT

= ) ( ) (
2
High-k thickness can be kept
relatively thick, to control leakage,
while EOT can be made quite low.
7
Interconnect Scaling Trends
A
2
A
1
Cu
Cu Cu
w
s
L
Low-k
1
Low-k
1
t
s
t
2
t
2
Low-k
2
Low-k
2
Cu
Cu
Cu
Cu Cu

=
2 1
2
2
1
1
2
t t
s w
k
k
s w
L k
RC
o Cu

1. Cu resistivity going up with scaling (due to boundary scattering).
2. Reduction in interconnect dielectric constant k has been slow.
3. Metal width w and space s continue to reduce with scaling.
4. Length L impacted by design/architecture.
8
Interconnect Low-k Dielectric Introduction
1997 ITRS
1999 ITRS
2001 ITRS
2003 ITRS

1
1.5
2
2.5
3
3.5
4
4.5
1995199719992001200320052007200920112013
Year of Production
D
i
e
l
e
c
t
r
i
c

k
-
v
a
l
u
e
2003 2003
ITRS ITRS
2001 ITRS 2001 ITRS
1999 1999
ITRS ITRS
1997 ITRS 1997 ITRS
ITRS Roadmap for Low-k Interconnect Dielectric
S
l
i
p
p
i
n
g
Actual k~2.9
Introduction rate for Low-k interconnect dielectrics has
been slow and continues to slip
9
Reliability Trends
with
Continued Scaling
10
0
5
10
15
20
25
0 2 4 6 8 10
GATE VOLTAGE (Volts)
A
F




(
V
-
1
)
Agere
IBM
IMEC
TI
V- FIT
TDDB Trends for SiO
2
Gate Dielectrics
TI: P. Nicollian
IEDM (2005)
Extensive TDDB testing carefully recording: Hard Breakdown, Soft-
Breakdown and Stress-Induced Leakage Current
Continual validation of power-law model with a complete physics
understanding, e.g., roles of hydrogen species: H
0
and H
+
Carefully avoiding over-voltage conditions in designs and use conditions
Ramped to breakdown testing for each wafer lot using skew and outlier
statistical analysis for control
Power Law Model
t
BD
= aV
G
-N
AF = N/V
G
10.3
6.3
7.3
8.1
9.1
5
6
7
8
9
10
11
12
13
0 10 20 30 40 50 60
N (at%)
E
O
T




(

)
k(SiO
2
) = 3.9
k(Si
3
N
4
) = 7.5
t
PHYSICAL
= 12
Lose bulk SiO
2
properties
below 2 mono layers.
12 t
PHYS
for manufacturing.
S. Tang Apl. Surf. Sci 137 (1998)
M. Green JAP 90 2057 (2001)
E. Wu IEDM 541 (2000)
TI: P. Nicollian IRPS Tut. (2003)
N+ GATE
PWELL
direct
tunneling
electrons
SiON
H
0
+V
G
e
-
H
+
interface traps
bulk traps
Gate Oxide Integrity Controlled Through:
11
TDDB Trends for High-k Dielectrics
High-k Gate Dielectric Summary:
Leakage generally 2-3 decades lower versus
same equivalent oxide thickness
Breakdown strength E
BD
generally
decreases with k. Have to be careful with too
aggressive scaling of hgh-k thickness.
Field/Voltage Acceleration increases with
k and should be favorable for burnin
reduction/elimination.
EOT ()
5 10 15 20 25
J
g

@

(
|
V
f
b
|
+
1
)

(
A
/
c
m
2
)
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
10
3
10
4
nMOSCAP HfSiON
pMOSCAP HfSiON
NMOS SiO
2
Trendline
nMOSCAP HfON
TI: Shanware: IEDM, 939 ( 2003).
High-k Leakage Trends
Reduced
Leakage
12
NBTI Trends
NBTI Effects Controlled Through:
Controlling excessive hydrogen
Understanding full statistical NBTI-
degradation distribution
Determination of critical p-channel
speed paths
Designing with the NBTI-induced
shifts comprehended
Product Margin-Testing/Guard-
Banding
-14
-12
-10
-8
-6
-4
-2
0
0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
Characterization V
DD
(V)

F
O
S
C

(
%
)
Stress1: VDD=2.8V/30mins/105C
Stress2: VDD=2.8V/60mins/105C
TI: V. Reddy et. al., IRPS 2002
TI: A. T. Krishnan, IRPS Tutorials 2005
Poly
H H
SiO
2
Silicon
H
0 H
0
Eox
Interface State Generation
Step 1: Si-H(3eV) + hole Si + H
+
Step 2: H
+
+ e H
0
Step 3: H
0
+ H
0
H
2
(4eV)
13
Channel Hot-Carrier Trends
CHC Effects Controlled Through:
Extensive CHC testing --- complete understanding of voltage,
temperature and time-dependence of transistor parametric-degradation
Determining the full statistical distribution of CHC degradation
Circuit checkers, e.g., determination of critical speed paths
Designing with the CHC-induced parametric shifts fully comprehended
Product Margin-Testing/Guard-Banding
0.01
0.1
1
10
100
1000
0 50 100 150
L (nm)
L
i
f
e
t
i
m
e

(
A
r
b
i
t
r
a
r
y
)
NMOS
PMOS
Channel Hot Carrier (CHC) Injection can degrade transistor parameters
0.6
0.8
1
1.2
1.4
1.6
0 50 100 150
L (nm)
V
D
D

(
V
)
Vdd held ~ constant
Vdd reduced
with scaling
Vdd Trends
CHC Lifetime Trend
14
0
1
2
3
4
5
6
7
8
9
10
0 20 40 60 80
Silicide thickness (nm)
S
h
e
e
t

r
e
s
i
s
t
a
n
c
e

(
o
h
m
/
s
q
)
CoSi2
NiSi
Silicide Trends
Sheet resistance for NiSi lower than CoSi
2
For same sheet resistance, average Si consumed is much less with NiSi
For similar junction depth, lower junction leakage achieved with NiSi
32nm Silicide Challenges :
Maintaining low sheet-resistance plus low junction-leakage a challenge
Shallow junctions versus adequate annealing of implant-induced damage
Raised source/drains required for low-sheet/low-leakage junctions?
0
10
20
30
40
50
60
70
80
0 1 2 3 4 5 6 7 8
Sheet r esistance (ohms/sq)
S
i
l
i
c
o
n

c
o
n
s
u
m
p
t
i
o
n

(
n
m
)
CoSi2
NiSi
Ref: Lauwers et al, JVST-B, p.2026, 2001
1.E-10
1.E-09
1.E-08
1.E-07
140 145 150 155 160 165 170 175
Junction depth (nm)
L
e
a
k
a
g
e

(
A
/
c
m

)
CoSi 2
Ni Si
Ref: Lauwers et al, JVST-B, p.2026, 2001
Silicide : NiSi PtSi Pd
2
Si
Resistivity: 20-30 25-35 25-35
(ohm-cm)
15
Feature
Size
IC Process
Parameter
Impact on ESD
robustness
<1 m Silicide

<0.25 um
Leff

Tox <40 A

65-90 nm

Poor thermal
resistance
Local channel
heating
Oxide stress
Metal current
density
Ch. Self-heating
Every technology advance has significant impact
on ESD design for the IC circuits
32 nm
FinFET
SOI
ESD Trends
ESD Controlled Through:
Special ESD protection circuits are designed and implemented on chip
Understanding and mitigating the impact of processing on ESD circuits
ESD Checkers are used to aid designers
Extensive ESD and Latchup testing of final product
JEDIC standards used for shipping, handling and product use
Common Sources for
ESD Damage to
Semiconductor
Devices:
Human Body
Machines
Charged Devices
16
e
-
Extrusion
e
-
Voids
M
Electromigration-Induced Damage in Metal
TI: E. Ogawa, 2001 IEEE-IRPS Tutorial
Electromigration (EM) Effects Controlled Through:
Interconnect Process-Robustness
Extensive EM Testing
Current Design Rules Based On: Operating Temp, Duty Cycle,
AC vs. DC Operation, Metal Length and Width Considerations
Current Density Checkers and Power-Density (Hot-Spot) Analysis
17
Cu Stress-Induced Via-Voiding
Constrained-Cu grain-growth & excess vacancies.
Interfacial vacancy diffusion & precipitation.
TI: E.Ogawa, et al., : IEEE-IRPS, 312 (2002)
0
0.2
0.4
0.6
0.8
1
0 100 200 300
R
e
l
a
t
i
v
e

C
r
e
e
p

R
a
t
e
Temperature (C)
M-D Equation R > 5%, 168 hrs
190 C
T
0
C T eV Q N where
T k
Q
Exp T T R Model SM
B
N


270 , 74 . 0 , 2 . 3 :
) ( ) ( :
0
0
Creep/Voiding Rate Model
McPherson &
Dunn SM Model
Observed stress-induced Cu via-voiding
described McPherson & Dunn Model
VDP Structure Void Formation Kinetics
0%
10%
20%
30%
40%
50%
60%
70%
80%
168
hrs
336
hrs
500
hrs
168
hrs
336
hrs
500
hrs
168
hrs
336
hrs
500
hrs
168
hrs
336
hrs
500
hrs
R
e
l
a
t
i
v
e

%

o
f

F
a
i
l
i
n
g

S
i
t
e
s

(
4
8

t
o
t
a
l
)
OPEN >100% >50% >20% >10% >5%
100 C 150 C 200 C 250 C
VDP Test Structure
M1
M2
183 nm
V1
TI: McPherson & Dunn, J. Vac. Sci. Tech. B, 1321(1987)
Stress Migration (SM) Effects Controlled Through:
Post Cu-deposition anneals, strong capping layer adhesion, and SM bakes
Redundant vias needed for wide metal leads
Structure/layout dependent via rules for critical vias
18
0 1 2 3 4 5 6 7 8 9 101112
10
-1
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9

T
i
m
e

t
o

F
a
i
l
u
r
e

(
A
r
b
i
t
a
r
y

U
n
i
t
)
E (MV/cm)
OSG(k=2.9)
FSG(k=3.5)
PETEOS(k=4.2)
SiO
2
P-MSQ (k=2.4)
0 1 2 3 4 5 6 7 8 9 101112
10
-1
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9

T
i
m
e

t
o

F
a
i
l
u
r
e

(
A
r
b
i
t
a
r
y

U
n
i
t
)
E (MV/cm)
0 1 2 3 4 5 6 7 8 9 101112
10
-1
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
10
9

T
i
m
e

t
o

F
a
i
l
u
r
e

(
A
r
b
i
t
a
r
y

U
n
i
t
)
E (MV/cm)
OSG(k=2.9)
FSG(k=3.5)
PETEOS(k=4.2)
SiO
2
P-MSQ (k=2.4)
OSG(k=2.9)
FSG(k=3.5)
PETEOS(k=4.2)
SiO
2
P-MSQ (k=2.4)
Lower-k silica-based materials generally have lower Ebd and TDDB
Lower-k materials generally have lower modulus and lower mechanical strength
UV and/or e-beam shown to be effective at increasing strength/hardness
Low-k Interconnect Dielectric Trends

Low-k Dielectric Issues Controlled Through:

Extensive TDDB, adhesion, cohesion, and crack propagation testing
Detailed design rules for minimum-pitch line-lengths
Dual ramp-rate breakdown testing (TI: G. Haase, et al., IRPS, 466 (2005)
Ebd
TDDB
TI: E. Ogawa, et al., IRPS 2003
19
0
10
20
30
40
50
0 1 2 3 4 5 6
Current Densit y [ MA/cm2]
T
e
m
p
e
r
a
t
u
r
e

R
i
s
e


[

C
]
M2, FSG
M3, FSG
M4, FSG
M4, OSG
M3, OSG
M2, OSG
Interconnect Joule Heating Trends
Dielectric Thermal
Material Constant Conductivity
(mW/
o
C-cm)
PE-TEOS 4.2 ~ 12
FSG 3.6 ~ 8
OSG 2.8 ~ 5
Joule heating in metal leads becomes an issue for current
densities > 1MA/cm
2
and is exacerbated by low-k.
20
Defect Detection Trends with Scaling
breakdown field (MV/cm)
3 4 5 6 7 8 9
c
u
m
u
l
a
t
i
v
e

p
r
o
b
a
b
i
l
i
t
y

%
0.1
1
10
30
50
70
90
99
Killing Defects are becoming increasingly difficult to resolve physically
In some cases, the killing defect can be atomic/molecular in size. Must
rely more on electrical versus physical signature.
Electrical breakdown and TDDB measurements of interconnect dielectrics
have become standard interconnect reliability test.
Dual ramp-rate breakdown tests now used to determine true minimum to
metal-to-metal spacing for interconnects hundreds of meters long
0
10
20
30
40
50
60
70
80
90
100
180 130 90 65 45 32
technology nodes (nm)
k
i
l
l
e
r

d
e
f
e
c
t

s
i
z
e

I
n
m
)
Killing interconnect defects:
historically ~ 50% of geometry/space
M1-M1 @250C
3hr
1hr
7hr
Actually, today, killing interconnect
defects can be atomic/molecular in size
Impact of time-
window on ILD
breakdown strength
21
Photolithography Issues with Continued
Scaling ---What you draw is not exactly
what you get
Information is lost
N3
N4
Contact pad area loss
Asymmetric pitch CD control
Constrained gate end loss
Gate CD flaring near pads/turns
22
Lithography fewer tricks remain
Various Strategies/Tricks:
- Attenuated phase shift (130nm)
- Model-Based OPC (130nm)
- Alternating phase shift (90nm)
- Sub-resolution assist feat.( 65nm)
- Restricted design rules (45nm)
- Immersion lithography (45nm)
32nm Challenges for Lithography
Highly restricted design rules and high-index immersion for lithography
Double-exposure at multiple layers
Full 3D-electromagnetic litho simulation for RET/OPC
23
24
Summary: More Design Attention will be required for Reliability Assurance
MOSFET Scaling --- more evolutionary than revolutionary
Transistor I
drive
Increases --- normally come with increases in I
off
Strained Si --- offers improved I
drive
without I
off
increase
SiO
2
Gate Dielectrics (~1.2nm thick) --- very leaky (100-1000A/cm2)
High-k Gate Dielectrics --- reduced leakage (~ 1000x for same EOT)
High-k Films --- lower Ebd but improved field acceleration
NBTI --- impact on V
min
greater due to smaller voltage headroom
CHC --- no longer benefiting from Vdd reduction
Silicides --- low sheet resistance and low junction leakage at odds
ESD --- never seems to get easier
Interconnect RC --- starting to dominate circuit performance
EM and SM --- likely will require some type of Cu-cladding
Joule Heating --- more severe with lower-k
Defect Detection --- must rely more on electrical signature
Litho-Induced Defects --- RET/OPC becoming increasingly important
Reliability Impact of Continued Scaling --- Conclusions