PHASE-LOCKED LOOPS (PLL)

A PLL is an electronic servo loop consisting of a phase detector, a low-pass filter , and a
voltage-controlled oscillator. Its controlled oscillator makes it capable of locking or synchronizing
with an incoming signal. If the phase changes, indicating the incoming freqency is changing, the
phase-detector otpt voltage increases or decreases !st enogh to keep the oscillator freqency
the same as the incoming freqency, preserving the locked condition. "hs, the average voltage
applied to the controlled oscillator is a fnction of the freqency of the incoming signal. In fact,
the low-pass filter voltage is the demodlated otpt when the incoming signal is freqency-
modlated #provided the controlled oscillator has a linear voltage-to-freqency transfer
characteristic$.
PLLs were initially #late%&'(s$ very comple) and very e)pensive, and only sed in a very
few applications. *ver the years, the development of complete single-chip I+ PLLs made possible
the se of PLLs in comple) systems that previosly were impractical or neconomical.
Basics of Phase-Locked Loops
"he PLL provides freqency selective tning and filtering withot the need for coils or
indctors. As shown in the figre below, the PLL in its most basic form is a feedback system
comprised of three basic fnctional blocks, A phase comparator , low-pass filter #an integrator$,
and a voltage-controlled oscillator #-+*$.
"he basic principle of operation of a PLL can briefly be e)plained as follows , .ith no
inpt signal applied to the system, the error voltage -d is eqal to zero. "he -+* operates at a set
freqency f o which is known as the free-rnning freqency. If an inpt signal is applied to the
system, the phase comparator compares the phase and freqency of the inpt signal with the -+*
freqency and generates an error voltage, v.(t), that is related to the phase and freqency difference
between the two signals. "his error voltage is then filtered and applied to the control terminal of
the -+*. If the inpt freqency I. is sfficiently close to fo, the feedback natre of the PLL cases
the -+* to synchronize, or lock, with the incoming signal. *nce in lock, the -+* freqency is
identical to the inpt signal, e)cept for a finite phase difference.
"wo key parameters of a PLL system are its lock and captre ranges. "hey can be defined
as follows ,
Lock Range. /ange of freqencies in the vicinity of fo, over which the PLL can maintain
lock with an inpt signal. It is also known as the tracking or holding range. Lock range increases as
the overall gain of the PLL is increased.
Capture Range. 0and of freqencies in the vicinity of fo where the PLL can establish or
acqire lock with an inpt signal. It is also known as the acqisition range. It is always smaller
than the lock range, and is related to the low-pass filter bandwidth. It decreases as the filter
bandwidth is redced.
"he lock and captre ranges of a PLL can be illstrated with reference to the following
figre, which shows the typical freqency-to-voltage characteristics of a PLL. In the figre, the
inpt is assmed to be swept slowly over a broad freqency range. "he vertical scale corresponds
to the loop-error voltage.
In the pper part of the above figre, the loop freqency is being gradally increased. "he
loop does not respond to the signal ntil it reaches a freqency f1, corresponding to the lower edge
of the captre range. "hen, the loop sddenly locks on the inpt, casing a negative !mp of the
loop-error voltage. 1e)t, Vd varies with freqency with a slope eqal to the reciprocal of the -+*
voltage-to-freqency conversion gain, and goes throgh zero as fs 2 fo. "he loop tracks the inpt
ntil the inpt freqency reaches f2, corresponding to the pper edge of the lock range. "he PLL
then loses lock, and the error voltage drops to zero.
If the inpt freqency is now swept slowly back, the cycle repeats itself as shown in the
lower part of the preceding figre. "he loop recaptres the signal at f3 and traces it down to f4. "he
freqency spread between (f1, f3) and #f2, f4$ corresponds to the total captre and lock ranges of the
system3 that is, f3 - f1 2 captre range and f4 - f2 2 lock range. "he PLL responds only to those inpt
signals sfficiently close to the -+* freqency fo to fall within the lock or captre range of the
system. Its performance characteristics, therefore, offer a high degree of freqency selectivity,
with the selectivity characteristics centered abot fo.
If an incoming freqency is far removed from that of the -+*, so that their difference
e)ceeds the pass band of the low-pass filter, it will simply be ignored by the PLL. "hs, the PLL is
a freqency-selective circit.
(Aove taken fro! "App#$cat$ons of L$near Integrated C$rcu$ts%, & 'ugene R. (natek) *o+n ,$#e& - .ons,
1/01, pp 4/2-4/3) adapted & 4arr& Lunt to !ore !odern app#$cat$ons).
"he following timing diagram of the error voltage as a fnction of the inpt signal is also
helpfl.
f
o
f
s
V
e
V
d
1 2 3 4 5 6
"he operation can be seen from the si) bit periods shown in the above figre. In bit periods
% and 4, the data transition occrs at the rising edge of the -+* clock, fo, so the error voltage
remains at ( and the -+* neither speeds p nor slows down.
In bit period 5, the data transition occrs 067*/6 the rising clock edge, so the error
voltage Ve is positive for the time interval between the data transition and the clock rising edge.
"his error voltage is integrated by the low-pass filter, reslting in a positive change in the -+*
inpt voltage Vd, which in trn will case the -+* freqency fo to increase slightly. "his increase
in the -+* freqency is not shown in the diagram.
In bit periods 8 9 :, the data transition occrs A7"6/ the rising clock edge, so the error
voltage Ve is negative for the time interval between the clock rising edge and the data transition.
"his error voltage is integrated by the low-pass filter, reslting in a negative change in the -+*
inpt voltage Vd, which in trn will case the -+* freqency fo to decrease slightly.
"his continal closed-loop feedback keeps the -+* rnning at very near to an integer
mltiple of the data freqency #in the e)ample above, it rns at 4) the highest data freqency$. Any
variations in the basic freqency of the incoming data are ths tracked by the -+*, and the otpt
of the PLL is a clock which is freqency-locked with the data, allowing accrate definition of the
bit period of the data.