IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 18, NO.

6, NOVEMBER 2003

1405

DC Bus Voltage Control for a

Distributed Power System
Per Karlsson, Member, IEEE, and Jrgen Svensson

AbstractThis paper addresses voltage control of distributed

dc power systems. DC power systems have been discussed as a result of the introduction of renewable, small-scale power generation
units. Also, telecommunication power systems featuring UPS properties might benefit from a broader introduction of dc power systems. Droop control is utilized to distribute the load between the
source converters. In order to make the loading of the source converters equal, in per unit, the voltage control algorithm for each
converter has to be designed to act similar. The dc side capacitor of each converter, needed for filtering, is also determined as
a consequence. The root locus is investigated for varying dc bus
impedance. It is found that the risk of entering converter over-modulation is a stronger limitation than stability, at least for reasonable
dc bus cable parameters. The stationary and dynamic properties
during load variations are also investigated.
Index TermsConverters, impedance, losses, power cables,
power distribution, power semiconductor devices, stability.

I. INTRODUCTION

HIS PAPER addresses droop dc bus voltage control and

its stationary and dynamic behavior. The controller design
also gives a specification of the dc side filter, in this case purely
capacitive.
Several different dc bus voltage control schemes exist [1], of
which two seem commonly used: master-slave and droop control [2]. The master-slave method strongly relies on fast communication between the source and load converters. One of the
converters, referred to as the master, is responsible for controlling the dc bus voltage and distributing power references to the
other source converters. In this paper voltage droop control is
utilized. Droop control does not require any communication between the converters. Instead, the dc bus voltage is measured at
each source converter and all the source converters contribute to
balance the total power consumed by the loads and the losses of
the dc power system. In common voltage droop control, the dc
bus voltage declines linearly as the output current, or in some
cases power, for the converter increases in order to give stable
operation. This, of course, yields a stationary error in the voltage
level.
The paper starts with an overview of the simulation model.
Then the dc bus voltage controller utilized in the analysis is
introduced. The simulation model parameters are given and the
controller parameters are discussed. The root locus dependency
Manuscript received January 31, 2003; revised April 7, 2003. Recommended
by Associate Editor Y.-F. Liu.
The authors are with the Department of Industrial Electrical Engineering
and Automation, Lund University, Lund SE-221 00, Sweden (e-mail:
per.karlsson@iea.lth.se; jorgen.svensson@iea.lth.se).
Digital Object Identifier 10.1109/TPEL.2003.818872

Fig. 1.

Investigated dc power system configuration.

on dc bus impedance is investigated, and it is found that the risk

of entering converter over-modulation is a stronger limitation
than stability, for reasonable dc bus parameters. Last, simulation
results for a five-converter ring bus dc system with realistic cable
data are shown.
To investigate the transient response of the dc bus voltage
controllers, the power references for the power fed to the loads
are changed in steps.
II. SIMULATION MODEL
The investigated dc distribution network consists of five converters where three are operated as sources and two are feeding
power to loads. The converters are connected to galvanically
separated ac power sources or loads. The grids should be galvanically separated to avoid a low impedance path for the zero-sequence currents, discussed in [3]. Fig. 1 shows a five-converter
dc power system configuration, representative for the ones considered in the analysis.
Each converter has a front interface with an inductive connection to the source or load. Therefore, the end interface connected to the dc bus should be capacitive. Consequently, the
front side of the converter is current controlled, and the end side
is voltage controlled. To control the end side voltage, i.e. the dc
bus voltage, each converter intended for voltage control measures the voltage at its converter to bus interface.
Fig. 2 shows one of the converter subsystems of the dc network. From Fig. 2 it is clear that the converters considered are
self-commutated, three-phase full bridges. The dc link capacitor is used to partly decouple the ac and dc systems in such
a way that a disturbance on one side is not reflected on the
other side of the converter. In [2], a similar system is investigated but thyristor-based current source converters (CSCs) are
used instead of transistor equipped voltage source converters

0885-8993/03$17.00 2003 IEEE

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 18, NO. 6, NOVEMBER 2003

Fig. 2. Converter forming the interface between the dc bus and its three-phase
ac network, source or load.

Fig. 3.  -link model for the dc cable. Note that the cable capacitance is
included in the converter dc side capacitors, C and C .

(VSCs). The main advantage gained by using transistor based

VSCs compared to thyristor based CSCs is that the harmonic
content of the ac side current is reduced to a large extent. For
transistor-based VSCs the switching frequency can be selected
arbitrary, which means that the ac line current can be controlled
to be free of low order harmonics. However, a controller of
higher bandwidth and complexity is required. Furthermore, the
losses are higher and the power handling capability lower. The
cost of the converter including transducers and controllers is in
most cases higher.
A. DC Bus Model
Two dc bus models are discussed in this paper. The dc bus
voltage controllers are designed based on the assumption that
the dc bus is purely capacitive. Therefore, a purely capacitive dc
bus with capacitance equal to the total converter dc link capacitance, is analyzed first. Then a more realistic dc bus network
with the cable segments modeled as capacitive and inductive
-links, according to Fig. 3, is analyzed.
In [4], large signal stability in the case of distributed converters supplying constant power loads is investigated. From
-filter specification for the load converter is ob[4] an input
tained based on the maximum output power for the load converters and the total source converter output resistance. An equilibrium point criterion is used to formulate an upper limit for the
output resistance of the source converter, which results in an intuitively understandable criterion stating: The equivalent load
resistance must be higher than the source converter output resistance. Mathematically, this is expressed
(1)
with notations according to Fig. 3. A lower bound for the source
output resistance is also given in [4]. In the case of a single load
converter consuming constant power, the lower bound is given
by

Fig. 4. Control structure for dc bus voltage control. The source converter
current is denoted I and the cable current I
.

The stability problem therefore becomes a problem of selecting

converter dc side capacitors.
B. Controller Structure
The dc bus voltage controller structure is shown in Fig. 4. A
proportional (P) controller is used for the droop scheme, similar
to the PI-controller derived in [5] for back-to-back converter dc
link voltage control. This controller structure should be implemented in all converters, intended for power flow control. The
reason for this is to distribute the total load between as many
converters as possible when droop control is utilized.
Note that several converters are used to support the power
flow, which is not clear from Fig. 4. To simplify the investigation, a simple system with only one source and one load converter is considered. This is then extended to cover the case with
several source and load converters.
To attenuate the interaction between the ac side negative sequence voltage and the dc bus voltage control discussed in [6],
and to enhance controller pole placement the measured dc bus
voltage is low-pass filtered [5], see Fig. 4. The break-over fre.
quency of the low-pass filter is denoted
The dc bus voltage controller for the droop scheme, i.e., when
a P-controller is used, is written

(2)

(3)

Modifications made to the latter expression to include the case

with several constant power load converters are shown in [4].
The derived expressions are based on the assumption that the
is common for all the paralleled converters. In
resistance
a distributed power system this is not likely. The resistance is instead distributed along the cables. Furthermore, the inductance
is also a property of the cables used and not inserted on purpose
for filtering action. Here, only capacitors are inserted as voltage
stabilizers and filters, close to both source and load converters.

In the case of a purely capacitive dc distribution system, i.e.

,
and
, the
when
closed loop transfer function is written
(4)
The effects of nonzero cable impedance are shown in the next
section, where dynamic properties are examined. In the case

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KARLSSON AND SVENSSON: DC BUS VOLTAGE CONTROL

1407

of a purely capacitive dc distribution system, the current at the

, which in the case
receiving end is expressed as
of a single source gives a droop function

cated at the receiver or load converter, yielding

. The equivalent time constant is

(13)
Consequently, the converter dc bus capacitor is selected from
(14)
(5)
The stationary droop impedance or resistance is thus
and the actual and desired characteristic polynomials of
the closed loop transfer function are given by
(6)
which is fulfilled for

Note that for a multi-converter system, all the source converters

should have the same stationary characteristics in order to
achieve proper load sharing. This is fulfilled if the dc side
capacitor of each converter is selected according to the expression above. Furthermore, for an ideal cable, i.e., without any
impedance other than the dc side capacitors, the system transfer
function will be the same as for the two-converter system. For
converters with the following data

(7)
It is clearly seen that a high damping of the closed loop transfer
function poles requires a large dc distribution system capacitance. Here, the poles are chosen to give a performance corresponding to the one of a Butterworth filter, which means that
. This choice requires a
the damping is selected as
rather moderate dc distribution bus capacitance without making
the system oscillatory. The last point is important since the dc
distribution bus is not purely capacitive, which implies that it
is not advisory to make the simplified system oscillatory and
then introduce nonidealities into the system. For the selected
damping, the gain is
(8)
Assume that each converter corresponds to a virtual resistance,
with a base value equal to
(9)
In the case of droop control, the dc current at rated load for
rectifier operation increases due to the decreased output voltage
caused by the droop characteristic
(10)
is the relative converter output voltage drop at rated
where
power. The droop resistance is inversely proportional to the gain,
which yields

it is found that each converter, source and load, should have a

dc side capacitance to rated power ratio given by

Note that the rated power is given for inverter operation at a

. According to [7], the converter
dc link voltage equal to
losses decrease for rectifier operation compared to inverter operation. This implies that the maximum allowable rectifier power
is higher than the maximum inverter power based on the assumption that the converter losses are equal in the two cases.
When this method is used, communication is not required but
the dc bus capacitance needed for each converter is considerably higher than reported in other work on the same topic [6].
Therefore, the converter proposed here is more bulky. However,
the dc link capacitance for each converter is lower than twice
the one a regular three-phase converter is equipped with, i.e.,
for motor drive applications. Furthermore, the magnitude of the
dc bus voltage oscillations observed for an unbalanced ac load
[6] is inversely proportional to the dc bus capacitance [5]. The
oscillation appears at twice the frequency of the unbalanced ac
network [5], [6], which means that introducing a low-pass filter
with a break-over frequency lower than this frequency effectively attenuates the problem.
III. CABLE IMPEDANCE

(11)

In this section the requirements on the cable impedance are

investigated. First a stationary analysis is made giving the maximum cable resistance. Then the influence of the cable inductance is investigated. These investigations are made for a simple
two-converter system with a dc bus model according to Fig. 3.

(12)

A. Stationary Characteristics

This is rewritten to

Now it is assumed that only half of the required dc bus capacitance is located at the source converter. The other half is lo-

For simplicity, assume a network consisting of only one

source and one load and operating at steady state. The latter
assumption implies that the network can be regarded as purely

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1408

Fig. 5.

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 18, NO. 6, NOVEMBER 2003

Simplified Thevenin equivalent for stationary analysis.

resistive and only the stationary droop characteristic has to be

considered, see Fig. 5.
The current supplied to the load of this system is written
(15)
is the receiving end power. This is rewritten to a
where
second order algebraic equation and expressed in a per unit (pu)
system based on the source ratings, see Appendix A

Fig. 6. Per unit pv droop characteristic, including over-modulation and loss

limits. Note that in this figure the power is positive flowing from the ac to the
dc side.

where
is the pu value of the line-to-line receiving end
voltage. Together with (17), this gives the maximum cable
resistance

(16)
The stable solution to this equation is written
(17)
Since the resistors form a voltage-dividing network, the sender
side pu voltage drop is

(23)
The pu line reactance used in [5] is approximately equal to
for the pu base given in Appendix A, which meets
the requirements of the standard IEC 1000-3-2, if
,
and
at a switching
gives
frequency of 4.95 kHz. Assuming

(18)
The risk of entering converter over-modulation due to a too low
dc link voltage is the main reason for investigating the dc bus
voltages at different points in the network. The minimum dc
link voltage is determined from the required load voltage at the
converter output terminals, including the voltage drop across the
ac side filter. The line-to-neutral RMS voltage at the converter
output feeding a three-phase ac load is expressed as

(19)
The maximum RMS line-to-neutral voltage allowable for
avoiding over-modulation at stationary operation is
(20)
for symmetrical voltage references, i.e. when space vector pulse
width modulation (SVPWM) is used. If it is assumed that the
reactive power equals zero, the limiting case for the inverter,
i.e., receiver side, of the dc network is written
(21)
which gives
(22)

(24)
Furthermore, this corresponds to a source voltage given by
(25)
This means that the power supplied from the source equals
(26)
Cable losses approximately equal to 0.2 pu seems very high.
Fig. 6 illustrates the pu droop characteristic, expressed in pu
power scale, for a three-phase converter based on Semikron
SKM300GB123D modules, including over-modulation and loss
limits.
From Fig. 6 the increased power handling capability for rectifier operation at a semiconductor loss level equal to the rated appears to be close to 17%. This is not enough to cover cable losses
of 0.2 pu but on the other hand, a dc network design without margins to avoid over-modulation is not likely. The characteristic
,
,
shown in Fig. 6 is based on
, 50 Hz,
, and operation at unity
power factor for the ac network. The converter losses are calculated according to [8].
B. Stability
An impedance specification for individual loads of dc distribution systems, based on the small signal stability criterion,
is presented in [9]. Here, stability is studied for varying cable
parameters by investigation of the root locus. Therefore, the cables are from now on modeled as resistive and inductive, with

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KARLSSON AND SVENSSON: DC BUS VOLTAGE CONTROL

1409

the cable capacitance neglected or included in the converter dc

side capacitors (Fig. 3). The cable impedance is thus
(27)
The equivalent impedance of the receiving end is modeled
(28)
The impedance seen from the source converter is written
(29)
The cable resistance and receiving end equivalent resistance is
expressed based on their pu values according to
(30)
The corresponding time constants are

where

(31)
denotes pu time constant. The impedance is written

Fig. 7. DC bus voltage (top) and ac side output power (bottom) for the sending
(black) and receiving (grey) end converters at an output power step from zero
to rated power.

at rated output power. Therefore, the receiving end pu resistance

and also its time constant are given by
(32)
The source converter output voltage is divided between the cable
impedance and the equivalent impedance of the receiving end
converter, which gives

(40)
The pu time constant of the considered case is given by

(33)
Assuming complex poles, the characteristic polynomial is
(41)

(34)
The cable resistance and inductance are thus

The characteristic frequency and damping are identified

(35)
The characteristic frequency is expressed in pu
(36)
which gives the pu time constant for the cable
(37)
Since the dc bus voltage measured at the sending end converter
,
terminals is low-pass filtered with a break-over frequency
it is desirable that
(38)
The main purpose of (33)(38) is to provide a numerical base for
the further investigation where the limiting case with
is assumed. This gives the receiving end voltage
(39)

for a 750 V, 100 kW system. The simulation result for this case
is shown in Fig. 7. The cable data investigated are
and
, i.e.
. All timesimulations are made in DYMOLA with switch-mode converter
models utilizing vector current controllers according to [5] and
voltage droop controllers according to (3). The voltage droop
controller gain (8) for each source converter is calculated based
, since a load converter of the same rated power
on
. The ac side current reference for each one
will have
of the source converters is calculated from the droop current
reference based on the assumption that the converter is loss-less.
The measured dc bus voltage is low-pass filtered according to
Fig. 4.
In Fig. 7 it is seen that the stationary voltage is somewhat
lower than expected (a few Volts). This is due to the fact that
rated power is transmitted to the three-phase grid, i.e. the losses
in the line side filter have to be added to the power supplied to
the dc side of the converter. This also implies that the equivalent
, is lower than expected from the previous
load resistance,
calculations.

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 18, NO. 6, NOVEMBER 2003

(a)
Fig. 8.

Pole-zero map for the case investigated earlier, i.e., with cable data
r
= 0:06 pu and l
= 0:0024 pu which gives 
= 0:04 pu.
The small markings denote no load (p = 0) and the large markings denote
receiver output power equal to rated sender power (p = 1:0).

Now, the system is examined by means of pole-zero plots.

according to Fig. 4 is investiThe transfer function
gated in MATLAB, for different cable parameters and receiving
end loading. MATLAB is used due to the fact that when the
cable parameters are included the transfer function becomes
much more complicated than (4). The characteristic polynomial
for this two-converter system is of the fourth order and analytical expressions for the poles are not possible to derive. Note that
(33) is not used for stability investigations, since it does not take
the source converter output impedance, including , into account. Instead, (17) is used to calculate the receiving end voltage
for the actual loading. An equivalent load resistance is calculated from and . From this the transfer function
appearing in Fig. 4 is calculated according to (42). The total
impedance seen from the converter is calculated as the source
in parallel with
,
converter dc side capacitance
which also forms the transfer function from to , see Fig. 4.
The converter in Fig. 4 is considered to have a transfer funcfor the frequencies of interest and the extion
is set to zero. Fig. 8 shows the
ternal power reference
pole-zero plot for the system simulated in Fig. 7, both at no-load
(small markings) and at rated load (large markings). It is obvious
from Fig. 8 that the actual loading of the system is of minor importance for stability.
To investigate the robustness against parameter uncertainty,
is varied from 0.01 pu to 0.12 pu and the pu cable time
constant is varied from 0.02 to 0.4 pu. The root-locus is investigated for a case where the receiving end power is approximately
is
equal to rated power of the sending side converter, i.e.,
equal to one. This is not a strong limitation since it has been
found that the load level affects the pole-zero map to a barely
noticeable extent (Fig. 8). Fig. 9 shows the resulting root locus
for the poles and (Fig. 8). The two other poles, i.e. and
, are complex conjugate pairs of the poles shown in Fig. 9, and
therefore not illustrated. From Fig. 9 it is seen that a low cable
resistance results in a moderately damped system, which is also
expected. This is further seen from the overshoot appearing in
the dc bus voltage response resulting from a load power step at
low cable resistance and time constant, see Fig. 10. The overshoot is a consequence of the selected closed loop damping
. The overshoot is due to the
pole pair.
For a long time constant of the cable, the situation is worse,
which is shown in Fig. 11. In Fig. 11, an oscillation is super-

(b)
Fig. 9. Root locus for poles (a)  and (b)  at p = 1:0. The traces are from
top to bottom: r
= 0:01, 0.06 and 0.12 pu. The dotted lines show constant

= 0:02, 0.04, 0.05, 0.1, 0.2 and 0.4 pu from left to right. Note that the
pole  is real valued for low l
when r
= 0:12.

Fig. 10. DC bus voltage (top) and ac side output power (bottom) for the
sending (black) and receiving (grey) end converters at an output power step
= 0:01 pu, l
= 0:0002 pu and
from zero to rated power when r
thus 
= 0:02.

imposed on the voltage overshoot. The oscillation frequency is

close to 40 Hz, which corresponds to the location of (and ),
, the system is
see Fig. 9. On the other hand, when
well damped but the receiving end converter operates at the limit
of over-modulation for rated output power. Also the cable losses
are high, around 20%, as discussed earlier and therefore, such a
high cable resistance is not recommended. It is not realistic either. The system exhibits sufficient damping for
which is recommended for design.

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KARLSSON AND SVENSSON: DC BUS VOLTAGE CONTROL

Fig. 11. DC bus voltage (top) and ac side output power (bottom) for the
sending (black) and receiving (grey) end converters at an output power step
= 0:01 pu, l
= 0:004 pu and,
from zero to rated power when r
thus, 
= 0 :4 .
TABLE I
SIMULATION MODEL DATA

1411

Fig. 12. DC bus voltage (top) and ac side output power (bottom) for an
output power increase equal to 0.5 pu of rated load converter power at 100 ms
for converter 2 and 200 ms for converter 4 starting from 0 pu in both cases.
Quantities belonging to converter subsystem 1 are solid black, 2 are solid grey,
3 are dashed black, 4 are dashed grey, and 5 are dash-dotted black.

From the initial no load operating point, the output power of

converter 2 increases by 50% of rated power at
and the output power of converter 4 increases by 50% of rated
, see Fig. 12. In Fig. 12 it is shown that the
power at
load sharing works properly both in stationary and dynamical
conditions.
V. CONCLUSION

IV. LOAD SHARING

Load sharing is investigated by means of simulations. A ring
bus network configuration [2] is studied. The network and converter parameters are given in Table I.
Converter no. 1, 3, and 5 in Table I act as sources and converter no. 2 and 4 feed power to loads. Cable segment 1 is connected between converters 1 and 2 etc, and since this is a ring
bus, cable segment 5 is connected between converters 5 and 1
(Fig. 1). To calculate an appropriate cable resistance, it is assumed that the cable length of each segment is 100 m and that
, even if the ring bus
the maximum current density is 4
is broken. The cable inductance is calculated assuming a distance between the centers of the conductors equal to twice the
conductor diameter. Fig. 12 shows the dc bus voltage at the converter terminals and the power delivered from each converter to
its ac side.

A method to select the dc bus capacitance for each converter

of a dc distributed power system is presented. The maximum
cable resistance is specified upon the over-modulation limit.
Furthermore, stability is investigated with aid of the root-locus
for varying dc bus cable parameters. The droop control method
investigated with the converter parameters found in the analysis is simulated both in a two-converter application and in a
five-converter ring bus. From the simple two-converter analysis
it is found that for realistic cable data, the system can be modeled
in a steady state manner, i.e., without taking the cable inductance
into consideration. Therefore, system specification and investigation can be made using a resistive cable model in a load-flow
program. A five-converter dc ring bus is simulated with realistic
cable parameters, where it is found that proper load sharing is
obtained.
APPENDIX
PER UNIT SYSTEM

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(A1)
(A2)
(A3)

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 18, NO. 6, NOVEMBER 2003

(A4)
(A5)
(A6)
(A7)

[6] G. S. Thandi, R. Zhang, K. Xing, F. C. Lee, and D. Boroyevich, Modeling, control and stability analysis of a PEBB based dc DPS, IEEE
Trans. Power Delivery, vol. 14, pp. 497505, Apr. 1999.
[7] F. Blaabjerg, U. Jaeger, S. Munk-Nielsen, and J. K. Pedersen, Power
losses in PWM-VSI inverter using NPT or PT IGBT devices, in Proc.
IEEE-PESC Conf. (PESC94), vol. 1, Taipei, Taiwan, June 2024, 1994,
pp. 434441.
[8] Semikron Application ManualPower Modules, Apr. 2000.
[9] X. Feng, Z. Ye, K. Xing, F. C. Lee, and D. Borojevic, Individual load
impedance specification for a stable dc distributed power system, in
Proc. IEEE-APEC Conf. (APEC99), vol. 2, Dallas, TX, Mar. 1418,
1999, pp. 923929.

ACKNOWLEDGMENT
The authors wish to thank Dr. S. Lindahl, Department of Industrial Electrical Engineering and Automation, Lund University, Sweden, for his contributions, kind support, and sharing of
ideas and thoughts on the problems addressed in this work.
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[1] S. Luo, Z. Ye, R.-L. Lin, and F. C. Lee, A classification and evaluation
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901908.
[2] W. Tang and R. H. Lasseter, An LVDC industrial power distribution
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[3] K. Xing, F. C. Lee, J. S. Lai, G. Thandi, and D. Borojevic, Adjustable
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[4] M. Belkhayat, R. Cooley, and A. Witulski, Large signal stability criteria
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[5] M. Bojrup, Advanced control of active filters in a battery charger application, Licentiates thesis, Dept. Ind. Elect. Eng. Automat., Lund Inst.
Technol., Lund, Sweden, Nov. 1999.

Per Karlsson (M02) was born in Helsingborg,

Sweden, in 1970. He received the M.Sc.E.E and
Ph.D. degrees from Lund University, Lund, Sweden,
in 1995 and 2002, respectively.
He is currently a Research Associate at the Department of Industrial Electrical Engineering and Automation (IEA) where his research interests are in the
field of power electronics, especially in power system
applications. His previous research includes resonant
converter technology, voltage control, and fault detection and clearance in dc distributed power systems.

Jrgen Svensson was born in Malm, Sweden, in

1965. He received the M.Sc. degree in electrical engineering from the Lund Institute of Technology, Lund,
Sweden, in 1992 where he is currently pursuing the
Ph.D. degree in the Department of Industrial Electrical Engineering and Automation.
He is also with Sydkraft AB, Malm, Sweden,
where he works in the area of wind power. His
research interests are in the field of renewable
distributed power systems.

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