Pramod Kumar Meher, New Approach to Look-Up-Table Design and Memory-Based Realization of

FIR Digital Filter, Circuits and Systems, IEEE, vol. 57, NO. 3, March 2010, pp.592-603.

INTRODUCTION
Distributed arithmetic (DA)-based computation is used in this paper for efficient memory-
based implementation of finite impulse response (FIR) filter where the filter outputs are computed
as inner-product of input-sample vectors and filter-coefficient vector. The look-up-table (LUT)-
multiplier-based approach could be an area-efficient alternative to DA-based design of FIR filter.
In this paper conventional LUT-multiplier-based and DA-based structures were designed using
operand and inner-product decompositions, for FIR filter of equivalent throughput, where the
LUT-multiplier-based design involves nearly the same memory and the same number of adders,
and less number of input register. Memory size reduced to half by using two new approaches in
LUT-based-multiplication. The synthesized result shows that LUT-multiplier-based design results
15% less area than DA-based design at same throughput and lower latency.
KEYWORDS:
Digital signal processing (DSP) chip, distributed arithmetic, FIR filter, LUT-based
computing, memory-based computing, VLSI.
SUMMARY:
Odd-multiple-storage scheme approach suggested to reduce LUT size for LUT-based-
multiplication. By this scheme, for address-length 4, the LUT size is reduced to half by using a
two-stage logarithmic barrel-shifter and (W+4) number of NOR gates, where is the word-length of
the fixed multiplying coefficients. Three memory-based structures having unit throughput rate are
designed further for the implementation of FIR filter. One of the structures is based on DA
principle, and the other two are based on LUT-based multiplier using the conventional and the
proposed LUT designs. All the structures are found to have the same or nearly the same cycle
periods, which depend on the implementation of adders, the word-length and the filter order. The
LUT-multiplier-based filter involves times less number of decoders than the DA-based design. The
proposed LUT-multiplier-based design involves half the memory than the DA-based and
conventional LUT-based designs. The LUT-multiplier-based design of FIR filter therefore could
be more efficient than the DA-based approach in terms of area-complexity for a given throughput
and lower latency of implementation. The LUT-multipliers could be used for memory-based
implementation of cyclic and linear convolutions, sinusoidal transforms, and inner-product
computation.
TECHNIQUE USED:
Here Odd-multiple-storage technique is used to reduce the memory size of LUT to half the
memory than the Conventional LUT-based design and DA-based design.
LIMITATIONS :
While compared to DA-based design, LUT-Multiplier-based design results in higher adder-
widths