A monolithic peak current-mode buck converter with fast response

for high speed DVS application

Miao Yang, Weifeng Sun
n
, Shen Xu, Changbing Qin, Shengli Lu
National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China
a r t i c l e i n f o
Article history:
Received 4 June 2012
Received in revised form
4 December 2012
Accepted 10 December 2012
Available online 2 January 2013
Keywords:
Fast transient response
Fast tracking
Soft-start-up
Current sensing
Current mode
DCDC converter
a b s t r a c t
A monolithic peak current-mode step-down DCDC converter with fast response for DVS application is
presented in this paper. A novel fast on-chip soft-start circuit is used to reduce the overshoot voltage and
inrush current. The loop without large capacitor compensation is adopted to increase the slew rate of the
error amplier, which can dramatically decrease the transient response time of the system. Meanwhile,
automatic pulse width modulation (PWM) and pulse skip modulation (PSM) switching are used to improve
conversion efciency during the wide load range. The DCDC converter has been fabricated with a standard
0.13 mm CMOS process. Experimental results show that the start-up time is less than 50 ms without the
inrush current and overshoot voltage. The recovery time is less than 8 ms while the load current suddenly
changes 300 mA. This converter can operate at 1.5 MHz with output voltage from 0.725 V to 1.5 V for DVS
application. The up-tracking speed is about 31.25 ms/V and down-tracking speed is about 21.75 ms/V.
Measured power efciency is 84.293.8% for 1400 mA load current.
& 2012 Elsevier Ltd. All rights reserved.
1. Introduction
In recent years, the high speed Dynamic voltage scheduling
(DVS) method has been widely applied in portable electronic
systems, such as the power supply of SoC or power amplier, to
increase the efciency of the system [1,2]. One of the critical
modules to achieve DVS is the adaptive DCDC converter, which
should contain the characteristics of the fast load transient response,
the fast tracking speed and the fast start-up speed [35].
Many researchers have proposed different methods to improve
the fast response characteristic of the DCDC converter, especially
the load transient response and reference tracking speed. Bang-
bang-controlled is adopted to reach the fast load transient response
due to a wide bandwidth of the converter loop [6]. However, the
switching frequency is variable, and output voltage ripple is high.
A linearnon-linear control is proposed [7,8], but the transition
between linear and nonlinear is not smooth, which makes it difcult
to settle down after the large load transient. It will get worse when it
delivers power to a high dynamic processor. Therefore some
researchers adopted on-chip re-congurable Miller capacitor to
improve the transient response performance with variable slew rate
[9,10]. However, the compensation capacitor still limits the raise of
the slew rate. The concept of reference tracking speed has been put
forward only a few years ago. The maximum current charge method
is used in the up-tracking to increase the tracking speed [4]. But the
overshoot voltage will be introduced. Besides, for down-tracking,
only the load path discharges the charge of output capacitor.
Unfortunately, few people focus on decreasing the start-up time.
The conventional soft-start-up circuits need an external capacitor or
a large resistance on chip to regulate the soft-start-up time and the
piecewise limited current to eliminate the inrush current [4,11,12].
Then the overshoot and inrush current can be suppressed. But the
time is very long. It needs millisecond timescale generally.
In this paper, the converter loop without the large compensa-
tion capacitor is proposed to enhance the transience response.
The recovery time is decreased dramatically. The up counter and
down counter are adopted to make the reference voltage rise or
fall slowly. And the converter is forced to work in PWM mode
when the output voltage changes. The tracking speed can be
increased without overshoot voltage. A fast novel circuit with
simple D/A (digital-to-analog) converter and variable minimum
duty cycle is proposed to apply variable output voltage without
overshoot voltage and inrush current. In addition, the PWM/PSM
dual mode with DPSS (dynamic partial shutdown strategy) is used
to obtain high conversion efciency in a wide load range. The
structure of the proposed converter and circuits implementation
are introduced in Section 2. Measurement results are shown in
Section 3 and the conclusion is made in Section 4.
2. Circuit descriptions
Fig. 1 shows the proposed block diagram of the developed
chip. The peak current mode control is adopted in this converter.
Contents lists available at SciVerse ScienceDirect
journal homepage: www.elsevier.com/locate/mejo
Microelectronics Journal
0026-2692/$ - see front matter & 2012 Elsevier Ltd. All rights reserved.
http://dx.doi.org/10.1016/j.mejo.2012.12.004
n
Corresponding author. Tel.: 86 25 83795811; fax: 86 25 83795077.
E-mail address: swffrog@seu.edu.cn (W. Sun).
Microelectronics Journal 44 (2013) 128136
It contains a power stage, control circuit, voltage setting circuits
and soft-start-up circuits. Voltage setting circuits, including the
resistance network and the OPA (operational amplier), generate
the expected setting voltage V
SET
for the input of the error
amplier in control circuits. The control circuits contain the EA
(error amplier), PWM modulator, current sensor, slope compen-
sation, PWM/PSM digital circuits, buffer and some comparators
that are shown in Fig. 1. It supplies appropriate duty cycle for the
different output voltages V
out
. The soft-start-up circuits are
adopted to suppress the overshoot voltage and inrush current at
the start-up phase of the converter.
At moderate to heavy loads, the converter operates in PWM
mode in order to increase the conversion efciency in general.
The SR latch is included in the digital control circuits as shown in
Fig. 1. The clock pulse at the input of the SR latch initiates the
switching period. The off signal of the PMOSFET M
p
is supplied by
the output of the modulator. If the inductor current is larger than
the limited current, the limited current comparator will ip to
turn off the M
p
too.
With decreasing load current, the converter automatically
switches into PSM mode. The inductor current zero crossing point
acts as the condition of PWM mode switch to PSM mode at the
decreased phase of inductor. In order to increase the conversion
efciency, the low side NMOSFET M
N
will be turned off when the
inductor ramps zero. Once the current crosses zero, the PWM
control loop will be cut off. The DPSS method is used in the
structure [4]. Many modules are disabled such as the PWM
modulator, current sensor, and error amplier. The output voltage
V
out
decreases slowly, depending on the discharge speed of the
output capacitance C as shown in Fig. 1. When the voltage is less
than V
SET
, a constant value, the output of the voltage comparator
will switch at once. Then the system starts the PWM loop again,
which will be forced to work ten cycles. So the inductor current
zero crossing point will be sensed again. If the inductor current
can not decrease to zero, the system will switch to the PWM
mode. Otherwise, the system works in PSM mode.
In addition, the implementation of dynamic output voltage
change depends on the data register by I
2
C interface in the voltage
setting circuit. For example, when we want the output voltage to
change from 0.725 V to 1.5 V, the data register should be changed
from 5b00000 to 5b11111. If the data suddenly change, over-
shoot voltage would be generated. Therefore the up counter or
down counter are used in the converter, respectively, in order to
make R
NET
increase or decrease slowly. From Fig. 1, the equation
of the V
SET
can be obtained as follows:
V
SET
1
R
NET
R
F

V
REF
1
Then V
SET
will rise or fall slowly. So the output voltage V
out
can be
changed smoothly. The frequency of counter decides the tracking
speed of V
SET
. The converter is forced to work in PWM mode when
the V
SET
changes. Therefore, the up/down tracking speed can
increase without overshoot and undershoot. The design of the
counting frequency can refer to the design method of the frequency
of the D/A in the soft-start-up circuits, which will be discussed in
the following.
2.1. On chip fast soft-start-up circuits
The proposed soft-start-up circuits contain two sections: over-
shoot suppression circuit (Fig. 2) and inrush current suppression
circuit (Fig. 3). In Fig. 2, the transistors M
2
, M
3
, OPA and resistance
network are used to set a variable reference voltage V
SET
as
mentioned above. The gate voltage of transistor M
1
is supplied
by the output of 6-bit D/A converters slowly. However, the gate
voltage of the transistor M
2
has been xed at V
REF
, which is larger
than the gate voltage of M
1
. So at the initial phase of start-up, M
2
is cut off for the reason that the drain current of M
1
M
3
always
meet
I
M
1
I
M
2
I
M
3
2
Because of the virtual short characteristics of operational ampli-
er, the gate voltage of the transistor M3 will increase by the gate
voltage of the transistor M1 rising. I
M1
will decrease and I
M2
will
increase. When the gate voltage of the transistor M1 rises to a
certain value, the transistor will be cut off. At this time, I
M2
I
M3
.
Fig. 1. Structure of proposed buck converter.
M. Yang et al. / Microelectronics Journal 44 (2013) 128136 129
The soft-start-up of the setting voltage is completed successfully.
Therefore the Vout will rise following the setting voltage VSET
and avoid the overshoot voltage. This method can be applied to
set different voltage values. The clock frequency CLKRAMP of the
D/A converter decides the start-up time. If the ideal fastest
condition is considered, the system will work using maximum
duty cycle up to a limited current I
limited
and then work using
I
limited
until output voltage becomes stable. Therefore the fastest
time is
t
rise
I
limited
L =V
in
R
load
C ln
V
out
R
load
C

I
lim ited
C

ln
I
limited
C

3
In the proposed circuit, the rise time of V
SET
is designed slightly
longer than t
rise
to get better and faster V
out
start-up wave without
overshoot voltage.
In order to prevent the power MOSFET from being excessively
on and avoid ip error of PWM modulator or limited current
comparator by the switch noise disturbance, the minimum duty
cycle is used in DCDC converter. The minimum duty cycle is
made as big as possible on the premise of the input and output
voltage range. At the time of start-up, though the limited current
comparator is adopted, it is invalid at the time of minimum power
of MOSFET. Therefore the system will still generate inrush
current. The charge slope of the inductor is K
up_slope
(V
in

V
out
)/L, and the discharge slope is K
down_slope
V
out
/L. It is obvious
that charge slope is much larger than discharge slope at the
incipient stage of V
out
rising. The inductor current will exceed the
limited current value after several cycles. Fig. 4(a) is the simu-
lated result when the constant minimum duty cycle is adopted. It
is obvious that the inrush current still exists.
In the proposed converter, the variable minimum duty cycle is
adopted, which means that several clock cycles will be shielded at
the beginning of start-up. When the system meets some condi-
tions, it will change the minimum duty cycle. The dividing point is
decided by V
REF1
in Fig. 3, as follows:
V
in
V
REF1
D
min
T
s
=L V
REF1
1D
min
T
s
=L 4
where D
min
is the minimum duty cycle of the steady stage. When
V
out
is less than V
REF1
, the system uses smaller duty cycle and
slower clock CLK
START
. After several clocks, the charge energy and
discharge energy of the inductor will be equal at one cycle. Then
the clock CLK
NORMAL
is adopted in the system. The simulation
D
CLK
EN
Q_
Q
D
CLK
EN
Q_
Q
D
CLK
EN
Q_
Q
D
CLK
EN
Q_
Q
D
CLK
EN
Q_
Q
D
CLK
EN
Q_
Q
D
CLK
EN
Q_
Q
_
D/A
Q
6
Q
5
Q
4
Q
3
Q
2
Q
1
Q
0
Q
0
Q
2
Q
3
Q
4
Q
5
Q
6
Q
1
V
REF
OPA
Resistance
Network
R
F
R
NET
V
SET
CLK1
EN
R
1
R
2
M
1
M
2
M
3
D
CLK
EN
Q
Q
Fig. 2. Overshoot suppression circuit.
Vmodulator_out
Mux2-1
V
REF1
Vout
Comparator
Buffer
CKP
CKN
CLK
NORMAL
CLK
STRAT
Vlimited_out
CLK
NORMAL
CLK
STRAT
Fig. 3. Inrush current suppression circuit.
M. Yang et al. / Microelectronics Journal 44 (2013) 128136 130
results are shown in Fig. 4(b). The inrush current can be avoided
due to this design method.
2.2. Error amplier and PWM modulator
In order to design the peak current mode buck converter, the
loop design consideration is reported [13]. When the outer
voltage loop is open and inner current loop is closed, the loop
transfer function A
c
from the control voltage V
c
(s) to the output
voltage V
out
(s) is
A
c

R
load
R
S
1
1
R
load
Ts
L
m
c
D
0
0:5

1sCr
c
1
s
wp
1
1
s
wnQ

s
2
wn
2
5
where, D

1D, m
c
1S
e
/S
n
, w
p
1=CR
load
T
s
=LC m
c
D
0
0:5

,
Q1/p(m
c
D
0
0.5), w
n
p/T
s
, and D, S
e
, S
n
, R
load
, T
s
, R
S
stand for
the duty cycle, the slope of the compensation ramp signal, the rise
slope of inductor current, load resistance, switch frequency and
current sampling resistance, respectively. When the outer voltage
loop and inner current loop are all closed, the loop transfer
function
T
loop
T
c
A
c
6
where T
c
is the transfer function of the EA. In conventional design,
the zero in T
c
is in order to compensate the pole w
p
in A
c
. A pole
must be generated by T
C
as the main pole in the loop. However
this design not only introduces large RC compensation, but also
limits the slew rate of the EA. Therefore the response speed is
limited at this condition.
Based on the above analysis, a loop without the large capacitor
compensation design method is proposed. In the EA, the RC
compensation is not considered. Bode plots comparison between
conventional design and proposed design is shown in Fig. 5. The
proposed loop has the same bandwidth as that of the conven-
tional loop with large capacitor compensation. The only differ-
ence with the conventional loop is the loop gain at a low
frequency. The proposed loop adopts lower loop DC gain to keep
the system stable as shown in Fig. 5. The DC gain of loop is
decreased. So the load regulation performance will be sacriced
slightly. However, the DC offset of the output voltage is very
clearly not due to the small load current. It is obvious that 3 dB
of loop has increased by this method. So the response of loop is
improved. The frequency response simulation results of the
proposed loop are shown in Fig. 6. The loop width is about
360 kHz and the phase margin is about 421. The system can be
kept stable under different load conditions.
The circuits of EA and PWM modulator are shown in Fig. 7. The
differential-input and differential-output scheme is adopted in
the EA design in order to make the common output not affected
by the variable common input. In addition, the switching noise
coupled from output node can be ltered out easily. Thus, a nearly
noiseless error signal is derived through this structure [14]. The
EA is composed of transistors M
1
M
10
and resistances R
1
R
4
.The
DC gain of the EA is expressed as
T
c
g
m1
g
m5
R
1
R
3
7
The PWM modulator is composed of transistors M
12
M
18
,
resistances R
5
R
6
and a comparator. The current sensing signal
and slope compensating signal are necessary in the peak current
mode converter. The high accuracy current sensor will be ana-
lyzed in detail in the next section. In the proposed EA and
modulator circuits, simple circuits are used to achieve the
composition of signals and the generation of constant common
output of the error amplier as shown in Fig. 7. It can be obtained
that
V
n
V
eao
V
gs17
I
12
I
13
R
5
8
V
p
V
eao
V
gs18
I
14
R
6
9
And the aspect ratios of M
11
to M
14
, M
12
to M
15
, M
13
to M
16
,
and M
17
to M
18
are equal. M
17
and M
18
work in the saturation
region. So V
gs17
will be equal to V
gs18
. If V
p
V
n
is assumed, then
V
eao
V
eao
I
14
R
6
I
12
I
13
R
5
10
Therefore the value of I
14
R
6
is equal to the common output of the
EA and would not be changed by the variable common input of
the error amplier. Fig. 8 shows the simulation contrast results
between the proposed loop and conventional loop. It is obvious
that the proposed loop has faster transient response. The recovery
.5
1.5
I
L
(
A
)
V
o
u
t
(
V
)
0
0
.5
1
1.5
2.5
-.25
.25
.75
1.25
.5
1.0
1.25
3.5
C
L
K
(
V
)
V
S
E
T
(
V
)
I
L
(
A
)
V
o
u
t
(
V
)
C
L
K
(
V
)
V
S
E
T
(
V
)
I
limited
I
limited
0
1
2
3
4
0
.5
1
-.5
0
.5
1
1.5
-.25
.25
.75
1.25
00
Time(s)
110 220 330 440 50
00
Time(s)
110 2 20 3 30 440 50
Fig. 4. Simulated results of start-up V
SET
, V
out
I
L
and CLK for (a) constant minimum duty cycle and (b) variable minimum duty cycle.
Conventionalloop
Proposedloop
Loopgain(dB)
w (Hz)
wc
0
Fig. 5. Bode plots comparison between conventional loop and proposed loop.
M. Yang et al. / Microelectronics Journal 44 (2013) 128136 131
time for a 300 mA step load transient is only 2 ms and the output
voltage drop is about 5 mV.
2.3. Current sensor
There are mainly two derivational structures in emergent
papers based on an American patent [15]: one uses operational
amplier to clamp the voltage of the drain of sensing MOSFET and
power MOSFET [16,17]; the other employs current mirror to make
the voltage equal to them [18,19]. Both of these schematics
neglect the effect of the clamping current, which can introduce
a term in the current sensing expression and result in inaccurate
sensing current especially at large sensing ratio with small
h
a
s
e
(
d
e
g
r
e
e
)
(360kHz,0dB)
(360kHz,-138)
P
h
a
s
e
(
d
e
g
r
e
e
)
M
a
g
n
i
t
u
d
e
(
d
B
)
Frequency(Hz)
Fig. 6. Frequency response simulation results of the proposed loop (V
in
3.3 V, V
out
1.2 V).
Fig. 7. Error amplier and PMW modulator circuits.
Time(s)
75 100 125 150 175
1.1
8
1.2
2
0
400
V
o
u
t
(
V
)
I
l
o
a
d
(
m
A
)
100mA
400mA
2s
12mV
9.6s
5mV
9.5s
12mV
5mV
V
out1
V
out2
2s
Fig. 8. Load transient response comparison between V
out1
(conventional loop) and
V
out2
(proposed loop) with load current step between 100 mA and 400 mA.
CKP
CKP
CKP CKP CKP
CKN
M
P
M
1
M
N
M
2
M
3
M
4
M
5
M
6
M
7
M
8
M
9
M
S
M
10
M
11
M
18
I1
C
r
c
L
R
SEN
V
in
V
A
V
B
V
C
I
clamp
M
12
M
13 M
14
M
B1
M
SW
M
15
M
16
M
17
I
CS
R
load
Fig. 9. Proposed current sensing circuit.
M. Yang et al. / Microelectronics Journal 44 (2013) 128136 132
current sensing. In this converter, the appropriate aspect ratio of
the transistor M
SW
and several series MOSFET are used to solve
the problem of clamping current error to achieve high accuracy in
a wide load range, which can be seen in Fig. 9. The principle of
operation will be described in detail as follows.
When the clock signal CKP is low, the transistor M
S
is on. The
MOSFET M
S
is composed of the three cascade transistors M
10

M
12
. The series association of three transistors has a trans-
conductance-to-output conductance ratio as high as that of a
long-channel transistor but a shorter physical channel length.
Hence, the composite transistors have a cutoff frequency higher
than the cutoff frequency of its Dc equivalent long-channel
transistor [20]. The other advantage is that the equivalent gate
length of M
S
and the switch M
SW
get triple length of signal
transistor. The match of the two transistors will become better, so
the sensing current will be better. If the relationship of the aspect
ratio of M
S
to M
P
is designed as 1:K, K is designed as 16,000 to
decrease the work current of the current sensor, in order to make
the sensing current proportionally copy the inductor current
precisely. The relationship between the actual sensing current
and the drain of M
P
should be as follows:
K
I
P
I
CS

1
2
m
P
C
ox
WM
P
LM
P
2V
SG_MP
9V
TP
9V
SD_MP
V
2
SD_MP

1
2
m
P
C
ox
WMS
LMS
2 V
SG_MP
9V
TP
9

V
SD_MS
V
2
SD_MS

I
clamp

W
MP
=L
MP
W
MS
=L
MS
11
If the highest order terms of Eq. (11) are neglected, the necessary
and sufcient condition of Eq. (11) is
2 V
SG_MP
9V
TP
9

V
SD_MP
2 V
SG_M
S
9V
TP
9

V
SD_M
S

I
clamp
1
2
m
p
Cox
W
M
S
L
M
S
1 12
The transistors M
13
, M
14
, M
16
, and M
17
and compose a common-
gate amplier to make the potential of V
A
equal to the potential of
V
B
. Besides, M
15
M
17
have equivalent aspect ratios. Therefore, the
drain currents of M
15
and M
16
are equal to the clamping current
I
clamp
. Then Eq. (12) becomes
2I
clamp
m
p
C
ox
V
SG_M
SW
9V
TP
9

WM
SW
LM
SW

I
clamp
m
p
C
ox
V
SG_M
S
9V
TP
9

WM
S
LM
S
13
The source of the switch M
SW
is connected to the drain of M
P
,
not the power V
in
. The sourcegate voltage of the switch M
SW
is
less than the sourcegate voltage of M
S
. When the aspect ratio of
the switch M
SW
is adopted to be slightly larger than and close to
two times the aspect ratio of M
S
, the clamping current error can
be eliminated. Simulated results of I
L
, I
CS
at different currents
are shown in Fig. 10. The current sensing has enough band-
width to make I
CS
wave follow I
L
well. This sensing circuit has a
wide current sensing range with high accuracy as shown in
Fig. 11. The minimum accuracy and the maximal accuracy are
Time(s)
44 45 46 47 48
Time(s)
I
L
(
m
A
)
100
150
200
250
300
I
C
S
(

A
)
0
5.0
10
15
20
I
C
S
(

A
)
0
5
6
7
4
3
2
1
I
L
(
m
A
)
-100
100
150
-50
0
50
44 45 46 47 48
Fig. 10. Simulated results of I
L
, I
CS
for (a) V
in
3.3 V, V
out
1.2 V, I
load
200 mA and (b) V
in
3.3V, V
out
1.2 V, I
load
50 mA.
Fig. 11. Simulated accuracy of the proposed sensing circuit for load current from
50 mA to 400 mA and V
in
3.3 V, V
out
1.2 V.
Fig. 12. Chip microphotograph of the proposed converter.
M. Yang et al. / Microelectronics Journal 44 (2013) 128136 133
94% and 99.2% for load current from 50 mA to 400 mA, respec-
tively. Therefore this current sensing circuit can be applied in the
proposed converter to ensure high performance.
3. Experimental results
The proposed buck converter shown in Fig. 1 has been
implemented in the SMIC CMOS 0.13 mm process. The converter
is designed to provide variable output voltage and fast response
for SoC DVS application. Fig. 12 shows the micrograph of the chip,
the area of which is only 2.24 mm
2
, including I
2
C communication
interface and bonding PADs. The widths of the power MOSFET M
P
and M
N
are 24,860 mm and 7810 mm, respectively. And the
lengths of them are all 0.35 mm.
I
L
C1
C2
20s/div
43s
1V/div
200mA/div
20s/div
Vout
I
L
V
out
C1
C2
43.5s
20s/div 1V/div
200mA/div 20s/div
Fig. 13. Measured output voltage V
out
(Channel 1) and inductor current I
L
(Channel 2) during the start-up process for (a) no-load and (b) I
load
200 mA.
I
L
V
Pgate
C1
C2
0.5s/div 2V/div
0.5s/div
200mA/div
1V/div
I
L
V
Pgate
C1
C2
0.5s/div
0.5s/div 200mA/div
Fig. 14. Measured steady-state waveforms of M
P
gate voltage V
Pgate
(Channel 1) and inductor current I
L
(Channel 2) for (a) duty cycle o50% (V
in
3.3 V, V
out
0.725 V) and
(b) duty cycle450% (V
in
2.7 V, V
out
1.5 V).
C1
C2
C3
20s/div
V
LX
I
L
20mV/div
22mV
1V/div
100mA/div
20s/div
20s/div
V
out V
out
C1
C2
C3
V
LX
0.5s/div
I
L
4mV
10mV/div
1V/div
200mA/div
0.5s/div
0.5s/div
Fig. 15. Measured steady-state waveforms of output ripple voltage V
out
(Channel 1 AC coupled); switch node LX voltage V
LX
(Channel 2); inductor current I
L
(Channel 3) for
(a) I
load
50 mA and (b) I
load
150 mA.
C1
C2
VSET
19.5s
19.8s
25s
19.5s
20s/div 0.5V/div
20s/div
0.5V/div
V
out
Fig. 16. Measured reference tracking response with I
load
200 mA: V
out
(Channel 1);
V
SET
1.5 V-0.725 V-1.5 V (Channel 2).
M. Yang et al. / Microelectronics Journal 44 (2013) 128136 134
Fig. 13 shows the measured output voltage and inductor
current during the start-up with noload and 200 mA load.
Experimental results can match the analysis results, which can
not induce overshoot voltage and inrush current. And the start-up
time is less than 45 ms. Fig. 14 shows the steady-state wave-
forms of M
p
gate voltage and inductor current under different
conditions. It can be seen that the proposed converter can be
stable for all output voltages. Fig. 15 shows the steady-state
waveforms of output voltage at different load currents. From the
gure, the ripple voltage is 22 mV when the system works in PSM
mode and the ripple voltage is only 4 mV when it works in
PWM mode.
The reference tracking response of output voltage is shown in
Fig. 16. When the set voltage V
SET
changes between 1.5 V and
0.725 V, the output voltage can follow V
SET
better without over-
shoot and undershoot. The down tracking speed is 24.75 ms/V and
up tracking speed is 31.25 ms/V. The converter load transient
response is shown in Fig. 17. The recovery time for a 300 mA step
load transient is 8 ms more or less and the output voltage drop is
only 8 mV. These results can approach the simulated results. The
advantage of the proposed loop can be proved from the measured
load transient response results.
The proposed converter incorporated with DPSS adopting the
PWM and PSM mode gives high conversion efciency in a wide
load range from 1 mA to 400 mA. The measured results are shown
in Fig. 18. When the input voltage is 3.3 V and the output voltage
is 1.5 V, the full load of the conversion efciency of the converter
is above 84%. The peak efciency is over 93.8% at 240 mA.
Table 1 shows the performance comparison with previously
reported works [3,4,21,22]. With all the advancements described
above, the proposed design features higher conversion efciency
and fastest load transient response. On chips safe fast soft-start-
up circuits and preferable reference tracking speed are also
included. Besides, high accuracy sensing circuit design methods
are used to ensure stability over different load and voltage ranges.
All these features are realized in a low size SMIC 0.13 mm CMOS
process.
4. Conclusion
This paper describes a PWM/PSM dual mode converter for DVS
application. The method of the loop without capacitor compensa-
tion and high accuracy sensing circuit is proposed in the design.
The DPSS method is also used to decrease the power. The test chip
has been fabricated using a standard 0.13 mm CMOS process and
experimental results are presented for theoretical analysis. The
experimental results show that the converter has fast response
under different conditions, including start-up, load transient
response and tracking speed. Therefore it can well suit for on-
chip converter implementation especially for mobile devices that
require fast start-up, fast load transient response, high tracking
speed and high conversion efciency.
I
load
C1
C
2
100mA/div
(7.8s,8mV)
(8s,8mV)
10mV/div
20s/div
20s/div
V
out
Fig. 17. Measured load transient response with load current I
load
(Channel 2) step
between 100 mA and 400 mA of the output voltage V
out
(Channel 1).
Fig. 18. Measured conversion efciency for V
in
3.3 V and V
out
1.5 V.
Table 1
Performance comparison.
[3] [4] [21] [22] This work
Technology (mm) 0.35 0.6 0.18 0.35 0.13
Efciency (%) 8894.5 8296.7 72.485.6 87.292.7 84.293.8
Input voltage range (V) 3 2.26 1.8 3 2.73.6
Output voltage range (V) 0.52.5 0.6(V
in
0.2) 1 0.92.1 0.71.5
Maximum load current (mA) 800 1000 500 450 400
Switching frequency 828866 KHz 1.1 MHz 0.6571.2 MHz 1.7 MHz 1.5 MHz
Inductor/capacitor 4.7 mH/10 mF 4.7 mH/10 mF 4.7 mH/10 mF 4.7 mH/9.1 mF 4.7 mH/10 mF
Output ripple voltage (mV) NA o3 15 o10 4
Reference tracking speed (ms/V) 12.5 (up)
100 (down)
NA NA 17.8 (up)
12.5 (down)
31.25 (up)
21.75 (down)
Transient recovery time/transient
voltage variation
NA o20 ms/80 mV@ 500 mA
load step
o10 ms/44 mV@ 400 mA
load step
14.4 ms/52 mV@ 400 mA
load step
o8 ms/8 mV@ 300 mA
load step
Start-up time NA 2 ms NA NA o45 ms
Load regulation (%/A) NA 0.08 1.2 NA 2.2
M. Yang et al. / Microelectronics Journal 44 (2013) 128136 135
Acknowledgment
The authors would like to thank the National Natural Science
Foundation of China (61274022 and 61201034) and the Program
for New Century Excellent Talents in University (NCET-10-0331).
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