Our aim is to design a optical packet synchronizer that aligns the asynchronous packets into its

time slot boundaries. The below content explains how the objective is achieved. It basically
explains how the packets to one packet synchronizer module from channel 1 arriving gets
synchronized into their respective time boundaries and finally the synchronized outputs are
obtained. Similarly we can have other packet synchronizer modules for other channel inputs.

Fig1:optical packet synchronizer

The above diagram is one packet synchronizer module for channel 1 .Similarly,we can have
other packet synchronizer modules for other channel inputs.
1. For every optical packet signals(wavelength 1556.5nm and bitrate 9.95Gbps),a corresponding
optical label signals(wavelength in 1.3m range, bitrate 1.25 Gbps and containing addressing
information)is present. At first, the optical label signal is transmitted and then the optical
packet signal with a predetermined time delay of 202.5ns between them.
2. The WDM Coupler is made to split the optical packet signal from the label signal. The label
signal arrives at the delay counter unit. This optical label was received by a photodiode present
at the delay counter unit (and performs optical to electrical conversion-for a photodiode ,light
is the input and current is the output when operated in the reverse bias),the delay counter
would make use of the delay of this label signal with respect to the reference time to calculate
the delay time. Our optical synchronizer has a time slot of 1024 ns with time resolution of 16ns.
3. The below diagram explains how the delay of the optical label is calculated with respect to
the reference time at the delay counter unit.

Fig2: calculating time delay for the label signal
With reference to the above diagram, now if T_d is about 960ns(distance between the 2
reference lines in above diagram is 1024 ns with 16 ns resolution).This value could be expressed
as the sum of the product of 128 and 16.
960=(128*7)+(16*4)=(896+64)
The reason why we have expressed this as the sum of the product of 128 and 16 is because we
will have our optical packet signal delayed by two stage delay lines. Each stage has 8 delay lines
each.
From fig 1, In the first stage ,each delay line would have a time delay difference of 128ns
between them. So, the first delay line in this stage would have 0 ns delay,next line 128ns delay
and subsequently the 8
th
line would have 896 ns delay.
In the second stage of delay lines, each delay line would have a time difference of 16ns
between them. So, the first delay line in this stage has delay of 0 ns, next one with 16 ns and
subsequently,the 8
th
line with 112 ns.
With respect to our example of 960 ns delay,we shall examine how this system chooses it as a
sum of 896ns and 64 ns.
The basic idea is that the optical packet signal as it appears at the first stage and the second
stages of delay lines should occur this 960ns delay so that the packet signal is aligned within the
time slot of 1024 ns. Our packet signals would be of 1024ns duration including 128 ns guard
band,(i.e 896ns of info +128ns guard band=1024ns).
4. The delay counter(in fig 1) would be 6 bits wide, with each count being 16 ns
So if bit pattern xxxxxx(6bits)-their place values from LSB to MSB would be
16,32,64,128,256,512
So the least value of the delay counter would be
000000-0 ns
To the highest value of
111111----16+32+64+128+256+512= 1008 ns. Note that if the count had been 1024 ns
(1008+16 ns), then it would mean its perfectly aligned within its time slot, so no more
alignment required.
So coming back to our case of 960 ns,the counters count would be 111100.Let us take left 3
bits as the MSB and the right 3 bits as the LSB.The MSB is used to choose first stage of delay
lines(present after the SOAG) and the LSB to choose the second stage of delay lines.
MSB1118(base 2 system.)8
th
delay line in first stage. This MSB would act as the control
signals to the SOAG(to make that respective SOAG act as a gate to allow packets pass) to direct
the optical packets to that stage
LSB---100---4(base 2)---4
th
delay line in second stage.
The delay lines in the second stage are wavelength dependent as in fig 1 ,since an AWG DEMUX
is used to pass the optical packet with that corresponding wavelength on to that delay line.
These wavelengths 1-8 (1554.1 nm TO 1548.5 nm with channel spacing of 0.8 nm)are available
from a DBR tunable LD.
So, for choosing the proper delay line in the second stage ,DBR LD has to be properly tuned.
They can be properly tuned by controlling the injection current to the DBR region of the LD.
There must be a mechanism wherein the delay counter uses the LSB bits to control the current
output from the photodiode where the optical packet is received and then control this as the
injection current to the DBR LD, so that it can operate at that correct wavelength range. Then
the wavelength conversion of the packet signal using wavelength convertor(WC) is done using
the continous wave light from DBR LD. The optical packet would be fed to wavelength
convertor based on XPM.
5. The optical splitter is used to direct the packets to one of the SOAG.SOA acts as
gates/switching elements and also help undo the losses from other passive components like
couplers etc. other elements used in the system are optical couplers and EDFA.The control
signals from delay counter unit to SOAG and tunable DBR LD is given after some delay so that
the gating action of the SOA(fig1) is facilitated and that the packets have arrived properly.
6. At the output from the AWG MUX , we would see synchronized output of channel and this
could be directed tom the required port. So, the synchronization is used from any one of the 64
paths (from 1
st
and 2
nd
delay stages.).