Contents

1.

UART...................................................................................................................................................... 1
Receiver..................................................................................................................................................... 1
USART........................................................................................................................................................ 1

2.

I2c .......................................................................................................................................................... 1
I2C Transfer Protocols....................................................................................................................... 2
The fast rate corresponds to a data transfer rate of 50K bytes/sec which is too slow for
some control applications. ................................................................................................................ 2

3.SPI............................................................................................................................................................... 2
OPERATION MODES ...................................................................................................................................... 3

1. UART

Receiver - All operations of the UART hardware are controlled by a clock signal which runs at a
multiple of the data rate, typically 8 times the bit rate. The receiver tests the state of the incoming signal
on each clock pulse, looking for the beginning of the start bit. If the apparent start bit lasts at least onehalf of the bit time, it is valid and signals the start of a new character. If not, it is considered a spurious
pulse and is ignored. After waiting a further bit time, the state of the line is again sampled and the
resulting level clocked into a shift register

USART chips have both synchronous and asynchronous modes. In synchronous transmission, the clock
data is recovered separately from the data stream and no start/stop bits are used. This improves the
efficiency of transmission on suitable channels since more of the bits sent are usable data and not
character framing.
Max speed 115.2 KB/ps

2. I2c

The Inter-Integrated Circuit (I2C) bus is a two wire multi-master/slave low speed serial bus. The different
devices are accessed by transmitting unique 7-bit addresses.
The bus is composed of two bidirectional pins:
SCL - Serial Clock signal
2. SDA - Serial Data signal
1.

Since communication on the bus is half-duplex, slaves do not transmit any data unless a master has
first addressed it.

I2C Transfer Protocols

A normal transfer has the master send a start bit followed by the 7-bit address followed by a single
bit to indicate whether it will be reading or writing the address. The slave at the corresponding
address responds with an acknowledgment bit followed by 8-bits of data. At this point, the master
can either transmit another start bit or it can issue a stop bit to stop transfers.

The fast rate corresponds to a data transfer rate of 50K bytes/sec which is too slow for some
control applications.

3.SPI

OPERATION MODES

At CPOL=0 the base value of the clock is zero

For CPHA=0, data are captured on the clock's rising edge (lowhigh transition) and data is
propagated on a falling edge (highlow clock transition).

For CPHA=1, data are captured on the clock's falling edge and data is propagated on a rising edge.

At CPOL=1 the base value of the clock is one (inversion of CPOL=0)

For CPHA=0, data are captured on clock's falling edge and data is propagated on a rising edge.

For CPHA=1, data are captured on clock's rising edge and data is propagated on a falling edge.

***During each SPI clock cycle, a full duplex data transmission occurs:

the master sends a bit on the MOSI line; the slave reads it from that same line

the slave sends a bit on the MISO line; the master reads it from that same line

maximum bit rate possible : 10Mbps