MindShare x86 ISA

Intel Core 2 Processor (Penryn)
Intel Nehalem Processor

Intel Atom Processor
AMD Opteron Processor (Barcelona)
Intel 32/64-bit x86 Software Architecture
AMD 32/64-bit x86 Software Architecture
x86 Assembly Language Programming
Protected Mode Programming
PC Virtualization
IO Virtualization (IOV)
Computer Architectures with Intel Chipsets
Intel QuickPath Interconnect (QPI)
PCI Express 2.0
USB 2.0
USB 3.0
Embedded USB 2.0 Workshop
PCI
PCI-X
Modern DRAM Architecture
SAS
Serial ATA
High Speed Design
EMI / EMC
Bluetooth Wireless Product Development
SMT Manufacturing
SMT Testing

Basic Terms and Concepts
Mode/SubMode

1
Is This the Book for You?
A Moving Target
x86 Instruction Set Architecture (ISA)

x86 Instruction Set Architecture
2
Glossary of Terms
32-/64-bit x86 Instruction Set Architecture Specification
The Specification Is the Final Word

About This Book
3
Book Organization
Mode/SubMode

4
Topics Outside the Scope of This Book
The CPUID Instruction
Detailed Description of Hyper-Threading

About This Book
5
Detailed Description of Performance Monitoring
Documentation Conventions
Trademarks

6
Visit Our Web Site

About This Book
7
We Want Your Feedback

8

Part 1
Mode/SubMode
The Next Part

11
This Chapter
The Next Chapter
ISA Definition
This Book Focuses on the Common Intel/AMD ISA
For Simplicity, Intel Terminology Is Used Throughout

12
Some Terms in This Chapter May Be New To the Reader
Two x86 ISA Architectures

Chapter 1: Basic Terms and Concepts
13
Processors, Cores and Logical Processors

14
Fundamental Processing Engine: Logical Processor

15
IA Instructions vs. Micro-ops
RISC Instructions Sets Are Simple
x86 Instruction Set Is Complex

16
But You Cant Leave It Behind
Complexity vs. Speed Dictated a Break With the Past
Why Not Publish a Micro-Op ISA?

17
Some Important Definitions
Virtual vs. Physical Memory

18
Other Important Terms

19

20

21
The Previous Chapter
This Chapter
The Next Chapter
Basic Execution Modes

22

Chapter 2: Mode/SubMode Introduction
23

24

25
IA-32 SubModes

26

27

28
IA-32e SubModes

29

30
Mode Switching Basics
Initial Switch from IA-32 to IA-32e Mode

31

32

33
IA-32e SubMode Selection

34

35

36

37

38
Protected/Compatibility 16-/32-bit SubModes

39

40

41
This Chapter
The Next Chapter

42
Major Evolutionary Developments

Chapter 3: A (very) Brief History
43

44

45

46
16-bit Mode Background
8086 and Real Mode

47

48
286 Introduced 16-bit Protected Mode

49

50

51
386 Supported Both 16- and 32-bit Protected Mode

52

53

54

55
The Intel Microarchitecture Families

56

57
A Brief Timeline

58

59

60

61

62

63
This Chapter
The Next Chapter

64
State After Reset

Chapter 4: State After Reset
65

66

67

68

69

70

71

72

73
Soft Reset
Boot Strap Processor (BSP) Selection

74
AP Discovery and Configuration
Initial Memory Reads

75

76

The Previous Part
This Part

The Next Part

79
This Chapter

80
The Next Chapter
The Pre-386 Register Sets
8086 Register Set

Chapter 5: Intro to the IA-32 Ecosystem
81

82
286 Register Set

83

84
IA-32 Register Set Overview

85
Control Registers

86

87

88
Status/Control Register (Eflags)

89
Instruction Fetch Facilities
General

90
Branch Prediction Logic
General Purpose Data Registers

91

92
Defining Memory Regions/Characteristics
MTRRs
Segment Registers

93
Address Translation Facilities
Interrupt/Exception Facilities

94
Kernel Facilities

95
Real Mode Has No Memory Protection
Memory Protection in Protected Mode
Introduction
Segment Selection in Protected Mode

96
Access Rights Check
The Descriptor Tables
Descriptor Table Registers

97
Task Data Structure
Address Translation Facilities
Effective/Virtual/Linear/Physical Addresses

98
Introduction to Address Translation (Paging)
RAM Is Finite and Cant Hold Everything

99
RAM and Mass Storage Are Managed on a Page Basis
This Requires a Series of Directories
Malloc Request

100
Problem: Non-Contiguous Memory Allocation
Malloc Returns a Virtual Address to the Application

101
IA-32 Applications Have a 4GB Virtual Address Space
Legacy FP Facilities
In the Beginning, FPU Was External and Optional

102
It Was Slow...
486DX Integrated It
x87 Register Set
x87 FP Instruction Set
General Purpose Instruction Set
MMX Facilities

103
Introduction
SIMD Programming Model

104
SSE Facilities
Introduction
Motivation

105
Instruction Set
Model-Specific Registers
General

106
Accessing the MSRs
Debug Facilities

107
Automatic Task Switching Mechanism

108

109
This Chapter

110
The Next Chapter
Why a Comprehensive Instruction Set Listing Isnt
Included

Chapter 6: Instruction Set Expansion
111
386 Instruction Set

112

113

114

115

116

117
Instruction Set (as of March, 2009)

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155
This Chapter

156
The Next Chapter
64-bit Machine Language Instruction Format
A Complex Instruction Set with Roots in the Past

Chapter 7: 32-bit Machine Language Instruction Format
157
Effective Operand Size
Introduction
Operand Size in 16- and 32-bit Code Segments

158
Operand Size in 64-bit Code Segments

159

160
Instruction Composition

161

162
Instruction Format Basics

163

164

165

166

167

168
Opcode (Instruction Identification)
In the Beginning

169
1-byte Opcodes

170

171

172
2-byte Opcodes Use 2-Level Lookup
2nd-Level Opcode Map Introduced in 286
Instructions with 2-byte Opcodes: Five Possible Forms

173
A 2-byte opcode preceded by a prefix byte being used in a non-stan-
dard manner (see Special Use of Prefix Bytes on page177) that alters
the characteristics of the instruction.

174

175

176
3-byte Opcodes Use 3-Level Lookup
3-Level Opcode Maps Introduced in Pentium 4 Prescott
Currently There Are Two 3rd-Level Maps Defined
Instructions with 3-byte Opcodes: Three Possible Forms

177
A 3-byte opcode preceded by a prefix byte being used in a non-standard
manner (see Special Use of Prefix Bytes on page177) that alters the
characteristics of the instruction.
Special Use of Prefix Bytes

178

179

180
Opcode Micro-Maps (Groups)
Micro-Maps Associated with 1-byte Opcodes
Some Opcodes Employ 2 x 8 Micro-Maps

181

182

183
Micro-Maps Associated with 2-byte Opcodes

184

185

186

187
3-byte Opcodes Dont Use Micro-Maps
x87 FP Opcodes Inhabit Opcode Mini-Maps

188

189
Special Opcode Fields

190

191

192

193

194
Operand Identification
General

195
Specifying Registers as Operands

196
Implicit Register Specification
Explicit Register Specification in Opcode
Explicit Register Specification in ModRM Byte

197

198
Addressing a Memory-Based Operand
Instruction Can Specify Only One Memory-Based Operand

199

200
Addressing Memory Using the ModRM Byte

201

202

203
Using the SIB Byte to Access a Data Structure

204

205

206
Near and Far Branch Target Addressing

207

208

209
Specifying an Immediate Value As an Operand

210
Instruction Prefixes

211
Operand Size Override Prefix (66h)
In 32-bit Mode

212

213
In 16-bit Mode
Special Usage of 66h Prefix

214
Address Size Override Prefix (67h)
In 32-Bit Mode

215
In 16-Bit Mode
Lock Prefix
Shared Resource Concept

216
Race Condition Can Present Problem
Guaranteeing Atomicity of Read/Modify/Write

217
Use Locked RMW to Obtain and Give Up Semaphore Owner-
ship

218
Instructions That Accept Lock Prefix
Repeat Prefixes
Normal Usage

219

220
Special Usage
Segment Override Prefix
General

221
Usage In String Operations
Segment Override Use With MMX and SSE1 - 4 Instructions
Branch Hint Prefix

222
Summary of Instruction Set Formats

223

224

225

226

227

228
This Chapter
The Next Chapter

Chapter 8: Real Mode (8086 Emulation)
229
8086 Emulation

230

231
Unused Facilities

232
Real Mode OS Environment
Single-Task OS Environment Overview
Command Line Interface (CLI)

233
Program Loader
OS Services

234
Direct IO Access
Application Memory Usage
Task Initiation, Execution and Termination

235
Running Real Mode Applications Under a Protected Mode
OS
Real Mode Applications Arent Supported in IA-32e Mode
Real Mode Register Set
Introduction

236

237
Control Registers

238
CR0

239

240

241

242

243
Address Translation (Paging) Control Registers

244
CR4 (Feature Control Register)

245

246

247

248

249
XCR0 (XFEM)

250

251
Flags Register

252

253

254

255
General Purpose Registers (GPRs)
A, B, C and D Registers

256
EBP Register: Stack Frame Address Register

257

258
Index Registers

259
Stack Pointer (SP) Register
Instruction Pointer Register

260
Kernel Registers
x87/MMX FPU Register Set

261

262
SSE Register Set
Debug Address Breakpoint Register Set
General

263
Defining Trigger Address Range

264
Defining Access Type
Defining Scope (Current Task or All Tasks)
Special Notes

265

266

267

268

269
Local APIC Register Set

270

271

272
Architecturally-Defined MSRs
General
Determining MSR Support
Accessing the MSRs

273

274

275

276

277

278

279

280

281
IO Space versus Memory Space
IO Operations
IO Operations in IO Address Space
IN and OUT Instructions

282
Block (String) IO Operations

283

284
IO Space is Limited and Crowded
Memory-Mapped IO (MMIO) Operations
Introduction
Know the Characteristics of Your Target
Why the Logical Processor Must Know the Memory Type

285
Uncacheable (UC) Memory

286
No IO Protection
Operand Size Selection

287
Address Size Selection

288
Real Mode Memory Addressing
No Address Translation
Introduction to Real Mode Segmentation

289

290

291

292
All Segments are 64KB in Size

293
Memory Address Representation
Accessing the Code Segment

294
Jumping Between Code Segments
Far Jumps and Calls

295
Near Jumps and Calls

296
IP-Relative Branches
Operations That Default to the Code Segment

297
Accessing the Stack Segment
Introduction

298
Stack Characteristics
Pushing Data Onto the Stack

299

300
Popping Data From the Stack
Stack Underflow/Overflow

301
Processor Stack Usage
Accessing Parameters Passed on the Stack

302
Operations That Default To the Stack Segment

303
Accessing the DS Data Segment
General
Operations That Default to the DS Data Segment

304
Accessing the ES/FS/GS Data Segments
General

305
Operations That Default to the ES Data Segment
Segment Override Prefixes
Example Segment Register Initialization

306

307
Accessing Extended Memory in Real Mode

308

309

310
Big Real Mode

311
286 DOS Extender Programs
Hot Reset and 286 DOS Extender Programs

312
Alternate (Fast) Hot Reset

313
286 DOS Extenders on Post-286 Processors

314

315
String Operations

316
Real Mode Interrupt/Exception Handling
Events and Event Handlers

317
Events Are Recognized on an Instruction Boundary
The IDT
Definition of the IDT

318

319

320

321

322

323

324
IDT and IDTR Initialization

325
Stack Initialization

326
Event (Interrupt and Exception) Handling

327
Software Event Types
Introduction

328
Software Exceptions

329

330
Software Interrupt Instructions

331

332
Hardware Event Types
NMI

333

334
SMI
Maskable Interrupts

335

336
Machine Check Exception

337
Summary of Real Mode Limitations
Transitioning to Protected Mode

338

339
This Chapter

340
The Next Chapter
A Little History

Chapter 9: Legacy x87 FP Support
341
x87 FP Instruction Format
FPU-Related CR0 Bit Fields

342

343
x87 FPU Register Set
The FP Data Registers

344
x87 FPUs Native Data Operand Format

345

346
32-bit SP FP Numeric Format
Background
A Brief IEEE FP Primer

347
The 32-bit SP FP Format

348
Representing Special Values
An Example

349
Another Example

350
DP FP Number Representation
FCW Register

351

352
FSW Register

353

354

355
FTW Register
Instruction Pointer Register
Data Pointer Register

356
Fopcode Register
General
Fopcode Compatibility Mode

357
FP Error Reporting
Precise Error Reporting
Imprecise (Deferred) Error Reporting

358
Why Deferred Error Reporting Is Used
The WAIT/FWAIT Instruction
CR0[NE]

359
DOS-Compatible FP Error Reporting
FP Error Reporting Via Exception 16

360
Ignoring FP Errors

361

362
This Chapter
The Next Chapter

Chapter 10: Introduction to Multitasking
363
Concept

364
An ExampleTimeslicing
Another ExampleAwaiting an Event
1. Task Issues Call to OS for Disk Read
2. Device Driver Initiates Disk Read

Chapter 10: Introduction to Multitasking
365
3. OS Suspends Task
4. OS Makes Entry in Event Queue
5. OS Starts or Resumes Another Task
6. Disk-Generated Interrupt Causes Jump to OS

366
7. Interrupted Task Suspended
8. Task Queue Checked
9. OS Resumes Task

367
This Chapter

368
The Next Chapter
Hardware-based Task Switching Is Slow!

Chapter 11: Multitasking-Related Issues
369
Private (Local) and Global Memory
Preventing Unauthorized Use of OS Code

370
With Privilege Comes Access
Program Privilege Level
The CPL

371
Calling One of Your Equals
Calling a Procedure to Act as Your Surrogate
Data Segment Protection
Data Segment Privilege Level
Read-Only Data Areas

372
Some Code Segments Contain Data, Others Dont

373

374
IO Port Anarchy

375
No Interrupts, Please!

376
BIOS Calls

377

378
This Chapter
The Next Chapter
Protection-Related Mechanisms

Chapter 12: Summary of the Protection Mechanisms
379

380

Chapter 12: Summary of the Protection Mechanisms
381

382

383
This Chapter
The Next Chapter

384
Real Mode Segment Limitations

Chapter 13: Protected Mode Memory Addressing
385
An Important Reminder: Segment Base + Offset = Virtual
Address

386
Descriptor Contains Detailed Segment Description
Segment RegisterSelects Descriptor Table and Entry

387

388

389

390
Introduction to the Descriptor Tables
Segment Descriptors Reside in Memory

391

392

393
Global Descriptor Table (GDT)
GDT Description
Setting the GDT Base Address and Size

394
GDT Entry 0

395
Local Descriptor Tables (LDTs)
General

396
Creating and Selecting an LDT

397

398

399
General Segment Descriptor Format
Granularity Bit and the Segment Size

400
Segment Base Address Field
Default/Big Bit
In a Code Segment Descriptor, D/B = Default Bit

401
Override Prefixes

402
In a Stack Segment Descriptor, D/B = Big Bit

403
Segment Type Field
Introduction to the Type Field
Non-System Segment Types

404

405

406
Segment Present Bit
Descriptor Privilege Level (DPL) Field

407
System Bit

408
Available Bit
Goodbye to Segmentation
Introduction

409
IA-32 Flat Memory Model

410

411

412
No Protection? Paging Takes Care of It
A Reminder of Where We Are

413

414

415
This Chapter

416
The Next Chapter
Abbreviation Alert
Selecting the Active Code Segment

Chapter 14: Code, Calls and Privilege Checks
417

418
CS Descriptor
CS Descriptor Selector

419
Calculating the Descriptors Memory Address
Descriptor Read and Privilege Checked
CS Descriptor Format

420

421

422

423
Accessing the Code Segment
In-Line Code Fetching
Short and Near Branches (Jumps and Calls)
General

424
Example Near Jump
Far Branches (Far Jumps and Calls)
General

425
Example Far Jump

426

427
Short/Near Jumps
General
No Privilege Check
Unconditional Short/Near Branches

428
Conditional Branches
General

429

430

431
Loop Instructions

432

433

434
Unconditional Far Jumps
The Privilege Check

435
Far Jump Targets
Far Jump Forms

436
Privilege Checking
No Check on Near Calls or Near Jumps

437
General
Definitions
Definition of a Task
Definition of a Procedure
CPL Definition

438
CS DPL Definition
Conforming and Non-Conforming Code Segments

439
RPL Definition

440
Privilege Check on Far Call or Far Jmp
General
Example

441
Jumping from a Higher-to-Lesser Privileged Program

442
Direct Procedure Calls
Introduction
General

443
Near Calls/Returns
Description

444

445
Call/Ret Operand Size Matching
Near Call/Return Forms

446

447
Far Calls
General
Far Call Forms

448

449

450

451
Far Call, Same Privilege Level
Far Call to a More-Privileged Procedure

452
Far Call to a Procedure in a Different Task
Indirect Procedure Far Call Through a Call Gate
Example Scenario Defines the Problem
The Scenario

453
The Problem

454
The SolutionDifferent Gateways
The Call Gate Descriptor

455

456
Call Gate Example
Execution Begins

457
Call Gate Descriptor Read

458
Call Gate Contains Target Code Segment Selector

459
Target Code Segment Descriptor Read

460

461
The Big Picture
The Call Gate Privilege Check

462
Automatic Stack Switch
Background
A Potential Problem
The Solution: Pre-Allocated Stacks

463

464

465

466
Far Call From 32-bit CS to 16-bit CS
General
Method 1: Far Call with Operand Size Override Prefix

467
Method 2: Far Call Via 16-bit Call Gate

468

469

470
Method 3: Call 32-bit/16-bit Interface Procedure

471
Far Call From 16-bit CS to 32-bit CS

472
Method 1: Far Call With an Operand Size Prefix

473
Method 2: Far Call Via a 32-bit Call Gate

474

475
Far Returns
General

476
Far Return Forms

477

478

479
This Chapter

480
The Next Chapter
A Note Regarding Stack Segments

Chapter 15: Data and Stack Segments
481
Data Segments
General
Two-Step Permission Check

482
An Example

483

484
Selecting and Accessing a Stack Segment
Introduction

485
Expand-Up Stack

486

487
Expand-Down Stack
The Problem

488

489
Expand-Down Stack Description

490
An Example

491
Another Example

492

493
This Chapter

494
The Next Chapter
Three Generations

Chapter 16: IA-32 Address Translation Mechanisms
495
Demand Mode Paging Evolution

496
Background
Memory and Disk: Block-Oriented Devices
Definition of a Page

497
Example Scenario: Block Transfer from Disk to
Memory

498
A Poor Memory Allocation Strategy

499
Applications Are Presented With a Simplified World-View
Introduction
Life Without Paging Would Be Chaotic

500
The Virtual World Is a Simple One

501

502

503

504

505

506
Virtual Address Space Partitioning

507

508
Example Virtual Buffer Allocation

509
Address Translation Advantages
Introduction
Simplifies Memory Management

510
Efficient Memory Usage
A Wasteful Approach

511
A Better Approach: Load On Demand
Attribute Assignment

512
Track Access History
Allows DOS Applications to Co-Exist
Problem: Running Multiple DOS Programs
Solution: Address Redirection

513
First-Generation Paging
Definition of First Generation Paging

514
Paging Logics Interpretation of a Virtual Address

515
First-Generation Paging Overview
The Set-Up

516
Virtual-to-Physical Address Translation

517

518

519

520

521

522
Two Overhead Memory Reads Take a Toll

523
The TLBs
TLB Miss

524
TLB Hit
TLB Maintenance

525
TLBs Are Cleared on Task Switch or Page Directory Change
Updating a Single Page Table Entry

526
Global Pages
Problem
Global Page Feature

527
Enabling Paging

528

529
Detailed Description of PDE and PTE
PDE Layout

530

531
PTE Layout

532

533

534

535
Checking Page Access Permission
The Privilege Check
Segment Privilege Check Takes Precedence Over Page Check

536
U/S Bit in PDE and PTE Are Checked

537
Accesses with Special Privilege
The Read/Write Check

538
Missing Page or Page Table
Introduction
Page Table Not Present

539

540

541

542
Page Not Present

543

544

545
Page Faults
Page Fault Causes

546
Page Fault During a Task Switch

547
Page Fault while Changing to a Different Stack
Page Fault Error Code
Additional Page Fault Information

548
Access History

549

550
4MB Pages
Basic Concept
Enabling the PSE Feature
Simplifies Housekeeping

551
How To Set Up a 4MB Page

552
The Address Translation

553
Second-Generation Paging
First-Gen Problem: 4GB Physical Memory
The Solution: PAE-36 Mode
Enabling PAE-36 Mode

554
CR4[PSE] Is Dont Care
Application Still Limited to a 4GB Virtual Address
Space

555
Virtual Address Space Partitioning
First Generation Partitioning

556
Second Generation Partitioning

557
Second Generation Uses 3-Level Lookup Mechanism

558
CR3 Points to PDPT in Lower 4GB

559
Enlarged Physical Address Space

560
The Translation
Step 1: PDPT Lookup

561

562
Step 2: Page Directory Lookup

563

564

565
Step 3: Page Table Lookup

566

567
Page Protection Mechanisms
General

568
Write-Protection

569
Example Usage: Unix Copy-on-Write Strategy

570

571
3-Level LookupIncreased TLB Size

572
Microsoft PAE Support

573

574
Linux PAE Support
PSE-36 Mode (PAE-36 Modes Poor Cousin)

575
PSE-36 Mode Background
Detecting PSE-36 Mode Capability
Enabling PSE-36 Mode

576
Per Application Virtual Memory Space = 4GB
First-Generation Lookup Mechanism
Selected PDE Can Point to 4KB Page Table or a 4MB
Page

577
Virtual Address Maps to a 4MB Page in 64GB Space

578
Windows and PSE-36

579
AMD Enhanced PSE-36 to PSE-40
Execute Disable Feature
Problem: Malicious Code
The Overflow

580

581
The Exploit

582
The Fix: Intercept Code Fetches from Data Pages
Enabling the Execute-Disable Feature

583
Available in both IA-32 and IA-32e Mode
How It Works

584

585
Defining a Pages Caching Rules
Introduction
Translation Table Caching Rules
General

586
First-Generation Paging Tables
Second-Generation Paging Tables

587
Page Caching Rules
PAT Feature (Page Attribute Table)
Whats the Problem?

588
Detecting PAT Support
PAT Allows More Memory Types

589
Default Contents of IA32_CR_PAT MSR

590
Memory Type When Page Definition and MTRR
Disagree

591

592

593
Altering IA32_CR_PAT MSR
Ensuring IA32_CR_PAT and MTRR Consistency

594

595
Assigning Multiple Memory Types to a Single
Physical Page

596
Compatibility with Earlier IA-32 Processors

597
Third Generation Paging

598

599
This Chapter

600
The Next Chapter
Characteristics of Memory Targets
Introduction
Example Problem: Caching from MMIO

Chapter 17: Memory Type Configuration
601
Early Processors Implemented Primitive Mechanism

602
Solution/Problem: Chipset Memory Type Registers
Solution: Memory Type Register Set

603
MTRR Feature Determination

604
MTRRs Are Divided Into Four Categories
MTRRDefType Register

605
State of the MTRRs after Reset
Fixed-Range MTRRs
The Problem: Legacy Issues
Enabling the Fixed-Range MTRRs

606
Defining Memory Types in Lower 1MB

607
Variable-Range MTRRs
How Many Variable-Range Register Pairs?
Variable-Range Register Pair Format

608
MTRRPhysBasen Register
MTRRPhysMaskn Register

609
Programming Variable-Range Register Pairs
Enabling Variable-Range Register Pairs
Memory Types
Memory Type Defines Processor Aggressiveness

610
Five Memory Types
Uncacheable (UC) Memory

611
Uncacheable Write-Combining (WC) Memory
Description

612
Weakly-Ordered Writes
Cacheable Write-Protect (WP) Memory

613
Cacheable Write-Through (WT) Memory

614
Cacheable Write-Back (WB) Memory

615
The Definition of a Speculatively Executed Load

616
Rules as Defined by MTRRs

617
Memory Type Provided in Memory Transaction
Paging Also Defines Memory Type

618
In an MP System, MTRRs Must Be Synchronized
Posted-Write Related Issues
General
Synchronizing Events

619
PMWB and WCBs Arent Snooped

620
WCB Usage
An Example

621

622

623

624

625

626

627
All WCBs in Use

628
Draining the WCBs

629
This Chapter

630
The Next Chapter
Hardware- vs. Software-Based Task Switching

Chapter 18: Task Switching
631
A Condensed Conceptual Overview
A More Comprehensive Overview
The Scheduler and the Task Queue

632
Setting Up a Task
The Task Data Structure

633
The LDT
The TSS

634
The Address Translation Tables

635
The GDT and GDTR Register

636
The LDTR Register

637
The Task Register (TR)

638
Starting a Task

639
Suspend Task and Resume Scheduler
Execution

640

641
Hardware-Based Task Switching
Its Slow

642
Why Didnt OSs Use It?
Why Wasnt It Improved?
Why Does It Still Exist?
Introduction to the Key Elements

643

644

645

646
The Trigger Events

647

648
The Descriptors
TSS Descriptor

649
Task Gate Descriptor

650

651

652
The Task Register
General
TR Instruction Pair

653

654
TSS Data Structure Format
General

655
Required Fields
Optional Fields

656
Register Snapshot Area

657

658

659
Debug Trap Bit (T)
IO Port Access Protection

660

661
IO Permission Bit Map

662

663

664
Interrupt Redirection Bit Map
OS-Specific Data Structures
Privilege Level 0 - 2 Stack Definition Fields

665
Link Field (to Old TSS Selector)
Comprehensive Task Switch Description

666

667

668

669

670
Calling Another Task
An Overview

671
A Comprehensive Example

672

673

674

675

676

677
LTR Instruction and the Busy Bit
When Is Busy Cleared?
Critical Error: Switching to a Busy Task

678
Busy Toggle Is a Locked Operation
Linkage Modification
Task Switching and Address Translation
One GDT to Serve Them All

679
Each Task Can Have Different Virtual-to-Physical Mapping
TSS Mapping Must Remain the Same for All Tasks

680
Placement of a TSS Within a Page(s)
Switch from More-Privileged Code to Lower
Software-Based Task Switching

681
This Chapter

682
The Next Chapter
Handler vs. ISR

Chapter 19: Protected Mode Interrupts and Exceptions
683
Real Mode Interrupt/Exception Handling

684
The IDT
General

685
Protected Mode IDT and the IDTR

686

687

688
The Gates
Introduction

689

690

691
Interrupt Gate

692

693
Trap Gate

694
Actions Taken When Interrupt or Trap Gate Selected

695

696
Actions Taken When Task Gate Selected

697
Interrupt/Exception Event Categories

698

699
General Event Handling

700

701

702

703

704
State Saved on Stack (but which stack?)

705

706

707

708
Return to the Interrupted Program
General

709
The IRET Instruction

710

711

712

713
Maskable Hardware Interrupts
General
Maskable Interrupt Vector Delivery

714
PC-Compatible Vector Assignment

715

716

717

718

719
Actions Performed by the Handler

720
Effect of CLI/STI Execution
General

721

722
Other Events That Affect Interrupt Flag Bit

723
Protected Mode Virtual Interrupt Feature
Non-Maskable Interrupt (NMI) Requests
PC-Compatible NMI Logic
NMI Description

724
More Detailed Coverage of Hardware Interrupt Handling
Machine Check Exception

725
SMI (System Management Interrupt)
Software Interrupts

726
INT nn Instruction
INTO Instruction

727
BOUND Instruction
INT3 (Breakpoint) Instruction

728
Software Exceptions
General
Faults, Traps, and Aborts

729

730

731

732

733

734

735
Instruction Restart After a Fault
Exception Error Codes

736

737

738

739
Interrupt/Exception Priority

740

741

742

743
Detailed Description of Software Exceptions
Divide-by-Zero Exception (0)
Processor Introduced In
Exception Class
Description
Error Code
Saved Instruction Pointer
Processor State

744
Debug Exception (1)
Exception Class
Description

745
Error Code
Processor State
The Resume Flag Prevents Multiple Debug Exceptions

746
NMI (2)
Exception Class
Error Code
Processor State
Breakpoint Exception (3)

747
Exception Class
Description
Error Code
Processor State

748
Overflow Exception (4)
Exception Class
Description
Error Code
Processor State
Array Bounds Check Exception (5)

749
Exception Class
Description
Error Code
Processor State
Invalid OpCode Exception (6)
Exception Class
Description

750
Error Code

751
Processor State
Device Not Available (DNA) Exception (7)
Exception Class
Description

752
Error Code
Processor State
Double Fault Exception (8)
Exception Class

753
Description

754

755
Shutdown Mode

756
Error Code
Processor State
Coprocessor Segment Overrun Exception (9)
Exception Class
Description
Error Code

757
Processor State
Invalid TSS Exception (10)
Exception Class
Description

758
Error Code

759
Processor State
Segment Not Present Exception (11)
Exception Class

760
Description
Error Code

761
Processor State
Stack Exception (12)
Exception Class
Description

762
Error Code

763
Processor State
General Protection (GP) Exception (13)
Exception Class
Description

764

765
Error Code

766
Processor State
Page Fault Exception (14)
Exception Class
Description

767
Error Code

768
CR2
Processor State

769
Page Fault During a Stack Switch

770
Vector (Exception) 15
FPU Exception (16)
Exception Class
Description

771
Handling of Masked Errors

772
Handling of Unmasked Errors

773
Error Code
Processor State

774
Alignment Check Exception (17)
Background: Misaligned Transfers Affect Performance
Alignment Is Important!

775
Exception Class
Description

776
Implicit Privilege Level 0 Accesses
Storing GDTR, LDTR, IDTR or TR

777
FP/MMX/SSE Save and Restore Accesses
MOVUPS and MOVUPD Accesses
FSAVE and FRSTOR Accesses
Error Code

778
Processor State
Machine Check Exception (18)
Exception Class
Description
Error Code

779
Processor State
SIMD Floating-Point Exception (19)
Exception Class
Description

780

781

782
Exception Error Code
Processor State
Legacy Problem: 2-Step SS:ESP Update
Problem Description
The Solution

783
This Chapter

784
The Next Chapter
A Special Note
Real Mode Applications Are Dangerous

Chapter 20: Virtual 8086 Mode
785
Solution: a Watchdog

786

787
Real Mode Applications Run at Privilege Level 3
Switching Between Protected Mode and VM86 Mode
Eflags[VM] = 1 Switches Processor into VM86 Mode

788
But Software Cannot Directly Access Eflags[VM]
Scheduler Activates VM86 Mode

789
Exiting VM86 Mode
Determining Interrupted Task Is a Real Mode Task

790
Returning to VM86 Mode from VMM
VMM Passes Control to Real Mode Interrupt/Excep-
tion Handler
Real Mode Applications World View
The DOS World

791

792
Memory Address Formation in VM86 Mode

793
Multiple DOS Domains in Separate 1MB Areas

794

795
VMM Should Not Reside in the HMA

796
Dealing with Segment Wraparound
8088/8086 Processor
286 and Later Processors
Solutions

797
Using the Address Size Override Prefix
Sensitive Instructions
Problematic Instructions

798
CLI (Clear Interrupt Enable) Instruction
STI (Set Interrupt Enable) Instruction

799
PUSHF (Push Flags) Instruction
POPF (Pop Flags) Instruction
INT nn (Software Interrupt) Instruction
IRET (Interrupt Return) Instruction

800
Solution: IOPL Sensitive Instructions
Handling Direct IO
The Problem
IO-Mapped IO
IO Permission in Protected Mode

801
IO Permission in VM86 Mode

802
Memory-Mapped IO

803
To Permit an Access
To Deny an Access
For Finer Control
Handling Video Frame Buffer Updates

804
Handling Exceptions in VM86 Mode
Processor Actions

805
Option 1.
Option 2.
Option 3.

806
Option 1: Protected Mode Handler Services
Exception
Option 2: Handler Passes Exception to VMM for
Servicing

807

808
Option 3: Exception Handled by Another Task

809
Hardware Interrupt Handling in VM86 Mode
NMI, SMI, and Maskable Interrupts

810

811
Real Mode Applications Unreal Reality

812
VM86 Task Executes CLI When VME = 0
CLI Handling

813
Subsequent High-Priority Interrupt Detected
Servicing of Lower-Priority Interrupt Deferred

814

815

816
STI/POPF/PUSHF/IRET Handling When VME = 0
Attempted Execution of STI Instruction (VME = 0)
Attempted Execution of PUSHF Instruction (VME = 0)

817
Attempted Execution of POPF Instruction (VME = 0)
Attempted Execution of IRET Instruction (VME = 0)

818
CLI/STI/POPF/PUSHF Handling When VME = 1
VM86 Extensions

819
Background
When VME = 1 and IOPL = 3, Task Can Control Eflags[IF]

820
When VME = 1 and IOPL < 3, Task Controls VIF, Not IF
Eflags[VIP] Is Controlled by the VMM
Software Cannot Directly Access Eflags[VIP]
CLI Followed by a Maskable Interrupt

821

822
Subsequent STI Effect Depends on Eflags[VIP]

823

824

825
A Special Case
POPF/PUSHF Handling
Software Interrupt Instruction Handling
Software Interrupt Handling in Protected Mode

826
Software Interrupt Handling in VM86 Mode
INT3 Is Special

827

828

829
VMM Passes Control To Real Mode Handler

830

831

832
Halt Instruction in VM86 Mode
Protected Mode Virtual Interrupt Feature
General

833
1. Task executes CLI, Clears VIF
2. Maskable Interrupt Occurs and Is deferred
3. Task Executes STI

834
Registers Accessible in Real/VM86 Mode
Instructions Usable in Real/VM86 Mode

835
This Chapter
The Next Chapter

836
Introduction

Chapter 21: The MMX Facilities
837
Detecting MMX Capability
The Basic Problem
Assumptions
The Operation

838
Example: Processing One Pixel Per Iteration
Example: Processing Four Pixels Per Iteration

839

840
MMX SIMD Solution

841
Dealing with Unpacked Data

842
Dealing with Math Underflows and Overflows

843
Elimination of Conditional Branches
Introduction

844
Non-MMX Chroma-Key/Blue Screen Compositing
Example

845
MMX Chroma-Keying/Blue Screen Compositing
Example

846

847
Changes To the Programming Environment

848
Handling a Task Switch
MMX Instruction Set Syntax

849

850

851
This Chapter
The Next Chapter

852
Chapter Objectives
SSE: MMX on Steroids

Chapter 22: The SSE Facilities
853

854

855

856

857
Streaming SIMD Extensions (SSE)
The Motivation Behind SSE

858
Detecting SSE Support
The SSE Elements

859
SSE Data Types

860
The MXCSR
MXCSR Description

861

862

863
Loading and Storing the MXCSR
SIMD (Packed) Operations

864
Scalar Operations
Cache-Related Instructions

865
Overlapping Data Prefetch with Program Execution

866

867

868
Streaming Store Instructions

869

870

871

872

873
Ensuring Delivery of Writes Before Proceeding
An Example Scenario

874
SFENCE Instruction

875

876

877
Elimination of Mispredicted Branches
Background
SSE Misprediction Enhancements

878
Reciprocal and Reciprocal Square Root Operations

879
MPEG-2 Motion Compensation

880
Optimizing 3D Rasterization Performance
Optimizing Motion-Estimation Performance
Accuracy vs. Fast Real-Time 3D Processing (FTZ)

881
SSE Alignment Checking
The SIMD FP Exception
Saving and Restoring x87/MMX/SSE Registers
General

882
MXCSR Mask Field

883
OS Support for SSE
General

884
Enable SSE Instruction Sets and Register Set Save/Restore
Enable the SSE SIMD FP Exception

885
SSE Setup
Summary of the SSE Instruction Set

886

887
The SSE2 Instruction Set
General
DP FP Number Representation

888
SSE2 Packed and Scalar DP FP Instructions
SSE2 64-Bit and 128-Bit SIMD Integer Instructions

889
SSE2 128-Bit SIMD Integer Instruction Extensions
Your Choice: Accuracy or Speed (DAZ)

890
The Cache Line Flush Instruction

891
Fence Instructions
MFENCE Instruction

892

893
LFENCE Instruction

894
SFENCE Instruction
Non-Temporal Store Instructions
Introduction
MOVNTDQ Instruction

895
MOVNTPD Instruction

896
MOVNTI Instruction

897
MASKMOVDQU Instruction

898
PAUSE Instruction
Thread Synchronization

899
The Problem

900
The Fix

901
When a Thread Is Idle
Spin-Lock Optimization
Branch Hints

902
SSE3 Instruction Set
Introduction
Improved x87 FP-to-Integer Conversion Instruction
The Problem

903
The Solution
New Complex Arithmetic Instructions

904
Improved Motion Estimation Performance
The Problem

905
The Solution
The Downside

906
Instructions to Improve Processing of a Vertex
Database

907
MONITOR/MWAIT Instruction Pair
Background

908
Monitor Instruction
Mwait Instruction

909
Example Code Usage
The Wake Up Call

910
SSSE3, SSE 4.1, and 4.2

The Previous Part
This Part
The Next Part

913
This Chapter

914
The Next Chapter
The Big Picture

Chapter 23: IA-32e OS Environment
915

916
Mode Switching Overview
Booting Into Protected Mode

917
Initial Switch from IA-32 to IA-32e Mode

918

919

920
CS D and L Bits Control IA-32e SubMode Selection

921

922
Old and New Applications Running Under a 64-bit OS

923
Things You Lose In IA-32e Mode (hint: not much)
Old Applications Live in an Expanded Universe
Old Legacy Universe = 4GB or 64GB

924
IA-32e Universe Is At Least 16 Times Larger

925
Virtual Memory Addressing in IA-32e Mode
Virtual Address in Compatibility Mode

926
Virtual Address in 64-bit Mode
In Compatibility Mode, Segmentation Is Operative

927
In 64-bit Mode, Hardware-Enforced Flat Model
General
New Segment Selector Causes Descriptor Read
Segment Register Usage in 64-bit Mode

928

929

930

931

932

933

934
64-bit Mode: No Limit Checking = No Limits?

935
Table Limit Checks Are Performed
Stack Management
Stack Management in Compatibility Mode

936
Stack Management in 64-bit Mode

937
Segment Override Prefixes Other Than FS/GS Are
Ignored

938
Protection Provided by Paging
Segment Registers Preserved On Mode Switch
64-bit Instruction Pointer
Instruction Fetching

939
RIP-Relative Data Accesses
Changes To Kernel-Related Registers and Structures
Address Translation Mechanism
Basic Description

940
Top-Level Directory Placement
Detailed Description
GDT/LDT Descriptor Changes

941

942

943

944

945

946

947
GDT and GDTR Changes
GDT Descriptor Types

948

949
Executing LGDT in Compatibility Mode

950
Executing LGDT in 64-bit Mode

951
Unaligned Accesses to GDT or LDT

952
LDT and LDTR Changes
LDT Descriptor Types

953
LDTR Contents in IA-32e Mode
Unaligned Accesses to LDT

954

955
IDT/IDTR and Interrupt/Exception Changes
IDT Descriptor Types

956

957

958
Interrupt/Trap Gate Operational Changes

959

960

961

962

963
Executing LIDT in Compatibility Mode
Executing LIDT in 64-bit Mode

964
All Accesses to IDT Are Properly Aligned
IA-32e Call Gate Operation
General

965
IA-32e Call Gate Detailed Operation

966
IA-32e Call Gate Stack Switch

967

968
TR and TSS Changes
Real World TSS Usage

969

970

971

972

973
Illegal For Jump or Call To Select a TSS Descriptor
Executing LTR in Compatibility Mode

974
Executing LTR in 64-bit Mode
Revised TSS Structure

975

976
TSS Usage
Register Set Expansion (in 64-bit Mode)

977
Schedulers Software-Based Task Switching Mechanism
Switching to a 64-bit Task

978

979
Switching to a Legacy Task
General

980
Data Segment Register Initialization
CS and Instruction Pointer Initialization

981
The Switch

982

983
This Chapter

984
The Next Chapter
Theoretical Address Space Size

Chapter 24: IA-32e Address Translation
985
Limitation Imposed by Current Implementations
Four-Level Lookup Mechanism
Address Space Partitioning

986

987

988
The Address Translation
Initializing CR3
Step 1: PML4 Lookup

989

990
Step 2: PDPT Lookup

991

992
Step 3: Page Directory Lookup

993

994

995

996

997
Step 4: Page Table Lookup

998

999
Page Protection Mechanisms in IA-32e Mode
Page Protection in Compatibility Mode
Page Protection in 64-bit Mode

1000
Dont Forget the Execute Disable Feature!

1001

1002

1003

1004
TLBs Are More Important Than Ever

1005
No 4MB Page Support

1006

The Previous Part
This Part
The Next Part

1009
This Chapter

1010
The Next Chapter
Initial Entry to Compatibility Mode
Switching Between Compatibility Mode and 64-bit Mode

Chapter 25: Compatibility Mode
1011
Differences Between IA-32 Mode and Compatibility Mode
IA-32 Background
Unsupported IA-32 Features
Changes to the OS Environment

1012

1013
Memory Addressing
Segmentation

1014
FS/GS Segments
Virtual Address
Address Translation

1015
Register Set
Visible Registers

1016
No Access to Additional or Extended Registers
Control Register Accesses
Debug Register Accesses
Register Preservation Across Mode Switches

1017
Exception and Interrupt Handling
OS Kernel Calls
Call Gates

1018
Kernel Call Instruction Usage
SysEnter Instruction
SysCall Instruction

1019
Odds and Ends
IRET Changes
Segment Load Instructions

1020

The Previous Part
This Part
The Next Part

1023
This Chapter

1024
The Next Chapter
Overview of 64-bit Register Set

Chapter 26: 64-bit Register Overview
1025
EFER (Extended Features Enable) Register

1026

1027
Sixteen 64-bit Control Registers

1028

1029

1030

1031

1032

1033
64-bit Rflags Register
Sixteen 64-bit GPRs

1034

1035

1036
Kernel Data Structure Registers in 64-bit Mode

1037
SSE Register Set Expanded in 64-bit Mode

1038
Debug Breakpoint Registers

1039
Local APIC Register Set
x87 FPU/MMX Register Set
Architecturally-Defined MSRs

1040

1041
This Chapter

1042
The Next Chapter
Helpful Background
Switching to 64-bit Mode
The Defaults

Chapter 27: 64-bit Operands and Addressing
1043
The REX Prefix
Problem 1: Addressing New Registers

1044

1045
Problem 2: Using 16- and 64-bit Operands
Solution: The Rex Prefix

1046
Making Room for REX
REX Prefix Placement

1047
When You Need REX...

1048
...and when you dont

1049
Anatomy of a REX Prefix
General

1050

1051

1052
The Width Bit

1053
The Register Bit

1054

1055
The IndeX and Base Bits

1056

1057

1058
Addressing Registers Using REX[B] + Opcode[Reg]
Addressing Registers Using REX[B] + ModRM[RM]
Byte-Register Addressing Limitations

1059
Sometimes, REX Fields Have No Effect
Addressing Memory in 64-bit Mode
64-bit Mode Uses a Hardware-Enforced Flat Model
CS, DS, ES, and SS Segments Start at Virtual Address 0

1060
CS/DS/ES/SS Segment Override Prefixes Ignored
FS and GS Segments Can Start at Non-Zero Base Addresses
FS/GS Segment Override Prefixes Matter

1061
Default Virtual Address Size (and overriding it)

1062
Actual Address Size Support: Theory vs. Practice

1063
Canonical Address
General

1064
32- (and 16-) bit Addressing Limited to Lower 4GB

1065
Memory-based Operand Address Computation

1066

1067

1068

1069
RIP-relative Data Addressing

1070
Near and Far Branch Addressing

1071

1072

1073
Immediate Data Values in 64-bit Mode

1074
Displacements in 64-bit Mode

1075
This Chapter

1076
The Next Chapter
New Instructions
General
SwapGS Instruction
The Problem

Chapter 28: 64-bit Odds and Ends
1077
The SwapGS Solution

1078
MOVSXD Instruction: Stretch It Out
Enhanced Instructions

1079
Invalid Instructions

1080

1081
Reassigned Instructions
LAHF/SAHF Instruction Support

1082
Instructions That Default to a 64-bit Operand Size
Stack Operations

1083
Near Branches
Branching in 64-bit Mode
Short/Near Branches Default to 64-bit Operand Size

1084
Unconditional Jumps in 64-bit Mode

1085

1086

1087
Calls/Ret/Iret in 64-bit Mode
Instruction Forms in 64-bit Mode

1088

1089
Example Call/Return Operations

1090

1091

1092

1093
Conditional Branches in 64-bit Mode

1094

1095

1096

1097
NOP Instruction
FXSAVE/FXRSTOR
General
Fast FxSave/Restore Feature (AMD-only)

1098

1099

1100

1101
The Nested Task Bit (Rflags[NT])

1102
SMM Save Area
IA-32 Processor SM Save Area

1103

1104

1105

1106
Intel 64 Processor SM Save Area

1107

1108

1109

1110

The Previous Part
This Part
The Next Part

1113
This Chapter
The Next Chapter

1114
Real Mode Peculiarities That Affect the OS Boot Process
Example OS Characteristics

Chapter 29: Transitioning to Protected Mode
1115
Flat Model With Paging
Software-Based Task Switching

1116
Protected Mode Transition Primer
GDT Must Be In Place Before Switch to Protected
Mode

1117

1118

1119
No Interrupts or Exceptions During Mode Switch

1120
Creation of Protected Mode IDT

1121
Other Protected Mode Structures
TSS

1122
Address Translation Mechanism

1123

1124
Optional Structure: LDT

1125
Enable A20 Gate
Load Initial Code and Handlers Into Memory
The Switch to Protected Mode
Loading Segment Registers With GDT Descriptors

1126

1127
Load TSS Descriptor Into TR
Enable Interrupts

1128
Load Application Into Memory
Create Tasks Address Translation Tables
Switching From OS Scheduler to First Task
Example: Linux Startup

1129
1. Bootsect
2. Setup

1130

1131
3a. Startup_32 in boot/compressed/head.s

1132
3b. Startup_32 in kernel/head.s

1133

1134

1135

1136

1137

1138

1139
This Chapter
The Next Chapter

1140
No Need to Linger in Protected Mode
Entering Compatibility Mode

Chapter 30: Transitioning to IA-32e Mode
1141

1142
Switch to 64-bit Mode

Chapter 30: Transitioning to IA-32e Mode
1143

1144

The Previous Part
This Part

1147
This Chapter

1148
The Next Chapter
Just an Introduction?
Detailed Coverage of Virtualization

Chapter 31: Introduction to Virtualization Technology
1149
The Intel Model
OS: I Am the God of All Things!

1150
Virtualization Supervisor: Sure You Are (:<)
Root versus Non-Root Mode

1151
Detecting VMX Capability

1152
Entering/Exiting VMX Mode
Entering VMX Mode
Exiting VMX Mode

1153
Virtualization Elements/Terminology

1154
Introduction to the VT Instructions

1155

1156
Introduction to the VMCS Data Structure

1157

1158

1159

1160
Preparing to Launch a Guest OS

1161
Launching a Guest OS

1162
Guest OS Suspension

1163
Handling Timeslice Expiration
Handling a Sensitive Operation or a VMCALL
Resuming a Guest OS

1164

1165
Some Warnings Regarding VMCS Accesses

1166

1167
This Chapter

1168
The Next Chapter
What Falls Under the Heading of System Management?

Chapter 32: System Management Mode (SMM)
1169
The Genesis of SMM

1170
SMM Has Its Own Private Memory Space
The Basic Elements of SMM

1171
A Very Simple Example Scenario
How the Processor Knows the SM Memory Start Address

1172
Normal Operation, (Including Paging) Is Disabled
The Organization of SM RAM
General

1173
IA-32 Processor SM State Save Area

1174

1175

1176

1177

1178
Intel 64 Processor SM Save Area

1179

1180

1181

1182
Protecting Access to SM Memory

1183
Entering SMM
The SMI Interrupt Is Generated
No Interruptions Please
General

1184
Exceptions and Software Interrupts Permitted but Not
Recommended
Servicing Maskable Interrupts While in the Handler
Single-Stepping through the SM Handler

1185
If Interrupts/Exceptions Permitted, Build an IDT
SMM Uses Real Mode Address Formation

1186
NMI Handling While in SMM

1187

1188
Informing the Chipset SM Mode Has Been Entered
General
A Note Concerning Memory-Mapped IO Ports
The Context Save
General

1189
Although Saved, Some Register Images Are Forbidden
Territory
Special Actions Required on a Request for Power Down

1190
The Register Settings on Initiation of the SM Handler

1191
The SMM Revision ID

1192
The Body of the Handler
Exiting SMM
The Resume Instruction

1193
Informing the Chipset That SMM Has Been Exited
The Auto Halt Restart Feature

1194
Executing the HLT Instruction in the SM Handler

1195
The IO Instruction Restart Feature
Introduction
An Example Scenario
The Detail

1196
Back-to-Back SMIs During IO Instruction Restart
Multiprocessor System Presents a Problem

1197

1198
Caching from SM Memory
Background

1199
The Physical Mapping of SM RAM Accesses

1200

1201

1202

1203
FLUSH# and SMI#
Setting Up the SMI Handler in SM Memory

1204
Relocating the SM RAM Base Address
Description
In an MP System, Each Processor Must Have a
Separate State Save Area

1205
Accessing SM Memory Above the First MB
SMM in an MP System
SM Mode and Virtualization

1206

1207
This Chapter

1208
The Next Chapter

Chapter 33: Machine Check Architecture (MCA)
1209
Why This Subject Is Included
MCA = Hardware Error Logging Capability

1210
The MCA Elements
The Machine Check Exception

1211
The MCA Register Set

1212
The Global Registers
Introduction
The Global Count and Present Register

1213
The Global Status Register

1214
The Global Control Register
The Extended MC State MSRs

1215

1216

1217
The Composition of a Register Bank
Overview
The Bank Control Register
General

1218
P6 and Core Processors
The Bank Status Register
General

1219

1220
Error Valid Bit
Overflow Bit

1221
Uncorrectable Error Bit
Error Enabled Bit
Miscellaneous Register Valid Bit
Address Register Valid Bit

1222
Processor Context Corrupt Bit
MCA Error Code and Model Specific Error Code
Other Information
The Bank Address Register
The Bank Miscellaneous Register
Control 2 Register

1223
The Error Code
The Error Code Fields
Simple MCA Error Codes

1224
Compound MCA Error Codes
General

1225
Correction Report Filtering Bit

1226

1227

1228

1229
Example External Interface Error Interpretation

1230

1231

1232
Cache Error Reporting
Green/Yellow Cache Health Indicator
Background
TES (Threshold Error Status) Feature

1233
Interrupt On Soft Error Threshold Match
Before CMCI, Soft Error Logging Required Periodic Scan

1234
CMCI Eliminates MC Register Scan

1235
Determining Processors CMCI Support
Determining a Banks CMCI Support
CMCI Interrupt Is Separate and Distinct From MC Exception
CMC Interrupt May Affect Multiple Cores/Logical Processors
CMC Interrupt Should Only Be Serviced Once

1236
MC Exception Is Generally Not Recoverable

1237
Machine Check and BINIT#
Additional Error Logging Notes
Error Buffering Capability
Additional Information for Each Log Entry

1238

1239
This Chapter

1240
APIC and the IA-32 Architecture

Chapter 34: The Local and IO APICs
1241
Definition of IO and Local APICs
Hardware Context Is Essential
A Short History of the APICs Evolution
APIC Introduction
Pentium Pro APIC Enhancements

1242
The Pentium II and Pentium III
Pentium 4 APIC Enhancements: xAPIC

1243
The x2APIC Architecture

1244
Before the APIC

1245

1246
MP Systems Need a Better Interrupt Distribution
Mechanism
Legacy Interrupt Delivery System Is Inefficient

1247

1248
The APIC Interrupt Distribution Mechanism
Introduction

1249
Message Types

1250
Message Transfer Mechanism Prior to the Pentium 4
Message Transfer Mechanism Starting with the Pentium 4

1251
Message Transfer Mechanism in Intel QPI-based Systems

1252

1253
Processors Reside in Clusters

1254
Each Core/Logical Processor Has a Dedicated Local APIC
Introduction to the Message Addressing Modes

1255
Detecting Presence/Version/Capabilities of Local APIC
Presence
Version

1256
x2APIC Capability Verification
Local APICs Initial State

1257
Enabling/Disabling the Local APIC
General
Disabling Local APIC for Remainder of Power-Up
Session

1258
Dynamically Enabling/Disabling Local APIC

1259

1260
Mode Selection

1261
The Local APIC Register Set
Register Access in xAPIC Mode: MMIO
General
Local and IO APIC xAPIC Register Areas Are Uncacheable
xAPIC Register Access Alignment

1262
Register Access in x2APIC Mode: MSR
Introduction to the Local APICs Register Set

1263

1264

1265

1266

1267

1268

1269

1270

1271

1272

1273

1274

1275

1276

1277
Local APIC ID Assignments and Addressing
ID Assignment in xAPIC Mode
Introduction
Cluster ID Assignment

1278
Physical/Logical Processor and Local APIC ID Assignment

1279

1280

1281
xAPIC ID Register

1282
BIOS/OS Reassignment of xAPIC ID
Logical xAPIC Address Assignment
Maximum Number of xAPICs

1283
ID Assignment in x2APIC Mode
Two Hardware-Assigned Local APIC IDs
x2APIC ID (Physical Local APIC ID)

1284

1285
Logical x2APIC ID

1286

1287
Local APIC Addressing
Physical Addressing: Single Target

1288
Logical Addressing: Multiple Targets

1289

1290

1291

1292
Message Addressing Summary

1293

1294
Lowest-Priority Delivery Mode

1295
General
Warnings Related to Lowest-Priority Delivery Mode

1296
Chipset-Assisted Lowest-Priority Delivery

1297
Local APIC IDs Are Stored in the MP and ACPI Tables

1298
Accessing the Local APIC ID
An Introduction to the Interrupt Sources
Local Interrupts

1299
Remote Interrupt Sources

1300
Introduction to Interrupt Priority
General

1301
Definition of a User-Defined Interrupt

1302
User-Defined Interrupt Priority

1303

1304

1305
Definition of Fixed Interrupts
Masking User-Defined Interrupts
Task and Processor Priority
Introduction

1306
The Task Priority Register (TPR)
The Processor Priority Register (PPR)

1307
The User-Defined Interrupt Eligibility Test

1308
CR8 (Alternative TPR)

1309
Interrupt Message Format

1310

1311

1312

1313
IO/Local APICs Cooperate on Interrupt Handling
The Purpose of the IO APIC

1314

1315

1316
Overview of Edge-Triggered Interrupt Handling
Assumptions
Description

1317

1318

1319

1320

1321
Overview of Level-Sensitive Interrupt Handling
Assumptions

1322
Description

1323

1324

1325

1326
Higher-Priority Fixed Interrupt Preempts Handler

1327

1328

1329

1330

1331
IO APIC Register Set
IO APIC Register Set Base Address

1332
IO APIC Register Set Description

1333

1334

1335
IRQ Pin Assertion Register

1336
IO APIC EOI Register and Shared Interrupts

1337

1338

1339

1340
IO APIC ID Register
IO APIC Version Register

1341
IO APIC Redirection Table (RT) Register Set

1342

1343

1344
IO APIC Interrupt Delivery Order Is Rotational

1345
Message Signaled Interrupts (MSI)
General

1346
Using the IO APIC as a Surrogate Message Sender
Direct-Delivery of an MSI

1347
Memory Already Syncd When Interrupt Handler
Entered
The Problem
Old Solution

1348
How MSI Solves the Problem
Interrupt Delivery from Legacy 8259a Interrupt Controller
Virtual Wire Mode A

1349

1350
Virtual Wire Mode B

1351
SW-Initiated Interrupt Message Transmission
Introduction

1352

1353
Sending a Message From the Local APIC
ICR in xAPIC Mode
ICR in x2APIC Mode

1354

1355

1356

1357

1358

1359
x2APIC Modes Self IPI Feature

1360
Locally Generated Interrupts
Introduction
The Local Vector Table

1361
The Pentium Familys LVT
The P6 Familys LVT
The Pentium 4 Familys LVT
Core Processors LVT

1362
LVT Register State After Reset, INIT, or Software
Disable
Local Interrupt 0 (LINT0)
The Mask Bit
The Trigger Mode and the Input Pin Polarity

1363
The Delivery Mode

1364
The Vector Field

1365
The Remote IRR Bit
The Delivery Status
Local Interrupt 1 (LINT1)

1366
The Local APIC Timer
General

1367
The Divide Configuration Register
One Shot Mode
Periodic Mode

1368
The Performance Counter Overflow Interrupt

1369

1370
The Thermal Sensor Interrupt

1371

1372
Correctable Machine Check (CMC) Interrupt

1373
The Local APICs Error Interrupt
Local APIC Error LVT Register
Error Status Register (ESR) Operation in xAPIC Mode
Error Status Register Operation in x2APIC Mode

1374

1375

1376
The Spurious Interrupt Vector
The Problem
Solution

1377
Additional Spurious Vector Register Features

1378
Boot Strap Processor (BSP) Selection
Introduction

1379
The BSP Selection Process
Pre-QPI BSP Selection Process

1380

1381
Intel QPI BSP Selection Process
How the APs are Discovered and Configured

1382
AP Detection and Configuration
Introduction
BIOS AP Discovery Procedure

1383

1384
Uni-Processor OS and the APs
MP OS and the APs

1385

1386

1387
The FindAndInitAllCPUs Routine

1388

1389

1390

Glossary of Terms
1391

1392

Glossary of Terms
1393

1394

Glossary of Terms
1395

1396

Glossary of Terms
1397

1398

Glossary of Terms
1399

1400

Glossary of Terms
1401

1402

Glossary of Terms
1403

1404

Glossary of Terms
1405

1406

Glossary of Terms
1407

1408

Glossary of Terms
1409

1410

Glossary of Terms
1411

1412

Glossary of Terms
1413

1414

Glossary of Terms
1415

1416

Glossary of Terms
1417

1418

Glossary of Terms
1419

1420

Glossary of Terms
1421

1422

Glossary of Terms
1423

1424

Glossary of Terms
1425

1426

Glossary of Terms
1427

1428

Glossary of Terms
1429

1430

Glossary of Terms
1431

1432

Glossary of Terms
1433

1434

Glossary of Terms
1435

1436

Glossary of Terms
1437

1438

Glossary of Terms
1439

1440

Glossary of Terms
1441

1442

Glossary of Terms
1443

1444

Glossary of Terms
1445

1446

Glossary of Terms
1447

1448

Glossary of Terms
1449

1450

Glossary of Terms
1451

1452

Glossary of Terms
1453

1454

Glossary of Terms
1455

1456

Glossary of Terms
1457

1458

Glossary of Terms
1459

1460

Glossary of Terms
1461

1462

Glossary of Terms
1463

1464

Glossary of Terms
1465

1466

Glossary of Terms
1467

1468

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