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Design and Implementation of Virtual Channel Router Architecture on FPGA for NoCs
DEPT. OF E&C, DBIT MTECH, VLSI & ES, 3
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INTRODUCTION
Network-on-Chip technology is already being adopted in the majority of large SoCs for
simplifying system integration at the IP-assembly functional verication level all the
way down to physical integration - by alleviating physical routing congestion and
simplifying timing closure. NoCs also improve performance by parallelizing
communication, offer quality-of-service (QoS) guarantees, and enable exible system
partitioning. The majority of these NoC features can be satised by the use of virtual
channels (VCs). A physical channel can be used in a time-multiplexed manner by
different VCs, provided that each VC owns a separate buffer space. VC-based
architectures enable trafc separation and isolation by assigning different trafc classes to
different VCs, and they reduce on-chip physical routing congestion by trading off
physical channel width and the number of supported VCs, thus, creating a more layout-
exible SoC architecture. The NoC needs to be both scalable, in terms of network
functionality and performance, as well as exible in terms of physical implementation.
This requirement motivates us to unify a VC-based architecture that favors NoC
scalability with elastic buffering, which eases physical implementation and promises area
and power reduction.
The main purpose SoC system is to shrink the size of the chip as smaller as
possible while seeking at the same time for more scalability, lower latency and higher
bandwidth. Conventional bus-based-systems are no longer reliable architecture for SoC
due to a lack of scalability and parallelism integration, high latency and power
dissipation, and low throughput. In the forthcoming era scalable global on-chip
communications represent the only solution for many-core computing networks- on-chips
(NoCs).Networks-on-Chip (NoC), architectures are becoming the network fabric for both
general-purpose chip multi-processors and application-specific systems-on-chip designs.
In the design of NoCs, lower area and lower power overhead are both important design
parameters and the router microarchitecture plays a vital role in achieving these
performance goals. NoC connects CPU, DRAM, SRAM and DMA other custom designs
together using switching packets instead of switching messages or words, allowing NoC
to provide a higher performance and higher bandwidth. On the other hand, the need for a
high performance system that handles increased complexity becomes really important.
A typical NoC consists of computational processing elements (PEs), network
interfaces (NIs), and routers. The NI is used to packetize data before using the router
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Design and Implementation of Virtual Channel Router Architecture on FPGA for NoCs
DEPT. OF E&C, DBIT MTECH, VLSI & ES, 3
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backbone to traverse the NoC. Each PE is attached to an NI which connects the PE to a
local router. When a packet was sent from a source PE to a destination PE, the packet is
forwarded hop by hop on the network via the decision made by each router. For each
router, the packet is first received and stored at an input buffer. Then the control logics in
the router are responsible to make routing decision and channel arbitration. Finally, the
granted packet will traverse through a crossbar to the next router, and the process repeats
until the packet arrives at its destination.
Basic Virtual Channel Router Architecture:

Figure 1: Basic Virtual Channel Router Architecture.
As Figure 1 illustrates, a basic virtual-channel router mainly consists of the following
components: input port, routing unit, virtual channel allocator, switch allocator, crossbar
and output port. Packets are received by input ports, and then they are cached into virtual-
channel buffers according to their virtual-channel ID (VCID). Each virtual channel
associates with a single buffer. Routing unit gets routing information (source node
address, destination node address, etc.) from the buffered packets, and calculates an
appropriate output port for each packet. Once the routing computation is done, virtual-
channel allocator will allocate a free output virtual channel to the packet. Crossbar acts as
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Design and Implementation of Virtual Channel Router Architecture on FPGA for NoCs
DEPT. OF E&C, DBIT MTECH, VLSI & ES, 3
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a switching element. It fulfills data exchange in the virtual channel router. Switch
allocator controls the connection status of the crossbar, and allocate a time slot to each
data flit to transmit through the crossbar. Finally, all the packets are ejected from output
port to next router or local IP core.
In virtual channel router, several virtual-channels are associated with one physical
channel. They are allocated independently and compete with each other for total physical
bandwidth. Since virtual channels decouple buffer resources from transmission resources,
network congestion and packet delay can be reduced significantly in virtual-channel
router. When Network-on-Chip adopts adaptive routing, virtual channel can also be used
to ensure deadlock freedom. But for virtual- channel router, each virtual channel is
associated with a single buffer, increasing virtual channel means increasing buffer space.
Virtual-channel router should take a better tradeoff between Network-on-Chip
performance and implementation cost.
LITERATURE SURVEY
1. Mamta P. Daf; Bharati B. Sayankar; Performance and Evaluation of Loopback
Virtual Channel Router with Heterogeneous Router for On Chip Network, Fourth
International Conference on Communication Systems and Network Technologies,
2014.
Network on Chip (NOC) is an important communication infrastructure for
system on chips (SOC). Router is most important parameter of the NOC. Area
and performance both play a vital role in network on chip (NOC) architecture. In
this paper we implement the loop back virtual channel router by comparing the
look - ahead speculative virtual channel and baseline router architecture. In this
implemented loopback virtual channel router, if there is a request to a busy buffer,
the router will store incoming packet in any other suitable free buffer in the router.
This router will be complete a lookback operation before entering a wait state.
2. Seitanidis, I; Psarras, A; Dimitrakopoulos, G.; Nicopoulos, C., "ElastiStore: An
elastic buffer architecture for Network-on-Chip routers," Design, Automation and
Test in Europe Conference and Exhibition (DATE), 2014.
The design of scalable Network-on-Chip (NoC) architectures calls for new
implementations that achieve high-throughput and low-latency operation, without
exceeding the stringent area-energy constraints of modern Systems-on-Chip
(SoC). The router's buffer architecture is a critical design aspect that affects both
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Design and Implementation of Virtual Channel Router Architecture on FPGA for NoCs
DEPT. OF E&C, DBIT MTECH, VLSI & ES, 3
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network-wide performance and implementation characteristics. In this paper, we
extend Elastic Buffer (EB) architectures to support multiple Virtual Channels
(VC) and we derive ElastiStore, a novel lightweight elastic buffer architecture that
minimizes buffering requirements, without sacrificing performance. The
integration of the proposed elastic buffering scheme in the NoC router enables the
design of new router architectures - both single-cycle and two-stage pipelined -
which offer the same performance as baseline VC-based routers, albeit at a
significantly lower area/power cost.
3. Young Jin Yoon; Concer, N.; Petracca, M.; Carloni, L.P., "Virtual Channels and
Multiple Physical Networks: Two Alternatives to Improve NoC
Performance," Computer-Aided Design of Integrated Circuits and Systems, IEEE
Transactions on, 2013.
Virtual channels (VC) and multiple physical (MP) networks are two
alternative methods to provide better performance, support quality-of-service, and
avoid protocol deadlocks in packet-switched network-on-chip design. Since
contention can be dynamically resolved, VCs give lower zero-load packet latency
than MPs; however, MPs can be built with simpler routers and narrower channels,
which improve the target clock frequency, power dissipation, and area occupation.
4. Kwa, J.; Aamodt, T.M., "Small virtual channel routers on FPGAs through block
RAM sharing," Field-Programmable Technology (FPT), 2012 International
Conference on, 2012
As larger System-on-Chip (SoC) designs are attempted on Field
Programmable Gate Arrays (FPGAs), the need for a low cost and high
performance Network-on-Chip (NoC) grows. Virtual Channel (VC) routers
provide desirable traits for an NoC such as higher throughput and deadlock
prevention but at significant resource cost when implemented on an FPGA. This
paper presents an FPGA specific optimization to reduce resource utilization.
5. Latif, K.; Seceleanu, T.; Tenhunen, H., "Power and Area Efficient Design of
Network-on-Chip Router through Utilization of Idle Buffers," Engineering of
Computer Based Systems (ECBS), 2010 17th IEEE International Conference and
Workshops on.
Network-on-Chip (NoC) is the interconnection platform that answers the
requirements of the modern on-Chip design. Small optimizations in NoC router
architecture can show a significant improvement in the overall performance of
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Design and Implementation of Virtual Channel Router Architecture on FPGA for NoCs
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NoC based systems. Power consumption, area overhead and the entire NoC
performance is influenced by the router buffers. Resource sharing for on-chip
network is critical to reduce the chip area and power consumption. Virtual channel
buffer sharing by other router ports has been proposed to enhance the performance
of on-chip communication. We approach the router architecture optimization by
utilizing the idle buffers instead of increasing the number and size of buffers for
desired throughput.
6. Feiyang Liu; Huaxi Gu; Yintang Yang, "Performance study of virtual-channel
router for Network-on-Chip," Computer Design and Applications (ICCDA), 2010
International Conference on.
Network-on-Chip (NoC) overcomes the main constraints of traditional
bus-based System-on-Chip (SoC). It introduces the principle of interconnection
network into SoC design. Router is the main component of NoC and determines
performance to a large extend. Virtual-channel router is one of the promising
router architectures for Network-on-Chip, for its low delay and high network
throughput.
7. Nicopoulos, C.A; Dongkook Park; Jongman Kim; Vijaykrishnan, N.; Yousif,
M.S.; Das, C.R., "ViChaR: A Dynamic Virtual Channel Regulator for Network-
on-Chip Routers," Microarchitecture, 2006. MICRO-39. 39th Annual IEEE/ACM
International Symposium on.
The advent of deep sub-micron technology has recently highlighted the
criticality of the on-chip interconnects. As diminishing feature sizes have led to
increases in global wiring delays, network-on-chip (NoC) architectures are viewed
as a possible solution to the wiring challenge and have recently crystallized into a
significant research thrust. Both NoC performance and energy budget depend
heavily on the routers' buffer resources. This paper introduces a novel unified
buffer structure, called the dynamic virtual channel regulator (ViChaR), which
dynamically allocates virtual channels (VC) and buffer resources according to
network traffic conditions. ViChaR maximizes throughput by dispensing a
variable number of VCs on demand.
8. Mullins, R.; West, A; Moore, S., "The design and implementation of a low-
latency on-chip network," Design Automation, 2006. Asia and South Pacific
Conference on.
Many of the issues that will be faced by the designers of multi-billion
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Design and Implementation of Virtual Channel Router Architecture on FPGA for NoCs
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transistor chips may be alleviated by the presence of a flexible global
communication infrastructure. In the short term, such a network will provide
scalable chip-wide communication and ease the complexity of handling multi-
cycle communications. In the long term, the network will become a primary tool
for optimising power and data transfers and for scheduling computations. This
paper details the design and implementation of a low-latency on-chip network.
The network's speculative routers are in the best case able to route flits in a single
clock cycle, helping to minimise on-chip communication latencies and maximise
the effectiveness of buffering resources.
9. Kavaldjiev, N.; Smit, G. J M; Jansen, P.G., "A virtual channel router for on-chip
networks," SOC Conference, 2004. Proceedings. IEEE International.
This paper proposes an architecture of a virtual channel router for an on-
chip network. The router has simple dynamic arbitration which is deterministic
and fair. We show that the size of the proposed router is reduced by 49% and the
speed increases 1.4 times compared to a conventional virtual channel router.
PROBLEM FORMULATION
NoCs, much like macro networks, can scale efficiently as the number of nodes (i.e.
processing elements) increases. Besides performance, current designs indicate an
additional alarming trend pertaining to the on-chip interconnects: the chip area and power
budgets are increasingly being dominated by the interconnection network.
It is known that router buffers are instrumental in the overall operation of the on-
chip network. However, of the different components comprising the interconnection
fabric of SoCs, buffers are the largest leakage power consumers in an NoC router,
consuming about 64% of the total router leakage power. Similarly, buffers consume
significant dynamic power and this consumption increases rapidly as packet flow
throughput increases. In fact, it has been observed that storing a packet in a buffer
consumes far more energy than transmitting the packet. Furthermore, the area occupied
by an on-chip router is dominated by the buffers. Consequently, buffer design plays a
crucial role in architecting high performance and energy efficient on-chip interconnects.
When a physical channel is divided in to a multiple number of logical channels.
These logical channels are called as virtual channel(VC). The concept of virtual channels
is used to create a deadlock free deterministic routing. A virtual channel has its own
queue, but it shares the bandwidth of the physical channel in a time multiplexed fashion.
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Design and Implementation of Virtual Channel Router Architecture on FPGA for NoCs
DEPT. OF E&C, DBIT MTECH, VLSI & ES, 3
RD
SEM
MOTIVATION
The NoC needs to be both scalable, in terms of network functionality and performance, as
well as exible in terms of physical implementation. This requirement motivates us to
unify a VC-based architecture that favors NoC scalability which eases physical
implementation and promises area and power reduction. The design of scalable Network-
on-Chip (NoC) architectures calls for new implementations that achieve high throughput
and low-latency operation, without exceeding the stringent area-energy constraints of
modern Systems-on-Chip (SoC). The routers buffer architecture is a critical design
aspect that affects both network-wide performance and implementation characteristics.
Virtual channel router can also be used to solve network deadlock when adopting
adaptive routing, and simultaneously provide guaranteed service and best-effort service.
Sometimes all these performances are achieved at the cost of increasing router
complexity and buffer requirement. Because Network-on-Chip is strict resource
constrained, a good virtual-channel router should make a better tradeoff between
performance and implementation cost.
OBJECTIVE OF PROJECT
To design a router that provides reduced size and high performance for low-cost FPGA
implementation. And used method should increases the overall performance of NoC
router. The main objective is to design a low power, low latency and high performance
virtual channel router architecture to be implemented on FPGA for On-Chip Networks.
METHODOLOGY
An interconnection network is characterized by its topology routing, and flow control.
The topology of a network is the arrangement of nodes and channels into a graph.
Routing specifies how a packet chooses a path in this graph. Flow Control ideals with the
allocation of channel and buffer resources to a packet as it traverses this path.
The majority of these NoC features can be satised by the use of virtual channels
(VCs). A physical channel can be used in a time-multiplexed manner by different VCs,
provided that each VC owns a separate buffer space. VC-based architectures enable
trafc separation and isolation by assigning different trafc classes to different VCs, and
they reduce on-chip physical routing congestion by trading off physical channel width
and the number of supported VCs, thus, creating a more layout-exible SoC architecture.
2014-15
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Design and Implementation of Virtual Channel Router Architecture on FPGA for NoCs
DEPT. OF E&C, DBIT MTECH, VLSI & ES, 3
RD
SEM
Virtual channel router can also be used to solve network deadlock when adopting
adaptive routing, and simultaneously provide guaranteed service and best-effort service.
Sometimes all these performances are achieved at the cost of increasing router complexity
and buffer requirement. Because Network-on-Chip is strict resource constrained, a good
virtual-channel router should make a better tradeoff between performance and
implementation cost.
EXPECTED OUTCOME OF THE PROJECT
The proposed router provides reduced size and high performance for low-cost FPGA
implementation and proposed method increases the overall performance of NoC router.
The design of the on-chip network can provide an efcient global communications
infrastructure for future gigascale ICs. A speculative architecture is able to accurately
produce datapath control signals one cycle in advance of their use. This enables both
datapath and control logic to operate concurrently providing signicant latency
improvements.