MOS capacitor operation

MOSFET or IGFET

N-channel MOS transistor

MOSFET with gate voltage zero

The gate voltage is equal to zero while the P-tpe

su!strate an" the source are groun"e"

The "rain is connecte" to a positive voltage

Since the source an" the su!strate are at the

sa#e potential there is no current $low in the
source-su!strate %unction

The "rain-su!strate %unction is reverse !iase" an"

e&cept $or a s#all negligi!le reverse lea'age
current no current $lows in that %unction either

(n"er these con"itions there is no channel

$or#ation) an" there$ore) no current $low $ro#
source to "rain*

MOSFET current vs voltage characteristics

MOS +Metal-O&i"e-
Se#icon"uctor,
-ssu#e wor' $unction o$ #etal an"
se#icon"uctor are sa#e*

MOS #aterials

The ideal two-terminal MOS structure
(V
FB
=0)
C
G s
ox
Q
V
C

ox
ox
ox
A
C
t

=
;
G ox ox
G ox
ox
Q C
Q C
A A t

= = =
A - capacitor area)
t
ox
- o&i"e thic'ness

ox
- per#ittivit o$ o&i"e
M
O
S
+

s
_
G
G s
ox
Q
V
C
=
C
Q
G
Q
0
G C
Q Q + =
G
V

Example: oxide capacitance
+a, .alculate the o&i"e capacitance per unit area $or
t
ox
/ 0 an" 12 n# assu#ing
ox
/ 3*4
0
) where
0
=
5*50672
-78
F9c# is the per#ittivit o$ $ree space* +!,
:eter#ine the area o$ a 7pF #etal-o&i"e-#etal
capacitor $or the two o&i"e thic'nesses given in
+a,*
-nswer; +a, /<42 nF9c#
1
/ <*4 $F9#
1
$or t
ox
/0 n#
an" / 7=1 nF9c#
1
/ 7*= $F9#
1
$or t
ox
/ 12 n#* The
capacitor areas are 780 an" 052 #
1

$or o&i"e
thic'nesses o$ 0 an" 12 n#) respectivel*

MOS structure

Shown is the se#icon"uctor su!strate with a thin o&i"e laer

an" a top #etal contact) also re$erre" to as the gate*

- secon" #etal laer $or#s an Oh#ic contact to the !ac' o$ the

se#icon"uctor) also re$erre" to as the !ul'*

The structure shown has a p-tpe su!strate*

>e will re$er to this as an n-type MOS capacitor since the

inversion laer contains electrons*

Structure an" principle o$ operation

To un"erstan" the "i$$erent !ias #o"es o$ an

MOS we consi"er 3 "i$$erent !ias voltages*
+7, !elow the $lat!an" voltage) V
F?

+1, !etween the $lat!an" voltage an" the

threshol" voltage) V
T
) an"

+3, larger than the threshol" voltage*

These !ias regi#es are calle" the

accumulation) depletion an" inversion #o"e
o$ operation*

Structure an" principle o$
operation

.harges in a MOS structure un"er accu#ulation)

"epletion an" inversion con"itions

Sche#atic illustration o$ a generic $iel"
e$$ect transistor

This "evice can !e

viewe" as a co#!ination
o$ two orthogonal two-
ter#inal "evices

MOS capacitor

Two-ter#inal
se#icon"uctor "evice

- #etal contact
separate" $ro# the
se#icon"uctor ! a
"ielectric insulator

(tilizes "ope" silicon as

the su!strate an" its
native o&i"e) silicon
"io&i"e) as the insulator
Silicon@silicon "io&i"e sste#)
@ the "ensit o$ sur$ace states at the o&i"e@
se#icon"uctor inter$ace is ver low co#pare" to the
tpical channel carrier "ensit in a MOSFET*
@ Insulating qualit o$ the o&i"e is quite goo"

MOS capacitor

The thic'ness o$ the o&i"e

tpicall varies !etween 0
to 02 n#

The se#icon"uctor
chosen $or the e&a#ple is
P-tpe silicon) which
correspon"s to the
su!strate o$ an n-channel
"evice

-ssu#e wor' $unctions

are sa#e

-ccu#ulation

Negative !ias is applie" to the #etal

gate while the silicon su!strate is
groun"e"
@
Structure !ehaves li'e a parallel-plate
capacitor where the two electro"es are
the silicon an" the #etal) an" the o&i"e is
the insulator !etween the#*

The application o$ the !ias gives rise

to a negative charge on the gate
@
This is a sur$ace charge in the #etal)
locate" at the #etalo&i"e inter$ace
@
-n equal charge o$ opposite sign appears
at the sur$ace o$ the silicon) at the silicon-
o&i"e inter$ace

-ccu#ulation laer

The charge in the

silicon can also !e
consi"ere" a sur$ace
charge
@
Its thic'ness is
appro&i#atel 72
nano#eters
@
This thin) hole-rich
laer is calle" an
accu#ulation laer

:epletion

S#all positive !ias is applie"

to the gate
@
Aoles near the silicon sur$ace
are repelle" ! the gate*

?ecause the acceptor "oping

ato#s cannot #ove in the
silicon lattice a negative
charge appears un"erneath
the gate o&i"e
@
Si#ilarl a positive charge o$
equal #agnitu"e can !e $oun"
in the gate electro"e) at the
#etal-o&i"e inter$ace

:epletion laer

The gate charge is a sur$ace

charge) !ut the charge in the
silicon is not

:epletion charge e&ten"s to a

non-negligi!le "epth into the
silicon

The "epth up to which holes

are repelle" is calle" the
"epletion "epth +&
"
,

Inversion

I$ a larger positive
voltage is applie" to
the gate the sur$ace
potential will continue
to increase
@
The hole concentration
near the sur$ace
"ecreases while the
electron concentration
increases) accor"ing
to the $ollowing
relationships;

Inversion laer
Electron sur$ace concentration / Aole sur$ace concentration
when E
i
coinci"es with E
F*
This happens
S
/
F
/+BT9q, ln +N
a
9n
i
,

Reions o! operation o! the MOS"ET:
#ccumulation (p-su$strate)
Holes + accumulate
in the p-type
semiconductor surface
0
0
GB FB
C
s
V V
Q

<

>
<
+ + + + + + + + + + + + + +
V
GB
G
B
- - - - - - - - - - -
+ + + +
Q
o
Q
G
Q
C

V
GB
G
B
+ + + + + + + + +
+ + + +
Q
o
Q
G
-
-
-
-
-
-
-
-
-
Q
C
-
-
-
-
-

F
= ermi potential !defined in
p-n "unction lecture i#e# $
i
-$

%
0
0
GB FB
C
s F
V V
Q

>

<
< <
%oles e&acuate !rom the '
semiconductor sur!ace and
acceptor ion chares
$ecome unco&ered
-
Reions o! operation o! the MOS"ET:
(epletion (p-su$strate)

V
GB
G
B
+ + + + + + + + +
+ + + +
Q
o
Q
G
-
-
-
-
-
-
-
-
-
Q
C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
GB FB
C
s F
V V
Q

>

<
>
electrons approach
the surface&
Reions o! operation o! the MOS"ET:
)n&ersion (p-su$strate)

Strong inversion

I$ the gate voltage is increase" $urther the

electron sur$ace concentration increases up to a
point where n(x=0) !eco#es equal to Na) which
is the original hole concentration in the su!strate
>hen
S
/1*
F
con"ition is #et se#icon"uctor is
sai" to !e in strong inversion

?an" "iagra#s in se#icon"uctor

>ea' inversion an" strong inversion

weak inversion:

b
<
s
< 2
b

Strong inversion:

s
=2
b

Flat band condition:

s
=0

Accumulation
condition:

s
< 0

Deletion:
0 <
s
<
b
T

.harges in se#icon"uctor

.harge versus !an" !en"ing9sur$ace
potential in se#icon"uctor

Threshol" voltage

There are twent in the region

I$ we want to invert the region with

@
First re#ove twent ! putting twent
@
Then put twent #ore
C
-
-
-
C
C C C C C
C C C C C
C C C C C
C C C C C
CC

Threshol" voltage

.onsi"er P tpe su!strate

Suppose ou want to invert a region in that

su!strate +two step process,
@
De#ove the holes in that region ! putting
electrons
No* o$ holes "oping concentration +E
i
-E
F
,
@
Put so#e #ore electrons in that region

Aow #an #ore electrons "oping concentration

+E
i
-E
F
,

Threshol" voltage
Threshol" voltage V / V
T
) correspon"ing to the
onset o$ the strong inversion

Strong inversion occurs when the sur$ace

potential
s
!eco#es equal to 1
b

In a MOS transistor the

gate voltage is equal to
su# o$ the potential "rops
in the se#icon"uctor an"
the o&i"e
>here
F
/+BT9q, ln +Na9ni,

Pol gate

>e have so $ar assu#e" that the Fer#i level o$

the #etal gate was equal to that o$ the silicon* In
practice this is not the case

In #o"ern "evices the gate #aterial is not an

actual #etal) !ut heavil "ope" polcrstalline
silicon) also calle" pol silicon

The "oping concentration use" $or that #aterial

is so high +72
12
9c#
3
, that it can !e consi"ere" as
a #etal) $or all practical purposes*

>or' $unction "i$$erence
Energ which is
necessar to e&tract
an electron with an
energ $ro# the
#etal is calle" the
Ewor' $unction
M
F
Si#ilarl) the wor'
$unction in the
se#icon"uctor is
note"
S.

?an" "iagra# $or p-n %unction
E
c
E
f'
E
fi
E
(
E
c
E
f)
E
fi
E
(
0
x
n
x
-x
p
-x
pc
x
nc
q
p
< 0
q
n
> 0
qV
*i
= q(
n -

p
)
*N
a
> N
d
-> |
p
|

>
n
p-type for x<0
n-type for x>0

Electron a$$init an" wor' $unction
E
o
E
c
E
f
E
i
E
(
q (electron
affinity)
q

q
(work function)
E
o
E
c
E
f
E
i
E
(
q (electron
affinity)
q

q
(work function)
' type semiconductor
* type semiconductor

MOS capacitor @ !an" "iagra#

I$ wor' $unctions are not sa#e i*e* i$ #etalGs

wor' $unction is s#aller than su!strate

S
/ H
S
C +E
.
- E
F
,

Flat !an" voltage +I
F?
,

-t zero applie" voltage) the

!en"ing o$ the energ !an"s is
i"eall "eter#ine" ! the
"i$$erence in the wor' $unctions
o$ the #etal an" the
se#icon"uctor
This !an" !en"ing changes with
the applie" !ias an" the !an"s
!eco#e $lat when we appl the
so-calle" $lat-!an" voltage +I
F?
,
I
F?
/+
M
-
S
,9q
/+
M
-H
S
- E
.
C E
F
,9q

MOS--ccu#ulation region

.harge carriers sa#e as that o$ su!strate tpe

getting accu#ulate" near Si-SIO
1
inter$ace

- MOS structure with a p-tpe se#icon"uctor

will enter the accumulation regi#e o$ operation
when the voltage applie" !etween the #etal an"
the se#icon"uctor is #ore negative than the $lat-
!an" voltage
@ I$ I
F?
is C2*0 I then accu#ulation region is !elow C2*0
I
@ I$ I
F?
is -2*10 I then accu#ulation region is !elow
-2*10 I

MOS @ "epletion region

-ssu#e MOS structure with a p-tpe su!strate

>hen V >V
F?
) the se#icon"uctor@o&i"e inter$ace
$irst !eco#es "eplete" o$ holes an" we enter the
so-calle" depletion regi#e

MOS @ inversion region
For su$$icientl larger voltages than I
F?
) we $inall
arrive at a situation in which the electron volu#e
concentration at the inter$ace e&cee"s the
"oping "ensit in the se#icon"uctor

This is the strong inversion case in which we

have a signi$icant con"ucting sheet o$ inversion
charge at the inter$ace

.harges in the o&i"e

O&i"es grown on silicon contain positive

charges "ue to the presence o$ conta#inating
#etallic ions or i#per$ect Si-O !on"s

These charges can either !e $i&e" or #o!ile in

the o&i"e

Mo!ile ions such as so"iu# an" potassiu# can

#ove in the presence o$ an electric $iel" i$ the
te#perature is high enough

.harges in the o&i"e

.onsi"er an ele#entar
positive charge +J, at a
"epth x in the o&i"e)
where x=0 is now "e$ine"
at the #etal9o&i"e
inter$ace

To insure charge
neutralit negative
charges will appear in the
#etal an" the silicon

The su# o$ these three

charges is equal to zero

.harges in the o&i"e

The charge in the

silicon can !e re#ove"
i$ an appropriate
negative voltage is
applie" to the gate

I$ the charge is closer to

the se#icon"uctor a
larger co#pensation
!ias on the gate is
require" to re#ove the
charge in the
se#icon"uctor

Inter$ace traps
Presence o$ Si-SiO
1
inter$ace at the silicon sur$ace
intro"uces pertur!ation to the perio"ic crstal
structure o$ the se#icon"uctor
@
.auses so#e Si-Si !on"s to !e un$ul$ille" or E"anglingE

-s a result there are energ states in the !an" gap

at the silicon sur$ace
@
These states are calle" Einter$ace statesE or Einter$ace
trapsK

The can !e charge" positivel or negativel)

"epen"ing on their nature an" their energ with
respect to the Fer#i level) an" thus) will a$$ect the
sur$ace potential

To co#pensate $or these charges) a !ias #ust !e

applie" to the gate

Flat !an" voltage-non i"ealities

Non i"ealities
@
>or' $unction "i$$erence
@
.harge in the o&i"e
@
Inter$ace states

Threshol" voltage

The $lat-!an" voltage #ust !e a""e" to the

e&pression $or the threshol" voltage calculate"
previousl in or"er to accuratel "escri!e the
actual) Enon-i"ealE threshol" voltage

:epletion an" enhance#ent "evices
Threshol" voltage +I
TA
, can !e either positive or
negative) "epen"ing on
@ :oping concentration +N
a
,
@
Material use" to $or# the gate electro"e) etc

For a n-channel MOSFET i$ the threshol"

voltage is
@
negative - "epletion-#o"e "evice
@
positive) the "evice is an enhance#ent-#o"e "evice

.ontrolling I
TA

:epletion-#o"e "evices will have an inversion

laer when the gate voltage is equal to zero
@
These "evices are so#eti#es re$erre" to as Enor#all
onE*

Enhance#ent-#o"e "evices require an applie"

positive gate voltage to create the inversion
laer
@
The are so#eti#es calle" Enor#all o$$E
I
TA
can !e a"%uste" ! intro"ucing a controlle"
a#ount o$ "oping i#purities in the channel
region "uring "evice $a!rication

MOS capacitance

In a MOS capacitor) the #etal contact an" the

neutral region in the "ope" se#icon"uctor
su!strate are separate" ! the insulator laer)
the channel) an" the "epletion region
.apacitance C
#os
o$ the MOS structure can !e
represente" as a series connection o$ the
insulator capacitance C
i
/ S
i
/d
i
) where S is the
area o$ the MOS capacitor) an" the capacitance
o$ the active se#icon"uctor laer C
s

Measuring capacitance
:. !ias
low-$requenc
ac signal

.apacitance in accu#ulation

>hen the gate voltage

is negative an
accu#ulation laer is
present

-s the gate voltage

varies a correspon"ing
variation o$ the
accu#ulation charge
occurs) an" the
capacitance o$ the
structure is equal to .
o&
area Farad C
t
C
OX
OX
OX
! =

.apacitance is
in"epen"ent
o$ gate voltage

.apacitance in "epletion

>hen the gate voltage is

increase" the silicon
sur$ace !eco#es
"eplete") an" the
variations o$ gate voltage
in"uce variations o$ the
"epletion charge

The value o$ the

capacitance is then
given ! the series
co#!ination o$ the gate
an" "epletion region
capacitances
.apacitance "ecreases
with gate voltage

.apacitance in inversion

-s the gate voltage is $urther increase" an

inversion laer is $or#e" an" variations o$ gate
voltage give rise to variations o$ inversion charge
an" thus the #easure capacitance is again
equal to .
OH
area Farad C
t
C
OX
OX
OX
! =

.apacitance is
in"epen"ent
o$ gate voltage

MOS capacitor @ capacitance as a $unction
o$ gate !ias

S#all-signal equivalent circuit o$ the MOS
capacitor

Main appro&i#ation $or co#pact MOS
#o"eling; the charge-sheet #o"el
Minorit carriers occup a zero-thicne!! laer at
the Si-SiO1 inter$ace

+E
F
-E
i
, $actor

Positive $or n tpe)

negative $or p tpe
an" zero $or intrinsic

In other wor"s)
@ i$ +E
F
-E
i
, is positive
then in that region we
have #ore no* o$
electrons
@ i$ +E
F
-E
i
, is negative
then in that region we
have #ore no* o$ holes
@ I$ E
F
/E
i
) then no) o$
holes / no* o$
electrons

>ea' inversion an" strong inversion

weak inversion:

b
<
s
< 2
b

Strong inversion:

s
=2
b

Flat band condition:

s
=0

Accumulation
condition:

s
< 0

Deletion:
0 <
s
<
b
T