270 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO.

1, JANUARY 2014
Digital Controller Design for Low Source Current
Ripple Fifth-Order Boost Converter
Mummadi Veerachary, Senior Member, IEEE
AbstractIn this paper, a new fth-order boost point of load
converter is proposed, and then, a digital controller is designed
using a Tchebyshev polynomial approach. The proposed converter
has a reduced source ripple current together with a better boost-
ing capability at lower duty ratios. Discrete-time models of the
converter are formulated and then used in the identication of
the direct digital controller stabilizing region. These discrete-time
transfer functions are transformed into a Tchebyshev represen-
tation, consisting of converter control-to-output and controller
transfer functions, which are then used to ascertain the existence
of a stabilizing controller, and if stabilization is possible, then the
entire set of gains is constructively determined. Using this method,
the controller gain range is obtained as a set of inequalities in two
variables for a xed third variable. By sweeping the third variable
over its entire range, the complete stabilizing sets are obtained.
Within these ranges, the optimal digital controller parameters
are obtained through a constrained optimization problem using
a genetic algorithm. An integral time absolute error performance
index is used in the optimization. A 30-W, 12- to 28-V, and 100-kHz
laboratory prototype closed-loop converter has been developed
and then tested, both as a simulation and experimentally, for its
voltage regulation capability against source and load perturba-
tions. Both the simulated and experimental results conrm the
effectiveness of the proposed design.
Index TermsDCDC converter, digital controller, discrete-
time model, fth-order boost converter, integral time absolute
error (ITAE), integral of time multiplied by the squared error
(ITSE), point of load converter (POLC), ripple current, stabilizing
region, Tchebyshev polynomial.
LIST OF SYMBOLS
[A
j
], [B
j
], [E
j
] Matrices of state-space model.
C
k
(u), S
k
(u) Tchebyshev polynomials.
C

Circle of radius .

d Small-signal perturbation in duty ratio.

(z) Characteristic polynomial in z-domain.
R(u, ), T(u, ) Real and imaginary parts of Q(z) Tcheby-
shev polynomial.
G
c
(z) Digital controller.
Manuscript received July 29, 2012; revised December 18, 2012; accepted
February 14, 2013. Date of publication February 22, 2013; date of current
version July 18, 2013. This work was supported in part by the Department
of Science and Technology, Government of India, through Research and
Development Project (Design and development of robust stabilizing digital
controllers for power electronic systems used in smart dc-grid applications)
under Grant SR/S3/EECE/0094/2010.
The author is with the Department of Electrical Engineering, Indian In-
stitute of Technology Delhi, New Delhi-110 016, India (e-mail: mvchary@
ee.iitd.ac.in).
Color versions of one or more of the gures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identier 10.1109/TIE.2013.2248336
n Order of polynomial.
P(z) z-domain polynomial.
k
1
, k
2
, k
3
, k
4
Digital controller coefcients.
State-transition matrix.
X Steady-state solution of state model.
x[n] Small-signal perturbation in x[n] at nth
sampling time.
I. INTRODUCTION
T
HE requirement for high-frequency power conversion
through low-power compact electronic circuits has in-
creased in recent years. As power conversion systems become
increasingly miniaturized, increasing the power density in the
point of load converters is one of the challenging issues facing
the power supply designers. One option in switch-mode con-
version [1][4] is to reduce the size of the magnetic elements,
if possible, avoiding the use of transformers wherever isolation
is not required and, more importantly, reducing the electro-
magnetic interference (EMI). Light weight units of a small
size and high power density are currently feasible through use
of high-frequency switching. Several different kinds of power
circuit topologies have been reported in the literature to drive
the loads, and they can be broadly classied into buck, boost,
and buckboost topologies. These basic converters or their
derivatives have applications in several different areas such
as the following: 1) powering miniaturized integrated circuits;
2) automotive electronics and power supplies; 3) defense and
telecoms applications; and 4) internet services (local and wide
area networks, etc.).
Boost-based topologies and their derivatives have a wide
range of applications in front-end circuits. However, the simple
boost converter requires a larger load capacitor in order to
maintain the desired load voltage ripple, and draws a high
inrush current at the time of starting. Sometimes, a load capac-
itor alone is unsuitable in providing the desired load voltage
ripple and meeting the imposed EMI requirements. In order
to eliminate some of these limitations, coupled inductor boost
converters and quadratic or higher order topologies have been
proposed in the literature [5][8]. However, a major limitation
of these topologies is device stress. Higher voltage gains can
be easily realized by means of higher order topologies, which
are essentially formulated by merging different circuit com-
binations into a single conguration. Although these may be
suitable from a voltage gain point of view, they exhibit lower
efciency on account of a greater number of switching devices.
To overcome some of these limitations, research is in progress
0278-0046/$31.00 2013 IEEE
VEERACHARY: DIGITAL CONTROLLER DESIGN FOR FIFTH-ORDER BOOST CONVERTER 271
on developing nonisolated single-switch topologies and their
control [6][15], showing that it is possible to obtain a high
static gain, together with improved steady-state and dynamic
performance. A fourth-order boost converter (FOBC) for load
voltage regulation purposes has been documented [7], and a
fth-order boost converter and a robust digital controller design
have been also presented [8]. Although these topologies are ca-
pable of boosting the source voltages, their boosting capability
in the low duty ratio range (D < 0.5) is limited, whereas the
high duty ratio operation yields lower efciency. Furthermore,
in both the fourth- and fth-order topologies, the source current
ripple is high. To overcome some of these shortcomings, a new
fth-order boost converter (NFOBC) is proposed in this paper.
However, there is not enough literature covering the identica-
tion of the stabilizing region for the digital controller and the
development of optimal digital controllers for such kinds of
converters. In this paper, the predetermination of the stabilizing
region of the digital controller using a Tchebyshev polynomial
approach [17][20], and obtaining an optimal digital controller
using a genetic algorithm (GA) [21] for the proposed higher
order boost converter, is addressed.
Several digital controller design methods based on
continuous-time models have been reported in control theory.
A nonlinear digital proportional-plus-integral-plus derivative
(PID) controller for synchronous buck converter was reported
in [9], wherein the controller gains are selected based on the er-
ror signal magnitude. The main limitation of this method is that
the gain ranges must be specied well in advance. Autotuning-
based methodology has been employed for designing a
PID controller for controlling switch-mode power supplies
[10]. This design method is based on the target bandwidth
requirement. A look-up-table-based digital PID design was
discussed in [2]. However, this occupies more memory space
of the processor. Most of the reported works are based on either
trial-and-error methods or evolutionary optimization methods,
but obtaining the range of gains and the stabilizing region
for the controller parameters is a complex task. Furthermore,
such designs have either a restricted range of operation or the
resulting range is infeasible for the power supply.
The digital redesign approach uses continuous-time small-
signal models [4], which are accurate only in the low-frequency
region. Furthermore, higher order converters exhibit complex
conjugate right half-plane zeros and nominal poles. On account
of these poles and zeros, the small-signal transfer functions
exhibit an up-down or down-up glitch, and the sharpness of
this glitch depends on the converter parasitic components. On
account of the limited range of the accuracy of continuous-
time small-signal models, the digitally redesigned controllers
may yield specic relative stability margins (gain margin (GM),
phase margin (PM), and crossover frequency) during design,
but the corresponding digital controller does not exhibit the
desired closed-loop converter performance in real time, as
indicated by the stability margins. In order to avoid the com-
plexities involved in the ad hoc and trial-and-error procedures,
a systematic digital controller design for the NFOBC based on
discrete-time models is established in this paper. A Tchebyshev
polynomial approach [17][20], which deals with discrete-time
z-transfer functions, is the basis for the controller design and
Fig. 1. Circuit diagram and operating modes of the proposed fth-order boost
converter. (a) Proposed fth-order boost converter. (b) Circuit diagram for
mode-1 operation. (c) Circuit diagram for mode-2 operation.
the predetermination of the stabilizing region. As the method-
ology is based on the discrete-time models, the controller, as
well as the resulting stabilizing region, feasibility is closer to
the realistic range. Once the stabilizing region for the digital
controller is known, there is a need to choose parameters of the
digital controller such that the closed-loop converter exhibits an
optimal performance. Although several optimization methods
have been reported in the literature, here, a GA [21] is used
to choose the optimal controller parameters from the predeter-
mined stabilizing region.
II. MODELING OF THE NFOBC
An NFOBC is shown in Fig. 1. In comparison with the
conventional boost converter, it has an additional boosting
network and consists of two capacitors (C
1
and C
2
), one diode
(D
2
), and an inductor (L
2
). Although the number of energy
storage components in the proposed converter is the same as
in the fth-order converter reported in [8], these two circuits
are different because of their physical location within the
circuit. These differences give the proposed converter several
advantages, of which the important features are the following:
1) the input source current ripple is very small compared with
the conventional boost converter and fourth- and fth-order
boost converters; 2) better voltage boosting capability in the
low duty ratio range; and 3) the voltage stress of capacitors (C
1
and C
2
) is less than the load voltage. A detailed comparison
of the various stress factors of the proposed converter with the
fourth- [7] and fth-order boost converters [8] is compiled for
identical source and load conditions and listed in Table I(a). A
272 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 1, JANUARY 2014
TABLE I
(a) COMPARISON oF THE NFOBC COMPONENT STRESS OVER THE
FOURTH AND FIFTH-ORDER BOOST CONVERTERS. (b) ANALYTICAL
RIPPLE EXPRESSION OF THE NFOBC, THE FOBC, AND THE
FIFTH-ORDER BOOST CONVERTER
time-domain analysis has been carried out for the three afore-
mentioned converters; then, various analytical expressions,
namely, ripple current, capacitor voltage stress, etc., are derived
and listed in Table I(b).
As this converter design is essentially for achieving a higher
load voltage from a low input dc supply, the magnitude of
current drawn on the source side is high, and hence, the in-
ductor currents i
1
and i
2
are continuous. In view of this, the
NFOBC analysis is discussed here for continuous current mode
of operation, wherein the converter has two different circuits
depending on the ON or OFF position of the switch S. Switch
S and D
1
conduct in mode 1, whereas diode D
2
conducts in
mode 2, and the corresponding equivalent circuits are shown
in Fig. 1(b) and (c), respectively. A steady-state analysis and a
discrete-time model of the NFOBC are established here under
four assumptions.
1) Switching devices are ideal.
2) The converter time constant is very high compared with
the switching time period.
3) The total delay in the control loop (analog-to-digital
conversion time plus control algorithm execution time)
is shorter than the switching time period.
4) While evaluating the state-transition matrix, higher and
second-order terms are neglected.
TABLE II
DESIGN EQUATIONS OF THE NFOBC
A. Steady-State Analysis
A steady-state analysis of the NFOBC is established here
using power balance theory. To nd the voltage gain of the
converter, a volt-second balance is applied for the two inductors
together with Kirchhoffs voltage/current law equations, and
the corresponding relationships are
Switch-ON period Switch-OFF period
v
L1
= (V
g
v
c2
v
0
) v
L1
= (V
g
v
c2
v
0
)
v
L2
= (v
c1
+v
0
) v
L2
= (v
c1
+v
c2
+v
0
)
Applying volt-second balance to inductor L
1
(V
g
v
c2
v
0
)D + (V
g
v
c2
v
0
)(1 D) = 0
=> v
c2
= (V
g
v
0
). (1)
Applying volt-second balance to the inductor L
2
(v
c1
+v
O
)D + (v
c1
+v
c2
+v
O
)(1 D) = 0. (2)
Simplifying (1) and (2) results in the voltage gain of the
converter as
v
0
V
g
=
(2 D)
(1 D)
. (3)
The energy storage elements design equations are established
through a simple time-domain analysis, and the corresponding
equations are tabulated in Table II.
B. Discrete-Time Model of the NFOBC
The NFOBC has two different operating modes, as shown in
Fig. 1, and in each mode of operation, the circuit is linear, and
its behavior can be easily described by the discrete-time state-
space model given by
[ x] = [A
j
][x] + [B
j
][u]
[y] = [E
j
][x]
_
t
j
< t < t
(j+1)
(4)
where [A
j
] is the state matrix, [B
j
] is the input matrix, [E
j
] is
the output matrix, [x] is the state vector, [y] is the output vector,
and [u] is the forcing function vector. Equation (5) gives the
values for [A
1
], B
1
, E
1
, E
2
, a, r
e1
, and r
a
[A
1
] =
_

(r
1
+r
e
+r
a
)
L
1
(r
e
+r
a
)
L
1
r
c2
r
34
L
1
r
c1
r
34
L
1
(r
ar
1)
L
1
(r
e
+r
a
)
L
2

(r
2
+r
e
+r
a
)
L
2
r
c2
r
34
L
2
r
c1
r
34
L
2
(1r
ar
)
L
2
r
c2
r
34
C
1
r
c2
r
34
C
1
1
r
34
C
1
1
r
34
C
1
0
r
c1
r
34
C
2
r
c1
r
34
C
2
1
r
34
C
2
1
r
34
C
2
0
1
aC
2
1
aC
2
0 0
1
aRC
2
_

_
VEERACHARY: DIGITAL CONTROLLER DESIGN FOR FIFTH-ORDER BOOST CONVERTER 273
TABLE III
Z-DOMAIN SMALL-SIGNAL MODEL EQUATIONS
[A
2
] =
_

(r
1
+r
c2
+r
a
)
L
1
(r
c2
+r
a
)
L
1
0
1
L
1
(r
ar
1)
L
1
(r
c2
+r
a
)
L
2

(r
2
+r
c1
+r
c2
+r
a
)
L
2
1
L
2
1
L
2
(1r
ar
)
L
2
0
1
C
1
1
C
1
0 0
1
C
2
1
C
2
1
C
2
0 0
1
aC
2
1
aC
2
0 0
1
aRC
2
_

_
B
1
=B
2
= [1/L
1
0 0 0 0]
T
E
1
= [ 1/a 1/a 0 0 (1 1/aR) ]
E
2
= [ r
a
r
a
0 0 (1 r
ar
) ]
a =(R +r
c3
)/R;
r
e1
= [r
c1
r
c2
/(r
c1
+r
c2
)] ;
r
a
=r
c3
/a. (5)
The discrete-time modeling for trailing-edge modulation re-
ported in [8] and [16] has been used here to establish var-
ious small-signal z-transfer functions, and the corresponding
model is
x[NT
s
] = x[(N 1)T
s
] +

d [(N 1)T
s
] (6)
where =e
A
1
(DT
s
t
d
)

2
, =e
A
1
(DT
s
t
d
)

2
,
1
=e
A
1
t
d
,

2
= e
A
2
D
2
T
s
, and = [(A
1
A
2
)X + (B
1
B
2
)V
g
]. Var-
ious small-signal z-transfer functions can be easily obtained
from this model, and the required transfer functions for the dig-
ital controller design are listed in Table III for easy reference.
III. DIGITAL CONTROLLER DESIGN
Controller design through continuous-time s-domain ap-
proach and then transforming into z-domain needs an appro-
priate sz transformation [8]. Furthermore, the small-signal
models obtained through linearization are accurate in the low-
frequency region, and hence, controllers obtained from such
models are less accurate, needing a lot of tuning while im-
plementing in real time. On the other hand, digital controllers
obtained from the converter discrete-time models, which are
derived in Section II, are more accurate as the modeling method
handles the sample-and-hold time delay effects. In view of
this, the nal resulting digital controller is more realistic and
meets the design tradeoffs without needing any ne-tuning. A
block diagram of the closed-loop controlled NFOBC is shown
in Fig. 2. The major task here is to generate the complete
stabilizing region of the digital controller that ensures load
Fig. 2. Block diagram of the digital controlled NFOBC.
voltage regulation against expected line and load perturbations.
Digital controller design through a trial-and-error approach
together with pole placement has been discussed in [9]. Robust
digital controller design [7], [8] through sensitivity functions
shaping has been reported to achieve robust performance re-
quirements. In both of these methods, the loop gain is the basis
for the design. The proposed Tchebyshev polynomial based
design also begins with loop gain but generates the entire sta-
bilizing region for the digital controller parameters (k
0
, k
1
, k
2
,
k
3
, and k
4
).
This design also ensures the desired range of stability mar-
gins to the closed-loop converter system, i.e., GM > 6 dB,
PM is 45

75

, and a sufcient bandwidth. The detailed

step-by-step design methodology is discussed in the following
paragraphs.
A. Tchebyshev Representation of Real Polynomials and
Rational Functions
Tchebyshev polynomials [17] are more useful in the design
of the controllers for discrete-time systems. These polynomials
together with Fosters theorem form the basis for obtaining
the necessary and sufcient conditions for Schur stability [16]
applicable to discrete-time systems. Tchebyshev polynomial
representation of a discrete-time transfer function along with
the root counting formula [18], with respect to the unit circle,
gives a set of linear inequalities in two unknowns for a xed
value of the third parameter. The solution region of these
inequalities is the stabilizing region of the digital controller
parameters.
Consider an nth order z-domain polynomial with real coef-
cients as P(z) = (a
n
z
n
+a
n1
z
n1
+ +a
0
). The image
of this polynomial is evaluated on the upper half of circle C

of
radius , which is centered at the origin, i.e.,
_
P(z) : z = e
j
, 0
_
. (7)
The preceding image P(z) can be easily expressed in terms of
R(u, ) and T(u, ) polynomials by substituting u = cos() as
P(e
j
) = R(u, ) +j
_
1 u
2
T(u, ) =: P
c
(u, ) (8)
where
R(u, )=a
n
c
n
(u, )+a
n1
c
n1
(u, )+ +a
1
c
1
(u, )+a
0
T(u, )=a
n
s
n
(u, )+a
n1
s
n1
(u, )+ +a
1
s
1
(u, )
c
k
(u, )=
k
c
k
(u), s
k
(u, )=
k
s
k
(u), k=0, 1, 2 . . .
274 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 1, JANUARY 2014
and C
k
(u) and S
k
(u) are real polynomials in u satisfying the
following recursive relations:
s
k
(u) = c

k
(u)/k, k = 1, 2, . . . (9)
c
k+1
(u) = uc
k
(u) (1 u
2
)s
k
(u). (10)
These are known as the Tchebyshev polynomials of the rst and
second kinds, respectively. The complex plane image of P(z)
as z traverses in the upper half of circle C

can be easily
obtained by evaluating P
c
(u, ) as u changes from 1 to 1.
B. Root Counting Formula
Let Q(z) = P
1
(z)/P
2
(z), where both numerator and de-
nominator polynomials are real rational functions. Let
R
i
(u, ) +j

1 u
2
T
i
(u, ), i = 1, 2, denote the Tchebyshev
representation of Q(z) polynomial on circle C

. Let R(u, )
and T(u, ) be dened by
R(u, )=R
1
(u, )R
2
(u, )+(1u
2
)T
1
(u, )T
2
(u, ) (11)
T(u, )=T
1
(u, )R
2
(u, )R
1
(u, )T
2
(u, ). (12)
Suppose that T(u, ) has z number of zeros at u = 1,
and let t
1
. . . t
k
represent real distinct zeros of T(u, ) of odd
multiplicity ordered as follows:
1 < t
1
< t
2
< < t
k
< +1. (13)
If z
1
and z
2
are the zeros of P
1
(z) and P
2
(z), respec-
tively, inside circle C

and no zeros on it, then according to

the root counting formula [18], the following identity has to
be satised in order to have a set of inequalities, which will
identify the stability region:
z
1
z
2
=
1
2
sgn
_
T
(p)
(1, )
_

_
sgn [R(1, )] + 2
k

j=1
(1)
j
sgn [R(t
j
, )]
+ (1)
k+1
sgn [R(1, )]
_
. (14)
C. Formulation of Stabilizing Regions
Consider the closed-loop control of the NFOBC (see Fig. 2),
wherein the converter load voltage dependence on the duty ratio
is represented by its discrete-time transfer function G(z) =
B(z)/A(z), with B(z) and A(z) being polynomials with real
coefcients, and with degrees B(z) n and A(z) = n, respec-
tively. The closed-loop converter is stable if the characteristic
polynomial [see (16)], i.e., (z), is Schur stable. Several dif-
ferent types of digital compensators [6][13] can be easily de-
signed for the proposed converter, but for the sake of simplicity,
both from the point of view of design and implementation, the
second order compensator (two-pole and two-zero congura-
tion) is sufcient in order to realize performance tradeoffs, and
it is given by
G
c
(z) =
k
c
(z z
1c
)(z z
2c
)
(z p
1c
)(z p
2c
)
=
[k
2
z
2
k
1
z +k
0
]
[z
2
k
3
z +k
4
]
(15)
where k
2
= k
c
, k
1
= k
c
(z
1c
+z
2c
), k
0
= (k
c
z
1c
z
2c
), k
3
=
(p
1c
+p
2c
), k
4
= (p
1c
p
2c
), z
1c
/z
2c
, and p
1c
/p
2c
, respectively,
are zero(s) and pole(s) locations of the digital controller. Al-
though this compensator is simple to implement, judicious se-
lection of the polezero location is required in order to stabilize
the NFOBC system, together with satisfying the desired dy-
namic response specications. In this stabilizing region, there
exist several controller parameter combinations stabilizing the
closed-loop converter. Hence, there is a need to identify the
range and the optimal controller parameters. Using Tchebyshev
polynomial representation, the converter model can be repre-
sented in general form, and the corresponding characteristic
polynomial is
(z) = (z p
1c
)(z p
2c
)A(z) +k(z z
1c
)(z z
2c
)B(z).
(16)
Multiplying the preceding characteristic polynomial equa-
tion on both sides with
2
z
1
B(
2
z
1
) results in

2
z
1
(z)B(
2
z
1
) =
2
z
1
[(z p
1c
)(z p
2c
)A(z)
+k(z z
1c
)(z z
2c
)B(z)] B(
2
z
1
). (17)
Substituting z = [u +j

1 u
2
] and z
1
= [u
j

1 u
2
] and then simplication yields

2
z
1
(z)N(
2
z
1
)
=
_

2
(u +p
1c
+p
2c
+up
1c
p
2c
)
+j
3
_
1 u
2
(1 p
1c
p
2c
)
_
[P
1
+jP
2
_
1 u
2
]
+kP
3
_

2
(u +z
1c
+z
2c
+uz
1c
z
2c
)
+j
3
_
1 u
2
(1 z
1c
z
2c
)
_
(18)
where
P
1
(u, ) =R
A
(u, )R
B
(u, )
+ (1 u
2
)T
A
(u, )T
B
(u, ) (19)
P
2
(u, ) =R
A
(u, )T
B
(u, ) T
B
(u, )R
A
(u, ) (20)
P
3
(u, ) =R
2
B
(u, ) + (1 u
2
)T
2
B
(u, ) (21)
VEERACHARY: DIGITAL CONTROLLER DESIGN FOR FIFTH-ORDER BOOST CONVERTER 275
and
A(z)|
z=e
j = A(e
j
)

u=cos
:
=R
A
(, u) +j
_
1 u
2
T
A
(, u)
B(z)|
z=e
j = B(e
j
)

u=cos
:
=R
B
(, u) +j
_
1 u
2
T
B
(, u)
B(
2
z
1
)

z=e
j
= B(e
j
)

u=cos
:
=R
B
(, u) j
_
1 u
2
T
B
(, u).
Expressing (18) in real and imaginary forms results in the
following equations:

2
z
1
(z)N(
2
z
1
)
= R
p
(, u, k, p
1c
, p
2c
, z
1c
, z
2c
)
+j
_
1 u
2
T
p
(, u, k, p
1c
, p
2c
, z
1c
, z
2c
) (22)
R
p
=
2
P
1
[p
1c
p
2c
+u(1 +p
1c
p
2c
)]
+
3
P
2
(1 u
2
)(p
1c
p
2c
1)
+
2
P
3
k [z
1c
z
2c
+u(1 +z
1c
z
2c
)] (23)
T
p
=
2
{P
1
(1 p
1c
p
2c
) P
2
[p
1c
p
2c
+u(1 +p
1c
p
2c
)]
+kP
3
(1 z
1c
z
2c
)} . (24)
From the preceding equations, it is evident that R
p
and
T
p
polynomials are dependent on the converter and controller
parameters. Applying the number root formula to the rational
function, i.e., (22), and imposing the Schur stability require-
ments yield a set of linear inequalities in terms of the unknown
parameters k, z
1c
/z
2c
, and p
1c
/p
2c
. The digital controller poles,
i.e., p
1c
and p
2c
, must be judiciously placed such that the
closed-loop converter is capable of attenuating the noise enter-
ing the control loop, together with the zero steady-state error
against step disturbances, such as line and load uctuations.
The closed-loop NFOBC exhibits zero steady-state error only
if the resultant transfer function is of type 1 or higher, and
to achieve this, the compensator of one of the poles must be
xed at z = p
1c
(p
1c
= 1). To achieve noise attenuation, the
second pole, i.e., p
2c
, location should be in the 01 range
(0 < p
2c
< 1). For the converter under consideration, p
2c
=
0.5839 gives better noise attenuating properties with the param-
eters k
3
= 1.5839 and k
4
= 0.5839. The remaining parameters
(k
0
, k
1
, k
2
) need to be determined and are dependent upon the
z
1c
and z
2c
locations. By xing one of these parameters, the
remaining two variables regions, satisfying Schur stability, can
be easily established by plotting the linear inequalities obtained
earlier. The following discussions establish the stabilizing re-
gions for the NFOBC.
D. Stabilizing Digital Controller Design for the NFOBC
The goal is to design a suitable stabilizing digital controller
G
c
(z), which exhibits, for a step reference r, a settling time
of less than 10 ms and an overshoot of less than 10%. The
proposed NFOBC dynamics are described by a set of z-transfer
functions, as shown in Fig. 2, of which the control-to-output
TABLE IV
NFOBC PARAMETERS
transfer function involved in the loop design process and for
the converter parameters, which are listed in Table IV, is
G
vd
(z)=
[0.05301z
4
+0.2107z
3
0.3132z
2
+0.2064z0.05093]
[z
5
4.678z
4
+8.787z
3
8.287z
2
+3.926z0.7478]
.
(25)
Converting into Tchebyshev form, we have
R
D
= 15.2u
5
35.95u
4
15.08u
3
+ 19.7u
2
+ 16.94u + 2.88 (26)
T
D
=15.22u
4
+ 35.95u
3
+ 22.69u
2
1.73u 3.688 (27)
R
N
= 0.407u
4
0.82u
3
0.207u
2
+ 0.409u + 0.2051 (28)
T
N
(, u) =0.407u
3
+ 0.8179u
2
0.41u 0.0001. (29)
By substituting values of R
D
, T
D
, R
N
, and T
N
in (19)(21),
we obtain
P
1
(, u) =0.7749u
5
+ 3.69u
4
7.01u
3
+ 6.65u
2
+ 3.14u0.5912 (30)
P
2
(u) = 0.775u
4
3.08u
3
4.594u
2
3.044u 0.7562 (31)
P
3
(u) =0.0415u
4
+ 0.1666u
3
+ 0.251u
2
+ 0.1677u + 0.042. (32)
From the root counting formula applied to (17), we obtain
i

+i
N
(l + 1)
=
1
2
sgn [T
p
(1, , K
3
)]

_
sgn [R(1, , k
0
, k
1
, k
2
)]
+ 2
k

j=1
(1)
j
sgn [R(t
j
, , k
0
, k
1
, k
2
)]
+ (1)
k+1
sgn [R(+1, , k
0
, k
1
, k
2
)]
_
(33)
276 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 1, JANUARY 2014
where i

are the roots of characteristic equation within the

unit circle, i
N
are the roots of the reverse polynomial N
r
(z)
of the numerator inside the unit circle, and l is the order
of the reverse polynomial of the numerator. The characteristic
equation has order = 5; thus, i

= 7. In addition, we have
i
N
= 1 and l = 4. Hence, i

+i
N
(l + 1) = 3. In addition,
for normal case, we choose the radius of circle as 1; thus,
in order to satisfy the root counting formula, we should have
at least two real roots for T(u, K
3
) between (1,1). Hence,
the range of K
3
can be found out by solving T(u, K
3
) such
that the two real distinct roots are within the unit circle. For the
NFOBC, the range of K
3
is 0.020.06.
As an example, for K
3
= 0.04, the roots of T(u, K
3
) are
0.9998 and 0.9227. In order to have matching magnitudes
on either sides of (33), the following inequalities are obtained:
sgn [R(1, k
1
, k
2
, 0.04)] >0
sgn [R(0.9998, k
1
, k
2
, 0.04)] <0
sgn [R(0.9227, k
1
, k
2
, 0.04)] >0
sgn [R(+1, k
1
, k
2
, 0.04)] <0. (34)
Equation (34) represents a set of linear inequalities in 2-D
space (k
1
, k
2
), and their region of intersection is the feasible
stabilizing region of the digital controller. This set of inequality
equations is graphically solved by using the plotregion com-
mand in MATLAB [22]. Feasible regions have been generated
for different values K
3
(0.020.06), for which the closed-loop
NFOBCsystemis stable (ensuring the Schur stability criterion),
and the corresponding 3-D and 2-D views are shown in Fig. 3.
Although different combinations of k
0
, k
1
, and k
2
stabilize the
closed-loop converter, the disturbance rejection rate, and the dy-
namic response against step load/source perturbation, depends
upon the controller parameter combinations. Furthermore, dif-
ferent combinations may also give close dynamic response
characteristics with different disturbance rejection features.
Manually selecting the right parameter combination from
the feasible stabilizing region, which results in an optimal
dynamic performance, is a challenging task for a designer. In
order to choose optimal controller parameters from the known
stabilizing region, and to overcome the serious limitations of
trial-and-error selection, a GA-based [21] search technique was
employed. Here, the optimal controller parameters selection is
based on the minimization of performance index, an integral
time absolute error (ITAE), subject to the constraint of a loop
gain crossover frequency of less than 400 Hz. For the NFOBC,
the ITAE gives the best selectivity of the performance indices
over the integral of time multiplied by the squared error (ITSE).
Furthermore, it has the advantage of producing smaller over-
shoots and oscillations than the ITSE, or integral square error
performance indices. Hence, this performance index is chosen
here for obtaining the optimum digital controller parameters.
The justication for putting the constraint on the crossover
frequency is that the proposed converter has complex conjugate
polezero pairs in close proximity causing the bode-magnitude
plot to show a sharp rise and then fall. This causes an up-
down glitch in the loop gain plot, which may intersect the 0-dB
Fig. 3. Stabilizing digital controllers parameter regions. (a) Three-
dimensional view. (b) Top view.
line resulting in the conditionally stable system. To avoid this
situation, the loop gain crossover frequency must be limited by
enforcing the constraint, while searching for optimal controller
parameters (see Fig. 4). The inputs to this optimization problem
are the digital controller parameter boundaries (k
0
, k
1
, and k
2
),
as shown in Fig. 3. The convergence of the minimization of the
ITAE performance index is subject to the loop gain constraint,
which is obtained from the GA optimization. The optimized
controller parameters are k
0
= 0.019, k
1
= 0.0617, and k
2
=
0.0432.
There exists a local optimal controller in each of the stabi-
lizing regions shown in Fig. 3, having a local minimum ITAE
performance index, and one can easily nd this by choosing an
appropriate range for k
0
, k
1
, and k
2
parameters while initiating
the GA optimization. However, such a selection gives subopti-
mal performance and needs to nd a global minimum perfor-
mance index. This can be achieved by choosing an appropriate
search region for the GA and for the problem under considera-
tion: k
2
= 0.020.08; k
1
= 0.10.08; k
0
= 0.010.001.
VEERACHARY: DIGITAL CONTROLLER DESIGN FOR FIFTH-ORDER BOOST CONVERTER 277
Fig. 4. Loop gain frequency response plots with different stabilizing regions
controller parameters listed in Table V (DG-1DG-5).
IV. RESULTS AND DISCUSSION
To validate the design methodology, simulation studies have
been made on a 30-W 12- to 28-V NFOBC and then com-
pared with prototype experimental observations. The laboratory
prototype NFOBC parameters are tabulated in Table IV. The
salient features of the proposed converter (low source current
ripple, better voltage gain, etc.) are experimentally veried,
and measured observations are shown in Figs. 58. Fig. 5
shows the percentage source ripple current variation with duty
ratio, whereas Fig. 6 represents steady-state source current
waveforms of the three converters (D 50%). In comparison
with other topologies (FOBC, fth-order boost converter), the
proposed NFOBC source current ripple is very small, and it is
almost independent of load or duty ratio variation. Furthermore,
the NFOBC exhibits better voltage gain and efciency at lower
duty ratios, as shown in Figs. 7 and 8. Lower source current
ripple in the proposed NFOBC is on account of low impressed
voltage (V
g
(v
c3
+v
0
)) across inductor L
1
[input source
current ripple expression from Table I(b)]. This is due to the
existence of capacitor C
2
, and it charges to a voltage such
that the difference between V
g
and (v
c3
+v
0
) is very small.
In other converters, i.e., fth-order boost converter and FOBC,
the inductor impressed voltage depends on the input dc source
voltage V
g
[input source current ripple expression is given
in Table I(b)], wherein realizing lower source ripple current
demands larger inductance and is responsible for poor dynamic
performance.
Following the procedure discussed in Section III, digital con-
troller stabilizing regions have been generated for the NFOBC.
The design specications enforced while generating the stabil-
ity regions, as well as in the GA optimization, are, namely,
GM of at least 6 dB, PM of between 45

and 75

, and the
crossover frequency should be around 400 Hz. Closed-loop
converter system stability has been tested in MATLAB, and
for illustration, ve different controller parameter combinations
have been considered at random, as listed in Table V, from
the generated regions shown in Fig. 3, and the corresponding
loop gain plots are shown in Fig. 4. These frequency response
characteristics also indicate that the closed-loop converter
Fig. 5. Experimentally measured source current ripple of the three converters.
Fig. 6. Comparison of source current ripple for the three converters (experi-
mentally measured).
Fig. 7. Voltage gain variation with duty ratio (experimentally measured).
system is stable in all cases, exhibiting different relative sta-
bility margins listed in Table V, and the degree of stability is
region dependent.
To validate the developed theoretical analysis and the pro-
posed design, a 30-W prototype closed-loop NFOBC was built
and then tested for its stability and load voltage regulation
against source and load perturbations. PSIM software [23] is
used for time-domain simulations. The digital controllers were
implemented using a DSPIC30F6010 microcontroller [24]. The
devices used in the laboratory prototype converter circuits were
switch IRF540, diode MUR1560, and IR2110 driver circuits.
The load voltage is sensed, where sampling of all signals is
278 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 1, JANUARY 2014
Fig. 8. Efciency variation with output power (experimentally measured).
TABLE V
DIGITAL CONTROLLER PARAMETERS
done at 100 kHz, and is brought down into the range 05 V,
which is then passed on to the analog-to-digital converter of the
DSPIC30F6010 processor. The digital controller [see (14)] has
been transformed into a discrete-time control law given by
d(n) = k
3
d(n 1) +k
4
d(n 2) +k
2
e(n)
+k
1
e(n 1) +k
0
e(n 2) (35)
where d(n), d(n 1), and d(n 2) are the new, one-cycle-
before, and two-cycles-before duty ratios, respectively; whereas
e(n), e(n 1), and e(n 2) are the new, one-cycle-before, and
two-cycles-before error signals, respectively.
The NFOBC regulation feature has been tested both in
simulation and experiment, and for illustration, the following
test conditions are presented as follows: step change in 1) load
R : 26 13 at V
g
= 12 V and 2) source voltage V
g
: 12
15 V at R = 26 . It is shown (see Figs. 9 and 10) that the
load voltage regulates to 28 V in about 68 ms. The digital
controller parameters listed in Table V are falling within the
stabilizing region, and for verication of this fact, dynamic
response characteristics have been captured against step load
disturbances and plotted in Figs. 9 and 10. These dynamic re-
sponse characteristics conrm the closed-loop system stability
in each of the stabilizing controller regions.
The dynamic response characteristics are also captured with
an optimal controller, i.e., G
c
(z), and shown in Figs. 9 and 10.
In order to show that the controller obtained through GA is
an optimal one, parameters for another controller are chosen
from the stabilizing area, i.e., G
cnopt
(z) : (DG-5), namely,
Fig. 9. Simulated dynamic response of the load voltage against disturbances.
(a) Start-up response. (b) Source voltage perturbation. (c) Load resistance
perturbation.
k
0
= 0.0094, k
1
= 0.037, and k
2
= 0.03; and experimental
dynamic responses shown in Fig. 9(a) have been measured for
identical step changes. A comparison of these results reveals
that the dynamic performance of the closed-loop converter is
better with the optimal digital controller, but an inferior start-
up dynamic response is observed with the G
cnopt
(z) controller.
Although the G
cnopt
(z) controller maintains the closed-loop
converter system stability, it is unable to yield a better dynamic
response than that obtained by G
c
(z). This clearly demonstrates
VEERACHARY: DIGITAL CONTROLLER DESIGN FOR FIFTH-ORDER BOOST CONVERTER 279
Fig. 10. Experimentally measured dynamic response of the load voltage
against disturbances. (a) Start-up response. (b) Source voltage perturbation.
(c) Load resistance perturbation.
that there is a need to choose the appropriate digital controller
parameter combination from the generated stabilizing regions.
The NFOBC is unstable for any other controller parameter
combination, which is not belonging to any of the feasible
regions shown in Fig. 3, and to demonstrate this feature, the
digital controller parameters k
0
= 0.0094, k
1
= 0.037, and
k
2
= 0.0319 have been chosen in the experimentation. The
measured dynamic responses of the converter for these con-
troller parameters are plotted in Fig. 11, where the load voltage
is oscillating around the steady-state reference voltage of 28 V.
This result clearly demonstrates that stabilizing, as well as
Fig. 11. Dynamic response of the load voltage with digital controller param-
eters falling in unstable region.
Fig. 12. Experimentally measured load voltage response against gradual
variation of load.
Fig. 13. Experimentally measured load voltage response against gradual
variation of source voltage.
destabilizing, controller parameter regions exist in the k
1
and k
2
planes, as demonstrated in Fig. 3, and care must be taken when
formulating the feasible constraint set given by (33). In order to
have a stable and optimal closed-loop performance, one has to
identify the stable region rst and then the corresponding opti-
mal controller parameter combination, which can be easily ob-
tained from the proposed digital controller design methodology.
The optimal controller robustness demonstrating experi-
ments were also conducted, and for demonstration, the char-
acteristics are given in Figs. 12 and 13 for the following:
1) load resistance variation from 20 to 40 and 2) source
voltage gradual variation from 10 to 15 V. These measurements
clearly indicate that the load voltage is regulated even for
larger variations in supply voltage and load resistance. The
experimental observations (see Fig. 10) included here are in
close agreement with the simulated results shown in Fig. 9.
The reasons for the slight discrepancy between the simulation
and experimental observations are as follows: 1) mismatch in
the nonidealities of the experimental converter setup and the
simulation circuit; 2) accuracy of the voltage sensing system;
280 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 1, JANUARY 2014
3) unaccountable delays present in the actual test circuit; and
4) type of simulation solvers used in the simulator back end.
V. CONCLUSION
A new fth-order boost point of load converter has been
proposed, and then, its relative merits have been examined. A
digital controller design procedure has been proposed for an
NFOBC using a Tchebyshev polynomial approach. This design
was done by a Tchebyshev polynomial representation of the
characteristic equation along with the root counting criterion.
This methodology guarantees to more accurately predetermine
entire stabilizing regions, as compared with ad hoc procedures,
which may not produce all possible ranges of controller gains.
Within these ranges, the best controller parameters were ob-
tained through a constrained optimization problem using a GA.
It was observed that an ITAE is a more suitable objective func-
tion for the proposed converter. The experimental observations
show that the controller stability regions established from the
proposed design were shown to be more realistic and accurate.
Hence, the proposed digital controller design can be easily
extended, with some necessary alterations, for the design of
digital controllers for other complex dcdc converters.
REFERENCES
[1] Y.-F. Liu and P. C. Sen, Digital control of switching power converters,
in Proc. IEEE Conf. Control Appl., 2005, pp. 635640.
[2] L. Guo, J. Hung, and R. M. Nelms, Evaluation of DSP-based PID
and fuzzy controllers for dcdc converters, IEEE Trans. Ind. Electron.,
vol. 56, no. 6, pp. 22372248, Jun. 2009.
[3] E. Babaei, M. E. Seyed Mahmoodieh, and H. Mashinchi Mahery, Opera-
tional modes and output-voltage-ripple analysis and design considerations
of buckboost dcdc converters, IEEE Trans. Ind. Electron., vol. 59,
no. 1, pp. 381391, Jan. 2012.
[4] M. K. Kazimierczuk and N. Kondrath, Comparison of wide- and
high-frequency duty-ratio-to-inductor-current transfer functions of dcdc
PWM buck converter in CCM, IEEE Trans. Ind. Electron., vol. 59, no. 1,
pp. 641643, Jan. 2012.
[5] J. M. Kwon, W. Y. Choi, and B. H. Kwon, Single-switch quasi-resonant
converter, IEEE Trans. Ind. Electron., vol. 56, no. 4, pp. 11581163,
Apr. 2009.
[6] B. Bryant and M. K. Kazimierczuk, Voltage loop of boost PWM dcdc
converters with peak current-mode control, IEEE Trans. Circuits Syst. I,
Reg. Papers, vol. 53, no. 1, pp. 99105, Jan. 2006.
[7] M. Veerachary and A. R. Saxena, Design of robust digital stabilizing
controller for fourth-order boost dcdc converter: A QFT approach,
IEEE Trans. Ind. Electron., vol. 59, no. 2, pp. 952963, Feb. 2012.
[8] V. Mummadi and B. K. Mohan, Robust digital voltage mode controller
for fth-order boost converter, IEEE Trans. Ind. Electron., vol. 58, no. 1,
pp. 263277, Jan. 2011.
[9] M. Veerachary and S. Devassy, Digital voltage-mode controller for
soft-switching ZVT-ON boost converter, in Proc. IEEE ICPCES, 2010,
pp. 15.
[10] E. Figueres, G. Garcer, J. M. Benavent, M. Pascual, and J. A. Martnez,
Adaptive two-loop voltage-mode control of dcdc switching converters,
IEEE Trans. Ind. Electron., vol. 53, no. 1, pp. 239253, Feb. 2006.
[11] T. Mishima and M. Nakaoka, A novel high frequency transformer linked
soft-switching half bridge dcdc converter with constant frequency asym-
metrical PWM scheme, IEEE Trans. Ind. Electron., vol. 56, no. 8,
pp. 29612969, Aug. 2009.
[12] N. Gowra Ramakanth and D. Ganta, Discrete-time modeling of multi-
state dcdc converters, in Proc. IEEE PEDES, 2010, pp. 16.
[13] M. Veerachary, Two-loop controlled buckSEPIC converter for input
source power management, IEEE Trans. Ind. Electron., vol. 59, no. 11,
pp. 40754087, Nov. 2012.
[14] R. B. Amarendra and E. Vargil Kumar, Two-input dcdc converter
for dc-grid applications, in Proc. 5th IEEE PICONF, 2012, pp. 16,
[CD-ROM].
[15] G. Zhou, J. Xu, and Y. Jin, Elimination of subharmonic oscillation
of digital-average-current-controlled switching dcdc converters, IEEE
Trans. Ind. Electron., vol. 57, no. 8, pp. 29042907, Aug. 2010.
[16] D. Maksimovic and R. Zane, Small-signal discrete time modeling of dig-
itally controlled PWM converters, IEEE Trans. Power Electron., vol. 22,
no. 6, pp. 25522556, Nov. 2007.
[17] L. H. Keel, J. I. Rego, and S. P. Bhattacharyya, A new approach to
digital PID controller design, IEEE Trans. Autom. Control, vol. 48, no. 4,
pp. 687692, Apr. 2003.
[18] L. H. Keel and S. P. Bhattacharyya, Root counting and phase unwrapping
with respect to the unit circle with applications, in Proc. 40th IEEE Conf.
Decision Control, 2001, pp. 34593464.
[19] S. P. Bhattacharyya, A. Datta, and L. H. Keel, Linear Control Theory:
Structure, Robustness and Optimization. Boca Raton, FL, USA: CRC
Press, 2009.
[20] K. Zhou and J. C. Doyle, Robust Optimal Control. Englewood Cliffs,
NJ, USA: Prentice-Hall, 2000.
[21] R. A. Krohling and J. P. Rey, Design of optimal disturbance rejection PID
controllers using genetic algorithms, IEEE Trans. Evol. Comput., vol. 5,
no. 1, pp. 7882, Feb. 2001.
[22] MATLAB User Manual, The MathWorks Inc., Natick, MA, USA, 2008.
[23] PSIM User Manual, The Powersim Technologies, Rockville, MD, USA,
2008.
[24] dSPIC30F6010 User Manual, Microchip, Chandler, AZ, USA, 2008.
Mummadi Veerachary (SM04) was born in
Survail, India, in 1968. He received the Bachelors
degree fromJawaharlal Nehru Technological Univer-
sity (JNTU), Anantapur, India, the M.Tech. degree
from the Regional Engineering College, Warangal,
India, and the Dr. Eng. degree from the University
of the Ryukyus, Nishihara, Japan, in 1992, 1994,
and 2002, respectively.
From 1994 to 1999, he was an Assistant Profes-
sor with the Department of Electrical Engineering,
JNTU. From October 1999 to March 2002, he was
a Research Scholar with the Department of Electrical and Electronics Engi-
neering, University of the Ryukyus. Since July 2002, he has been with the
Department of Electrical Engineering, Indian Institute of Technology Delhi,
New Delhi, India, where he is currently a Professor. His research interests are
power electronics and applications, modeling and simulation of large power
electronic systems, design of power supplies for spacecraft systems, control
theory application to power electronic systems, and intelligent solutions for
power supplies.
Dr. Veerachary is an Editorial Member of The Institution of Engineering
and Technology (IET) Proceedings on Power Electronics, IET, U.K.; and the
Journal of Power Electronics. He served as one of the Guest Editors of the
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, for two Special Sec-
tions on Photovoltaic Power Processing Systems and Efcient and Reliable
Photovoltaic Systems. He also served as one of the Guest Coeditors of the
IEEE TRANSACTIONS ON POWER ELECTRONICS, for a Special Session on
Power Electronics in Photovoltaic Applications. He is currently serving as an
Associate Editor of the IEEE TRANSACTIONS ON AEROSPACE AND ELEC-
TRONIC SYSTEMS. He was the recipient of the IEEE Industrial Electronics
Society Travel Grant Award for the year 2001; the Best Paper Award at the
International Conference on Electrical Engineering 2000 held in Kitakyushu,
Japan; and the Best Researcher Award for the year 2002 from the President
of the University of the Ryukyus. He is listed in Whos Who in Science and
Engineering 2003.