Chap 7

C.
Hutchens Chap 7 ECEN 4303 Handouts

1
Chapter 7
CMOS Logic Ckts
Classical CMOS
Compound
Transmission Gate
Dual Pass Gate Logic
C. Hutchens Chap 7 ECEN 4303 Handouts
2
Choice of Beta vs min-geo
We typically select between
matched - increased power better NM
Min.Geometry. - decreased and power NM
convenient layout.
This only effects speed and power and device
geometry's not the circuit diagram.
NANDs 2, 3, and 4 input
NORs 2, 3, and 4 input
Compound Gates
Use Duality Thereom
prop
= ( R
on
+ R
op
) C
L
t = 2.2R
oeff
(C
d
+ nC
g
) = t
delay
3
NANDs and NORs
Step 1 Use Pos Logic function to get NMOS
network.
Step 2 Use Duality Thereom to get PMOS
network.
Step 3
Choice 1 Min Geo. All devices Equal
Choice 2 matched
Note n = 2, 3 or 4 device in series
reduces k
eff
(Effective Pullup
Resistor) by n = 2, 3, or 4
Now to achieve the inverter
equivalent we must scale the series
devices by n
EX 3 input NOR increase W
p
x n =3
True matching W
n
= W
min
, W
p
= 3 k
R
W
n
Qusi min. geo. W
n
= W
min
, W
p
= 3 W
n
True min. geo. W
n
= W
min
, W
p
= W
n
Assumes 1 NMOS
ON
Assumes 1 PMOS
ON
4
NANDs, NORs and Compound Nets
Min Geometry- all device L
min
& W
min
"Beta" matched- Use Worst case branch
R
onp
= R
onn
; (W
Peff
= K
R
W
Neff)
)
Again result is equal NM and t
r
= t
f)
"Optimal delay" design- Use Worst case
R
onp
= R
onn
/(k
R
)
1/2
; (W
Peff
= (k
R
)
1/2
W
Neff)
)
EX 3 input NAND inc. W
n
x n = 3 Over W
p
True matched W
n
= 3 W
min
, W
p
= k
R
W
n
t = 2.2R
oeff
(C
o
+ nC
gs
) .

i
C
L
= L C
ox
W
i
+ C
o
C
o
3 C
dbp
+ C
dbn
5
Classical CMOS gates Cont
EX 3 input NAND inc. W
n
x n =3 Over W
p

True matched W
n
= 3 W
min
, W
p
= k
R
W
n

Qusi Min. Geo. W
p
= W
min
, W
n
= 3 W
min

True Min Geo. W
n
= W
p
= W
min

prop
= ( R
on
+ R
op
) C
L

t = 2.2R
oeff
(C
d
+ nC
gs
)

For Quasi Min. Geo

R
on
= 3 R
on
three transistors in series

R
op
= 1 R
op
one transistor is worst case.

i

C
L
= L C
ox
W
i
+ C
db

C
d
= 3 C
dbp
+ C
dbn
If we approximate C
db
by 2C
gs

C
d
2L C
ox
4 W
min

Assumes 1 PMOS
ON
6
Gate Sizing
I. NANDs
1) Start with minimum geometry
2) Pseudo minimum geometry (PMG)
Scale NMOS devices by the number of NMOS devices in series
i.e. 3 input NAND all NMOS devices W = 3W min
3) Beta matched NAND
Scale all PMOS devices in the PMG design by KR =
op
on
4) Optimal delay - scale all PMOS in the PMG design by KR =

op op
/
II. NORs
1) Start with minimum geometry
2) Pseudo minimum geometry (PMG)
Scale all PMOS devices by the number of devices in series i.e.
4 for a 4 input NOR
Now all PMOS devices width are W = 4 W
min
3) Beta matched NOR
op
on
4) Optimal delay - scale all PMOS in the PMG design by KR =

op op
/
7
Gate Sizing
III. Compound gates i.e. AND-OR-INVERT
1) Start with all devices minimum geometry
2) Pseudo scale all series P & N MOS transistors
Start with worst case path Wx = nWx where n is the
number of transistors in series where x equals n or p for
the & NMOS or a PMOS string and n is the number
transistors in the string.
Continue to scale the remaining transistor logic strings up
to typically four until all transistors are scaled. CAUTION
you may (will) have conflicting objective. Use worst case
delay to make the final decision. ALWAYS simulate the
noise margin.
3) Beta match
op
on
4) Optimal Delay same as previous

8
Classical CMOS gates Cont
"Beta" matched- Worst case
R
onp
= R
onn
; (W
Peff
= K
R
W
Neff)
)
"Optimal delay" matched- Worst case
R
onp
= R
onn
/(k
R
)
1/2
; (W
Peff
= (k
R
)
1/2
W
Neff)
)
n input NAND
(Observing that CL is equal for t
rise
and t
fall
and
assuming V
TP
+ V
TN
equal 0)
nL/W
N
= K
R
L/W
P
n/W
N
= K
R
/W
P
W
N
= n W
P
/ K
R
K
R
W
N
= n W
P
9
Comments on Hand C est.
1) For the purpose of hand estimates we will only
include those Cs connected directly to the output
node.
2) If a gate drives 10 or more equivalent loads we
will ignore C
d
= C
o
= C
self
Equivalent Load Defined C
eq
LC
ox
(W
n
+ W
p
)
where W
n
and W
p
are the width of a single P
or NMOS transistor used in the driving gate.
Now
prop
= ( R
on
+ R
op
) C
L
where C
L
L C
ox
W
i
t = 2.2R
oeff
n LC
ox
(W
n
+ W
p
)
and n the number of effective loads
= {L C
ox
W
i
}/ LC
ox
(W
n
+ W
p
)
= {

W
i
}/ (W
n
+ W
p
)
NOTE we have assuned
all logic uses the same L.
This results an error that
over estimates
performance by about
20%. USE SPICE TO
VERIFY YOUR DESIGN.
10
Compound CMOS Gates
1 ) Start by developing NMOS Logic
and Limit any logic ckt to no more
than 4 branches and 4 transistors
in parallel
_
Z = A(D+E)+BC
2) Rule Convert AND branches to OR
and OR branches to AND to develop
the PMOS network.
3 ) Size as required to achieve Beta
or geo. matching
NMOS
W
C
= W
B
= 2W
min
; W
D
= W
E
= 2W
min
; and
W
A
= 2W
min
; note under all worst case
conditions for R
on
, R
oneff
equals the
resistance of a min geometry NMOS.
PMOS
W
B
= W
C
= W
D
= W
E
= 3k
R
W
min
W
A
= 2k
R
W
min
where k
R
= 2.5 for Beta
matched and k
R
= 1 for quasi min geo.
11
Compound CMOS Gates
_ _
Z = A(D+E)+BC Z = AB + CD + EF
We can use any combination of 1 to 4
branches and 1 to 4 transistors per
branch. Note as a simple example if we
need a 8 input NAND we should use a)
two 4 input NANDs and a 2 input NOR
(inverting NAND) with an inverter or b)
use two 4 input NORS (inverting NAND)
and a two input AND.
Now replace C with A
bar
and D
with B
bar
and we have an XNOR
Gate. How about an inclusive
OR
_ _
Z = AB + AB = A B
12
Transmission or t-gates
In Out
Control
Control
The virtue off a t-gate is that
1) it combines the pull-up
properties of the PMOS with
the pull-dwn properties of
the NMOS to
2) take advantage of the
bidirectional logic properties
of MOS switches. This is
equivalent ot relay logic
Pull up case A = V
DD
log 1 PMOS V = -V
DD
while NMOS shuts off and can not pull up
beyond V
DD
- V
TN
before it shuts off. To make
maters worse V
SB
= V
OUT.
Pull down case A = V
SS
log 0 NMOS V =
V
DD
while PMOS shuts off and can not pull
down below V
SS
- V
TP
before it shuts off. To
make maters worse V
SB
= -V
OUT.
13
T-gate Example Ckts
8 transistor XOR
3varible Boolean ex
Deselector cell for Mux and
Decoder ckts.
14
Selector Demultiplexer
S
S
I
0
I
1
S
S
Z
Selector:
Choose I0 if S = 0
Choose I1 if S = 1
Demultiplexer:
I to Z0 if S = 0
I to Z1 if S = 1
S
S
0
I
1
S
S
Z
Z
15
Well-formed Switching Networks
0
I
S
S
Z
S
1
Z
"0"
S
S
S
"0"
Problem with the Demux implementation:
multiple outputs, but only one connected to the input!
The fix: additional logic to drive every output to a known value
Never allow outputs to "float"
16
Steering Logic
"0"
Zero
I
1
One
"0"
"1"
"0"
Zero
One
I
2
"0"
Two
Complex Steering Logic Example
Switch Logic Implementation: 2-input Tally Circuit
Zero
One
"0"
"0"
"1"
I
1
Zero
One
"0"
I
2
Two
"0"
Cascade the 1-input implementation!
17
Optimal Delay t-gate or inverter
Optimal Delay for SOI T-gate
Assuming VTN = |VTP|
( )
p n ox
DD
N n
DD
DD
p p
DD
delay
W W LC
V KN W
L V
V KN W
L V
t +
|
|
.
|
\
|
=
2
2
2
2
( )( )
ox p ox n ONP ONN delay
LC W LC W R R t + + =
( )
p n
on n Dp p
DD
DD
delay
W W
W W V
L V
t +
|
|
.
|
\
|
+
=

1 1 2
2
2
DD
DD
on n
p
p n Dp p
n
delay
V
L V
W
W
W
W
t
2
2
2 1 1
|
|
.
|
\
|
+ + + =

0
1
2
= +
|
|
.
|
\
|
=

on n Dp
n
p
p
delay
W
W
W
dW
dt

n n p
n p
W
W W

1
2
=
p
n
n
op
n
n p
W W W
2
= =
This analysis/design approach works
equally well for t-gates as well as inverters.
18
Multiplexers/Selectors
General Concept
2 data inputs, n control inputs, 1 output
used to connect 2 points to a single point
control signal pattern form binary index of input connected to output
n
n
I
1
0
0
0
0
1
1
1
1
I
0
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
Z
0
0
1
0
0
1
1
1
A
0
1
Z
I
0
I
1
Functional form
Logical form
Z = A' I + A I
0 1
Two alternative forms
for a 2:1 Mux Truth Table
19
Multipler/Selectors
I3
I0
I2
I1
A
B
Z
Gate Level
Implementation
of 4:1 Mux
Gate Level
Implementation
of 4:1 Mux
Transmission Gate
Implementation of
4:1 Mux
Transmission Gate
Implementation of
4:1 Mux
twenty transistors but slower
thirty six transistors inc pwr
20
Decoders/Demultiplexers
Select
Select
Select
Select
G
Output
0
Select
Select
Output
1
Select
Select
"0"
"0"
Select
Select
Select
Select
G
Output
Output
0
1
Naive, Incorrect Implementation
All outputs not driven at all times
Correct 1:2 Decoder Implementation
21
Decoders/Demultiplexers
G
Output
0
"0"
"0"
Select
1
Select
G
Output
1
"0"
"0"
0
G
Output
2
"0"
"0"
G
Output
3
"0"
"0"
Switch Implementation of 2:4 Decoder
Operation of 2:4 Decoder
S0 = 0, S1 = 0
one straight thru path
three diagonal paths
22
Tree Decoder
Offers bidirectionality,
Efficent use of gates but is
slow and difficult to layout
efficiently.
23
T-GATE DELAY
t-gates in series behave as a diffusion system and can be modeled with the
following time constant.
n
2
R C/2 approximate "Diffusion" time for large networks
Disperse transmission line model
For this reason large tree decoders in RAM memories can be very slow. This is
remedied by adding an active inverter every 3 to 5 t-gate. The optimal interval
is a function of the process and can be found by writing a model equation for a
t-gates in series with an inverter loaded with a t-gate. Differenting a wrt delay
and solving for optimal number of t-gates between inverters.
24
T-GATE DELAY

(
+

=
inv TG
a a
a
n
t 2 . 2
2
) 2 )( 1 (
( )
TG
TG inv
a

5
5 11 10 +
=
EX
TG
= 12nS
inv
= 15nS
Find the optimal ratio of Beta
matched T-gates to to Beta
matched inverters.
a = 2.7 Select a = 3
25
t-GATE time constant
Esimating R
Progating 1 R R
onp
dominant
Progating 0 R R
onp
dominant
Estimating C -Count all capacitance on
the (cap changing state is less).
n
2
R C/2
EX progagating 1 V
ss
to V
DD
C = 3C
dbn
+ 3C
gdp
+ 6 C
gdn
3{ C
dbp
+ C
dbn
+

2LC
ox
(W
p
+ W
n
)/2},
R 2R
onp
|| R
onn
Propagating 0
R R
onp
|| 2R
onn
Propagating 1
C 3{ C
dbp
+ C
dbn
+

LC
ox
(W
p
+ W
n
)}
Note a t-gate nodes loaded by an inverter will have less C
dbx
but greater Cgs.
26
Pass Gate Logic
A B
null A+B AB A AB B AB (AB) AB (AB) B A+B A A+B A+B ID*

0 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 0
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
27
Dual Pass Gate Logic
A B
null A+B AB A AB B AB (AB) AB (AB) B A+B A A+B A+B ID*

0 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 0
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

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C.

Hutchens Chap 7 ECEN 4303 Handouts

4) Optimal delay - scale all PMOS in the PMG design by KR =

4) Optimal delay - scale all PMOS in the PMG design by KR =

4) Optimal Delay same as previous

null A+B AB A AB B AB (AB) AB (AB) B A+B A A+B A+B ID*

null A+B AB A AB B AB (AB) AB (AB) B A+B A A+B A+B ID*

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