1

August 1997
HI3026
8-Bit, 120 MSPS, Flash A/D Converter
Features
Differential Linearity Error . . . . . . . . . . . . . . . 0.5 LSB
Integral Linearity Error . . . . . . . . . . . . . . . . . . 0.5 LSB
Integral Linearity Compensation Circuit
Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . 21pF
Wide Analog Input Bandwidth . . . . . . . . . . . . . 150MHz
Low Power Consumption . . . . . . . . . . . . . . . . . . 760mW
Internal
1
/
2
Frequency Divider Circuit (w/Reset Function)
CLK/2 Clock Output
Compatible with ECL, PECL and TTL Digital Input Levels
1:2 Demultiplexed Output Pin
Surface Mounting Package
Direct Replacement for Sony CXA3026Q
Applications
RGB Graphics Processing (LCD, PDP)
Digital Oscilloscopes
Digital Communications (QPSK, QAM)
Magnetic Recording (PRML)
Description
The HI3026 is an 8-bit, high-speed, flash analog-to-digital
converter optimized for high speed, low power, and ease of
use. With a 120 MSPS encode rate capability and full-power
analog bandwidth of 150MHz, this component is ideal for appli-
cations requiring the highest possible dynamic performance.
To minimize system cost and power dissipation, only a +5V
power supply is required. The HI3026s clock input interfaces
directly to TTL, ECL, or PECL logic and will operate with single-
ended inputs. The user may select 16-bit demultiplexed output
or 8-bit single channel digital outputs. The demultiplexed mode
interleaves the data through two 8-bit channels at
1
/
2
the clock
rate. Operation in demultiplexed mode reduces the speed and
cost of external digital interfaces, while allowing the A/D con-
verter to be clocked to the full 120 MSPS conversion rate.
Fabricated with an advanced Bipolar process, the HI3026 is
provided in a space-saving 48-lead MQFP surface mount
plastic package and is specified over the -20C to 75C
temperature range. For a faster clock rate, please refer to
the HI3026A (140 MSPS).
Pinout
HI3026 (MQFP)
TOP VIEW
Ordering Information
PART
NUMBER
TEMP. RANGE
(C) PACKAGE PKG. NO.
HI3026JCQ -20 to 75 48 Ld MQFP Q48.12x12-S
HI3026EVAL 25 Evaluation Board
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24 23 22 21 20 19 18 17
9
10
11
12
13 14 15 16
33
34
35
36
37 38 39 40 41 42 43 44 45 46 47 48
P1D3
P1D2
P1D1
P1D0
DGND2
DV
CC2
DV
CC1
DGND1
P2D7
P2D6
P2D5
P2D4
DV
EE3
V
RB
AGND
V
RM1
AV
CC
AV
CC
V
RM3
AGND
V
RT
DGND3
V
IN
V
RM2
R
E
S
E
T
N
/
E
R
E
S
E
T
/
E
R
E
S
E
T
N
/
T
S
E
L
E
C
T
I
N
V
D
V
C
C
2
D
G
N
D
2
P
1
D
7
P
1
D
6
P
1
D
5
P
1
D
4
C
L
K
O
U
T
C
L
K
/
E
C
L
K
N
/
E
C
L
K
/
T
N
C
N
C
N
C
D
V
C
C
2
D
G
N
D
2
P
2
D
0
P
2
D
1
P
2
D
2
P
2
D
3
File Number 4109.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002. All Rights Reserved
2
Block Diagram
5 8 30 19 31 42 12
DGND3
DV
CC2
DV
CC1
INV
AV
CC
11
9
126
65
64
63
2
127
128
129
191
192
193
254
255
6
4
7
RESET/E
RESETN/E
RESETN/T
CLKN/E
CLK/E
CLK/T
V
RB
V
RM1
V
IN
V
RM2
V
RM3
V
RT
R1
R/2
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/2
DELAY
D Q
Q
SELECT
3 10 45 29 20 32 41 1
DV
EE3
DGND2 DGND1 SELECT
43
18
17
16
34
35
36
37
38
39
40
(MSB)
P1D7
P1D6
P1D5
P1D4
P1D3
P1D2
P1D1
P1D0
(MSB)
P2D6
P2D5
P2D4
P2D3
P2D2
P2D1
P1D0
NC
CLKOUT
(LSB)
P2D7
(LSB)
6
-
B
I
T

L
A
T
C
H

A
N
D

E
N
C
O
D
E
R
E
N
C
O
D
E
R
6 BITS
6 BITS
6 BITS
6 BITS
8 BITS
8 BITS
L
A
T
C
H
B
T
T
L
O
U
T
21
22
23
24
25
26
27
28
T
T
L
O
U
T
33
1
46
48
47
2
15
13
14
AGND
L
A
T
C
H
A
R/2
44
HI3026
3
Absolute Maximum Ratings T
A
= 25
o
C Thermal Information
Supply Voltage (AV
CC
, DV
CC1
, DV
CC2
) . . . . . . . . . . -0.5V to 7.0V
(DGND3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
(DV
EE3
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7.0V to 0.5V
(DGND3 - DV
EE3
). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
Analog Input Voltage (V
IN
) . . . . . . . . . . . . . . . . .V
RT
- 2.7V to AV
CC
Reference Input Voltage (V
RT
). . . . . . . . . . . . . . . . . . .2.7V to AV
CC
(V
RB
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
IN
- 2.7V to AV
CC
(|V
RT
- V
RB
|). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V
Digital Input Voltage
ECL (***/E (Note 2)) . . . . . . . . . . . . . . . . . . . . . . . . DV
EE3
to 0.5V
PECL (***/E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to DGND3
TTL (***/T, INV). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to DV
CC1
Other (SELECT) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to DV
CC1
V
ID
(|***/E - ***N/E| (Note 3)) . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300
o
C
(Lead Tips Only)
Recommended Operating Conditions
WITH A SINGLE POWER SUPPLY MIN TYP MAX
Supply Voltage
DV
CC1
, DV
CC2
, AV
CC
. . . . . . . . . . . . . . . +4.75 +5.0 +5.25V
DGND1, DGND2, AGND . . . . . . . . . . . . . -0.05 0 +0.05V
DGND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75 +5.0 +5.25V
DV
EE3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05 0 +0.05V
Analog Input Voltage (V
IN
) . . . . . . . . . . . . . . V
RB
- V
RT
Reference Input Voltage
V
RT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.9 - +4.1V
V
RB
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 - +2.6V
|V
RT
- V
RB
| . . . . . . . . . . . . . . . . . . . . . . . . 1.5 - 2.1V
Digital Input Voltage
PECL (***/E) V
IH
. . . . . . . . . . . . . . . DGND3 - 1.05 DGND3 - 1.4V
PECL (***/E) V
IL
. . . . . . . . . . . . . . . DGND3 - 3.2 DGND3 - 1.4V
TTL (***/T, INV) V
IH
. . . . . . . . . . . . . . . . . 2.0V - -
TTL (***/T, INV) V
IL
. . . . . . . . . . . . . . . . . . - - 0.8V
Other (SELECT) V
IH
. . . . . . . . . . . . . . . . . - DV
CC1
-
Other (SELECT) V
IL
. . . . . . . . . . . . . . . . . - DGND1 -
VID (Note 3) (|***/E- ***N/E|). . . . . . . . . . . 0.4 0.8 -
Max Conversion Rate (f
C
, Straight Mode) . . . 100 - -
MSPS
Max Conversion Rate (f
C
, DMUX Mode) . . . . 120 - -
MSPS
Ambient Temperature (T
A
) . . . . . . . . . . . . . . . . . . . . . -20
o
C to 75
o
C
WITH DUAL POWER SUPPLIES MIN TYP MAX
Supply Voltage
DV
CC1
, DV
CC2
, AV
CC
. . . . . . . . . . . . . . +4.75 +5.0 +5.25V
DGND1, DGND2, AGND. . . . . . . . . . . . . -0.05 0 +0.05V
DGND3 . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05 0 +0.05V
DV
EE3
. . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5 -5.0 -4.75V
Analog Input Voltage (V
IN
) . . . . . . . . . . . . . V
RB
- V
RT
Reference Input Voltage
V
RT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.9 - +4.1V
V
RB
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 - +2.6V
|V
RT
- V
RB
| . . . . . . . . . . . . . . . . . . . . . . . 1.5 - 2.1V
Digital Input Voltage
ECL (***/E) V
IH
. . . . . . . . . . . . . . . . DGND3 - 1.05 DGND3 - 0.5V
ECL (***/E) V
IL
. . . . . . . . . . . . . . . . DGND3 - 3.2 DGND3 - 1.4V
TTL (***/T, INV) V
IH
. . . . . . . . . . . . . . . . . 2.0V - -
TTL (***/T, INV) V
IL
. . . . . . . . . . . . . . . . . - - 0.8V
Other (SELECT) V
IH
. . . . . . . . . . . . . . . . - DV
CC1
-
Other (SELECT) V
IL
. . . . . . . . . . . . . . . . - DGND1 -
V
ID
(Note 3) (|***/E- ***N/E|) . . . . . . . . . . 0.4 0.8 -
Max Conversion Rate (f
C
, Straight Mode) . . . 100 - -
MSPS
Max Conversion Rate (f
C
, DMUX Mode). . . . 120 - -
MSPS
Ambient Temperature (T
A
) . . . . . . . . . . . . . . . . . . . . . -20
o
C to 75
o
C
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
JA
is measured with the component mounted on an evaluation PC board in free air.
2. ***/E and ***T indicate CLK/E and CLK/T, etc., for the pin name.
3. V
ID
: Input Voltage Differential.
Electrical Specifications DV
CC1
,
2
, AV
CC
, DGND3 = +5V, DGND1, 2, AGND, DV
EE3
= 0V, V
RT
= 4V, V
RB
= 2V,
T
A
= 25
o
C
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Resolution - 8 - Bits
DC CHARACTERISTICS
Integral Linearity Error, E
IL
V
IN
= 2V
P-P
, f
C
= 5 MSPS - - 0.5 LSB
Differential Linearity Error, E
DL
- - 0.5 LSB
ANALOG INPUT
Analog Input Capacitance, C
IN
V
IN
= +3.0V +0.07V
RMS
- 21 - pF
Analog Input Resistance, R
IN
4 - 50 k
Analog Input Current, I
IN
0 - 500 A
HI3026
4
REFERENCE INPUT
Reference Resistance (Note 4), R
REF
75 115 155
Reference Current (Note 5), I
REF
9.7 17.4 28 mA
Offset Voltage V
RT
Side, EOT 2 - 15 mV
Offset Voltage V
RB
Side, EOB 2 - 10 mV
DIGITAL INPUT (ECL, PECL)
Digital Input Voltage: High, V
IH
DGND3 - 1.05 - DGND3 - 0.5 V
Digital Input Voltage: Low, V
IL
DGND3 - 3.2 - DGND3 -1.4 V
Threshold Voltage, V
TH
- DGND3 - 1.2 - V
Digital Input Current: High, I
IH
V
IH
= DGND3 - 0.8V -50 - +50 A
Digital Input Current: Low, I
IL
V
IL
= DGND3 - 1.6V -75 - 0 A
Digital Input Capacitance - - 5 pF
DIGITAL INPUT (TTL)
Digital Input Voltage: High, V
IH
2.0 - - V
Digital Input Voltage: Low, V
IL
- - 0.8 V
Threshold Voltage, V
TH
- 1.5 - V
Digital Input Current: High, I
IH
V
IH
= 3.5V -50 - 0 A
Digital Input Current: Low, I
IL
V
IL
= 0.2V -500 - 0 A
Digital Input Capacitance - - 5 pF
DIGITAL OUTPUT (TTL)
Digital Output Voltage: High, V
OH
I
OH
= -2mA 2.4 - - V
Digital Output Voltage: Low, V
OL
I
OL
= 1mA - - 0.5 V
SWITCHING CHARACTERISTICS
Maximum Conversion Rate, f
C
DMUX Mode 120 - - MSPS
Aperture Jitter, t
AJ
- 10 - ps
Sampling Delay, t
DS
3 4.5 6 ns
Clock High Pulse Width, t
PW1
CLK 3.2 - - ns
Clock Low Pulse Width, t
PW0
CLK 3.2 - - ns
Reset Pulse Width, t
PWR
(Note 6) RESETN t x 2 - - ns
RESET Signal Setup Time, t
RS
RESETN-CLK 3.5 - - ns
RESET Signal Hold Time, t
RH
RESETN-CLK 0 - - ns
CLKOUT Output Delay, t
DCLK
(C
L
= 5pF) 3.5 7 9 ns
Data Output Delay (Note 6), t
DO1
t
DO2
DEMUX Mode (C
L
= 5pF) t t + 1 t + 2 ns
(C
L
= 5pF) 4.5 8 10 ns
Output Rise Time, t
r
0.8 to 2.0V (C
L
= 5pF) - 2 - ns
Output Fall Time, t
f
0.8 to 2.0V (C
L
= 5pF) - 2 - ns
DYNAMIC CHARACTERISTICS
Input Bandwidth V
IN
= 2V
P-P
, -3dB 150 - - MHz
S/N Ratio f
C
= 120 MSPS, f
IN
= 1kHz Full Scale,
DMUX Mode
- 46 - dB
f
C
= 120 MSPS, f
IN
= 29.999MHz Full Scale,
DMUX Mode
- 40 - dB
Electrical Specifications DV
CC1
,
2
, AV
CC
, DGND3 = +5V, DGND1, 2, AGND, DV
EE3
= 0V, V
RT
= 4V, V
RB
= 2V,
T
A
= 25
o
C (Continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
HI3026
5
Error Rate (Note 7) f
C
= 120 MSPS, f
IN
= 1kHz Full Scale,
DMUX Mode, Error > 16 LSB
- -
10
-12
TPS
f
C
= 120 MSPS, f
IN
= 29.999MHz
Full Scale, DMUX Mode, Error > 16 LSB
- -
10
-9
TPS
f
C
= 100 MSPS, f
IN
= 24.999MHz
Full Scale, Straight Mode, Error > 16 LSB
- -
10
-9
TPS
POWER SUPPLY
Supply Current, I
CC
125 145 185 mA
Supply Current, I
EE
0.4 0.6 0.8 mA
Power Consumption (Note 8), P
D
660 760 960 mW
NOTES:
4. R
REF
: Resistance value between V
RT
and V
RB
.
5. .
6. .
7. The unit of measure TPS: Times Per Sample.
8. .
Timing Diagrams
FIGURE 1. DEMUX MODE TIMING CHART (SELECT = V
CC
)
Electrical Specifications DV
CC1
,
2
, AV
CC
, DGND3 = +5V, DGND1, 2, AGND, DV
EE3
= 0V, V
RT
= 4V, V
RB
= 2V,
T
A
= 25
o
C (Continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
I
REF
V
RT
V
RB

R
REF
----------------------------- =
T
1
f
C
----- =
P
D
I
CC
I
EE
+ ( ) V
CC

V
RT
V
RB
( )
2
V
REF
------------------------------------- + =
N - 1
t
DS
t
PW1
t
PW0
N
N + 1
t
D02
N + 2
N + 3
N + 2 N
2V
0.8V
N - 2
t
DCLK
2V
0.8V
2V
0.8V
N - 3
2V
0.8V
N - 1
t
D01
t + 1ns
N - 1
RESET PULSE
CLK OUT
P2D0 TO D7
P1D0 TO D7
CLK
V
IN
t
t
PWR
HI3026
6
FIGURE 2. STRAIGHT MODE TIMING CHART (SELECT = GND)
FIGURE 3. ECL AND PECL SWITCHING LEVEL
Pin Descriptions
PIN NO SYMBOL I/O
TYPICAL
VOLTAGE LEVEL EQUIVALENT CIRCUIT DESCRIPTION
3, 10 AGND GND Analog Ground. Separated from the
digital ground.
5, 8 AV
CC
+5V (Typ) Analog Power Supply. Separated from
the digital power supply.
20, 29
32, 41
DGND1
DGND2
GND Digital Ground.
19, 30
31, 42
DV
CC1
DV
CC2
+5V (Typ) Digital Power Supply.
12 DGND3 +5V (Typ) (With a
Single Power Supply)
Digital Power Supply. Ground for ECL
input. -5V for PECL and TTL input.
GND (With Dual
Power Supplies)
Timing Diagrams
N - 1
N
N + 1
N + 2
N + 3
t
DS
t
PW1
t
PW0
N - 4
2.0V
0.8V
2.0V
0.8V
N - 5
N - 3
N - 4
N - 2
N - 3
N - 1
N - 2
N
N - 1
t
D02
8ns
2.0V
0.8V
t
DCLK
RESET PULSE
CLK OUT
(CLK IS INVERTED AND OUTPUT)
P2D0 TO D7
P1D0 TO D7
CLK
V
IN
t
V
ID
DGND3
V
IH
(MAX)
V
IL
V
TH
(DGND3 - 1.2V)
V
IH
V
IL
(MIN)
HI3026
7
1 DV
EE3
GND (With a Single
Power Supply)
Digital Power Supply. Ground for ECL
input. -5V for PECL and TTL input.
+5V (Typ) (With Dual
Power Supplies)
16, 17,
18
NC No Connect pin. Not connected with
the internal circuits.
13 CLK/E I ECL/PECL Clock Input.
14 CLK/NE I CLK/E Complementary Input. When left
open, this pin goes to the threshold
potential. Only CLK/E can be used for
operation, but complementary input is
recommended to attain fast and stable
operation.
48 RESETN/E I Reset Input. When the input is set to low
level, the built-in CLK frequency divider
circuit can be reset.
47 RESET/E I RESETN/E Complementary Input.
When left open, this pin goes to the
threshold voltage. Only RESETN/E
can be used for operation.
15 CLK/T I TTL Clock input.
46 RESETN/T I Reset Input. When left open, this input
goes to high level. When the input is
set to low level, the built-in CLK
frequency divider circuit can be reset.
44 INV I TTL Data Output Polarity Inversion Input.
When left open, this input goes to high
level. (See Table 1; I/O Correspondence
Table).
45 SELECT V
CC
or Ground Data Output Mode Selection. (See
Table 2; Operating Mode Table).
Pin Descriptions (Continued)
PIN NO SYMBOL I/O
TYPICAL
VOLTAGE LEVEL EQUIVALENT CIRCUIT DESCRIPTION
13 48
47 14
DGND3
DVEE3
1.2V
RR
R R
46 15
DV
CC1
1.5V
R
R/2
DGND1
DV
EE3
44
DV
CC1
DGND1
DV
EE3
45
DV
CC1
DGND1
DV
EE3
HI3026
8
11 V
RT
I 4.0V (Typ) Top Reference Voltage. Bypass to
AGND with a 1F tantal capacitor and
a 0.1F chip capacitor.
9 V
RM3
V
RB
+
(V
RT
- V
RB
)
Reference Voltage Mid Point. Bypass
to AGND with a 0.1F chip capacitor.
7 V
RM2
V
RB
+
(V
RT
- V
RB
)
Reference Voltage Mid Point. Bypass
to AGND with a 0.1F chip capacitor.
4 V
RM1
V
RB
+
(V
RT
- V
RB
)
Reference Voltage Mid Point. Bypass
to AGND with a 0.1F chip capacitor.
2 V
RB
I 2.0V (Typ) Bottom Reference Voltage. Bypass to
AGND with a 1F tantal capacitor and
a 0.1F chip capacitor.
6 V
IN
I V
RT
to V
RB
Analog Input.
33 to 40 P1D0 to
P1D7
O TTL Port 1 Side Data Output.
21 to 28 P2D0 to
P2D7
O Port 2 Side Data Output.
43 CLKOUT O Clock Output. (See Table 2; Operating
Mode Table).
Pin Descriptions (Continued)
PIN NO SYMBOL I/O
TYPICAL
VOLTAGE LEVEL EQUIVALENT CIRCUIT DESCRIPTION
11
9
7
4
2
R2
R/2
R
R
R
R
R
R
R/2
R1
COMPARATOR 1
COMPARATOR 63
COMPARATOR 64
COMPARATOR 127
COMPARATOR 128
COMPARATOR 191
COMPARATOR 192
COMPARATOR 255
3
4
---
2
4
---
1
4
---
6
AV
CC
DV
EE3
COMPARATOR
AV
CC
AGND
V
REF
21
33
43
40
28
DV
CC2
TO
TO
DGND2
DV
EE3
DGND1
DV
CC1
1
0
0
K
HI3026
9
Notes on Operation
The HI3026 is a high-speed A/D converter which is capable
of TTL, ECL and PECL level clock input. Characteristic
impedance should be properly matched to ensure optimum
performance during high-speed operation.
The power supply and grounding have a profound influence
on converter performance. The power supply and ground-
ing method are particularly important during high-speed
operation. General points for caution are as follows:
- The ground pattern should be as large as possible. It is
recommended to make the power supply and ground
patterns wider at an inner layer using a multi-layer
board.
- To prevent interference between AGND and DGND and
between AV
CC
and DV
CC
, make sure the respective pat-
terns are separated. To prevent a DC offset in the power
supply pattern, connect the AV
CC
and DV
CC
lines at one
point each, via a ferrite-bead filter. Shorting the AGND
and DGND patterns in one place immediately under the
A/D converter improves A/D converter performance.
- Ground the power supply pins (AV
CC
, DV
CC1
, DV
CC2
,
DV
EE3
) as close to each pin as possible with a 0.1F or
larger ceramic chip capacitor. (Connect the AV
CC
pin to
the AGND pattern and the DV
CC1
, DV
CC2
, DV
EE3
pins
to the DGND pattern).
- The digital output wiring should be as short as possible.
If the digital output wiring is long, the wiring capacitance
will increase, deteriorating the output slew rate and
resulting in reflection to the output waveform since the
original output slew rate is quite fast.
The analog input pin V
IN
has an input capacitance of
approximately 21pF. To drive the A/D converter with
proper frequency response, it is necessary to prevent per-
formance deterioration due to parasitic capacitance or
parasitic inductance by using a large capacity drive circuit;
keeping wiring as short as possible, and using chip parts
for resistors and capacitors, etc.
The V
RT
and V
RB
pins must have adequate bypass to pro-
tect them from high-frequency noise. Bypass them to
AGND with approximately 1F tantal capacitor and, 0.1F
capacitor. At this time, approximately DGND3 - 1.2V
voltage is generated. However, this is not recommended for
use as threshold voltage V
BB
as it is too weak.
When the digital input level is ECL or PECL level, ***/E pins
should be used and ***/T pins left open. When the digital
input level is TTL, ***/T pins should be used and III/E pins
left open.
TABLE 1. A/D CODE TABLE
V
IN
STEP
INV
1 0
D7 D0 D7 D0
V
RT
255 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
254 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1

V
RM2
128 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
127 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
V
RB
0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Test Circuits
FIGURE 4. CURRENT CONSUMPTION MEASUREMENT
CIRCUIT
FIGURE 5. INTEGRAL LINEARITY ERROR/DIFFERENTIAL
LINEARITY ERROR MEASUREMENT CIRCUIT
V
RT
V
IN
V
RB
AV
CC
DV
CC1
DV
CC2
DGND2
DGND1
AGND
DGND3
CLK/E
DV
EE3
4V
1.95V
2V
5MHz PECL
A A
5V 5V
I
CC
I
EE
A < B A > B
COMPARATOR
A8
TO
A1
B8
TO
B1
B0 A0
HI3026 BUFFER
CONTROLLER
DVM
000...00
TO
111..10
V
IN
8
0
8
1
-V
+V
S2
S1: ON WHEN A < B
S2: ON WHEN A > B
S1
-
+
HI3026
10
Operating Modes
The HI3026 has two types of operating modes which are selected with Pin 45 (SELECT).
DMUX Mode (See Application Circuits, Figures 18, 19, 20)
Set the SELECT pin to V
CC
for this mode. In this mode, the
clock frequency is divided by 2 in the IC, and the data is out-
put after being demultiplexed by this
1
/
2
frequency divided
clock. The
1
/
2
frequency divided clock, which has adequate
setup time and hold time for the output data, is output from
the CLKOUT pin.
When using multiple HI3026 units in parallel in this mode, dif-
ferences in the start timing of the
1
/
2
frequency divided clock
may cause operation as shown in the figure below. As a coun-
termeasure, the HI3026 is equipped with a function which
resets the
1
/
2
frequency divided clock. When resetting this
clock, the RESET pulse must be input to the RESET pin. See
the Timing Charts for the RESET pulse input timing. The A/D
converter can operate at f
C
(Min) = 120 MSPS in this mode.
Straight Mode (See Application Circuits, Figures 21, 22, 23)
FIGURE 6. ERROR RATE MEASUREMENT CIRCUIT
FIGURE 7. SAMPLING DELAY/APERTURE JITTER
MEASUREMENT CIRCUIT
NOTE: Where (LSB) is the deviation of the output codes when the
largest slew rate point is sampled at the clock which has exactly the
same frequency as the analog input signal, the aperture jitter t
AJ
is:
FIGURE 8. APERTURE JITTER MEASUREMENT METHOD
Test Circuits (Continued)
SIGNAL
SOURCE
COMPARATOR
A > B
PULSE
COUNTER
SIGNAL
SOURCE
HI3026 LATCH
+
1
/
8
LATCH
A
f
C
B
8
16 LSB
2V
P-P
SINE WAVE
4
-1kHz
V
IN
CLK CLK
f
C
LOGIC
ALALYZER
HI3026
V
IN
CLK
AMP
8
1024
SAMPLES
ECL
BUFFER
OSC1
: VARIABLE
OSC2
100MHz
f
R
100MHz
V
RT
V
RM2
V
RB
129
128
127
126
125
(LSB)

V
IN
CLK
V
IN
CLK
SAMPLING TIMING FLUCTUATION
(= APERTURE JITTER)
t
AJ
= /

t
-------


= /
256
2
---------- x 2f


.
TABLE 2. OPERATING MODE TABLE
OPERATING
MODE SELECT
MAXIMUM
CONVERSION RATE DATA OUTPUT CLOCK OUTPUT
DMUX Mode V
CC
120 MSPS Demultiplexed Output
60 MBPS
The input clock is
1
/
2
frequency
divided and output at 60MHz.
Straight Mode GND 100 MSPS Straight Output 100 MBPS The input clock is inverted and
output at 100MHz.
HI3026
11
Set the SELECT pin to GND for this mode. In this mode, data
output can be obtained in accordance with the clock frequency
applied to the A/D converter for applications which use the
clock applied to the A/D converter as the system clock.
The A/D converter can operate at f
C
(Min) = 100 MSPS in
this mode.
Digital Input Level and Supply Voltage Settings
The logic input level for the HI3026 supports ECL, PECL and
TTL levels.
The power supplies (DV
EE3
, DGND3) for the logic input
block must be set to match the logic input (CLK and RESET
signals) level.
TABLE 3. LOGIC INPUT LEVEL AND POWER SUPPLY SETTINGS
DIGITAL
INPUT
LEVEL DV
EE3
DGND3
SUPPLY
VOLTAGE
APPLICATION
CIRCUITS
ECL -5V 0V 5V Figures 18, 21
PECL 0V +5V +5V Figures 19, 22
TTL 0V +5V +5V Figures 20, 23
FIGURE 9. WHEN THE RESET PULSE IS NOT USED
FIGURE 10. WHEN THE RESET PULSE IS USED
HI3026
CLK
RESETN
A
HI3026
CLK
RESETN
B
8 BITS
CLK
CLKOUT
DATA
CLKOUT
DATA
8 BITS
CLK
HI3026
CLK
RESETN
A
HI3026
CLK
RESETN
B
8 BITS
CLK
CLKOUT
DATA
CLKOUT
DATA
8 BITS
CLK
RESET PULSE
RESET
PULSE
HI3026
12
Typical Performance Curves
FIGURE 11. CURRENT CONSUMPTION vs AMBIENT
TEMPERATURE CHARACTERISTICS
FIGURE 12. CURRENT CONSUMPTION vs CONVERSION RATE
CHARACTERISTICS RESPONSE
FIGURE 13. ANALOG INPUT CURRENT vs ANALOG INPUT
VOLTAGE CHARACTERISTICS
FIGURE 14. REFERENCE CURRENT vs AMBIENT
TEMPERATURE CHARACTERISTICS
FIGURE 15. SNR vs INPUT FREQUENCY RESPONSE FIGURE 16. ERROR RATE vs CONVERSION RATE
CHARACTERISTICS
170
160
150
140
130
-25 25 75
AMBIENT TEMPERATURE (
o
C)
C
U
R
R
E
N
T

C
O
N
S
U
M
P
T
I
O
N

(
m
A
)
170
160
150
140
130
0 60 120
CONVERSION RATE (MSPS)
C
U
R
R
E
N
T

C
O
N
S
U
M
P
T
I
O
N

(
m
A
)
f
IN
=
f
CLK
4
-1kHz
DMUX MODE
C
L
= 5pF
200
100
0
2 3 4
ANALOG INPUT VOLTAGE (V)
A
N
A
L
O
G

I
N
P
U
T

C
U
R
R
E
N
T

(

A
)
V
RT
= 4V
V
RB
= 2V
20
15
10
R
E
F
E
R
E
N
C
E

C
U
R
R
E
N
T

(
m
A
)
-25 25 75
AMBIENT TEMPERATURE (
o
C)
50
40
30
20
1 3 5 10 30 50
INPUT FREQUENCY (MHz)
S
N
R

(
d
B
)
f
C
= 120 MSPS
10
-6
10
-7
10
-8
10
-9
10
-10
120 140 160
CONVERSION RATE (MSPS)
E
R
R
O
R

R
A
T
E

(
T
P
S
)
f
IN
=
f
CLK
4
-1kHz
ERROR > 16 LSB
HI3026
13
FIGURE 17. MAXIMUM CONVERSION RATE vs AMBIENT TEMPERATURE CHARACTERISTICS
Application Circuits
FIGURE 18. DMUX ECL INPUT
Typical Performance Curves (Continued)
150
160
170
140
130
M
A
X
I
M
U
M

C
O
N
V
E
R
S
I
O
N

(
M
S
P
S
)
-25 25 75
AMBIENT TEMPERATURE (C
o
)
f
IN
=
f
CLK
4
-1kHz
ERROR > 16 LSB
ERROR RATE: 10
-9
TPS
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
P1D0 TO P1D7
8-BIT DIGITAL DATA
LATCH
DG
DG
+5V (D)
LATCH
P2D0 TO P2D7
8-BIT DIGITAL DATA
8-BIT DIGITAL DATA
8-BIT DIGITAL DATA
13 14 15 16 17 18 19 20 21 22 23 24
DG
+5V (D)
+5V (A)
2V
AG
AG
+5V (A)
4V
AG
AG
DG
ECL - CLK
ECL RESET PULSE
+5V (D)
DG
-5V (D)
AG
HI3026
14
FIGURE 19. DMUX PECL INPUT
FIGURE 20. DMUX TTL INPUT
Application Circuits (Continued)
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
P1D0 TO P1D7
8-BIT DIGITAL DATA
LATCH
DG
DG
+5V (D)
LATCH
P2D0 TO P2D7
8-BIT DIGITAL DATA
8-BIT DIGITAL DATA
8-BIT DIGITAL DATA
13 14 15 16 17 18 19 20 21 22 23 24
DG
+5V (D)
+5V (A)
2V
DG
AG
+5V (A)
4V
AG
AG
+5V (D)
PECL - CLK
PECL RESET PULSE
+5V (D)
DG
DG
AG
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
P1D0 TO P1D7
8-BIT DIGITAL DATA
LATCH
DG
DG
+5V (D)
LATCH
P2D0 TO P2D7
8-BIT DIGITAL DATA
8-BIT DIGITAL DATA
8-BIT DIGITAL DATA
13 14 15 16 17 18 19 20 21 22 23 24
DG
+5V (D)
+5V (A)
2V
AG
AG
+5V (A)
4V
AG
AG
+5V (D)
TTL - CLK
TTL RESET PULSE
+5V (D)
DG
DG
AG
HI3026
15
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-
able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
FIGURE 21. STRAIGHT ECL INPUT
Application Circuits (Continued)
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
P1D0 TO P1D7
8-BIT DIGITAL DATA
LATCH
DG
DG
+5V (D)
8-BIT DIGITAL DATA
13 14 15 16 17 18 19 20 21 22 23 24
DG
+5V (D)
+5V (A)
2V
AG
AG
+5V (A)
4V
AG
AG
ECL - CLK
+5V (D)
DG
-5V (D)
DG
ECL - TTL
DG
AG
HI3026
16
FIGURE 22. STRAIGHT PECL INPUT
FIGURE 23. STRAIGHT TTL INPUT
Application Circuits (Continued)
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
P1D0 TO P1D7
8-BIT DIGITAL DATA
LATCH
DG
DG
+5V (D)
8-BIT DIGITAL DATA
13 14 15 16 17 18 19 20 21 22 23 24
DG
+5V (D)
+5V (A)
2V
AG
AG
+5V (A)
4V
AG
AG
PECL - CLK
+5V (D)
DG
DG
DG
PECL - TTL
+5V(D)
AG
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
P1D0 TO P1D7
8-BIT DIGITAL DATA
LATCH
DG
DG
+5V (D)
8-BIT DIGITAL DATA
13 14 15 16 17 18 19 20 21 22 23 24
DG
+5V (D)
+5V (A)
2V
AG
AG
+5V (A)
4V
AG
AG
TTL - CLK
+5V (D)
DG
DG
DG
+5V(D)
AG
HI3026
17
FIGURE 24. STRAIGHT MODE TTL I/O (WHEN A SINGLE POWER SUPPLY IS USED)
Application Circuits (Continued)
12 11 10 9 8 7 6 5 4 3 2 1
25 26 27 28 29 30 31 32 33 34 35 36
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
CLK/E
CLKN/E
CLK/T
NC
NC
NC
DV
CC2
DGND2
P2D0
P2D1
P2D2
P2D3
RESETN/E
RESET/E
RESETN/T
SELECT
INV
CLKOUT
DV
CC2
DGND2
P1D7
P1D6
P1D5
P1D4
P
2
D
4
P
2
D
5
P
2
D
6
P
2
D
7
D
G
N
D
1
D
V
C
C
1
D
V
C
C
2
D
G
N
D
2
P
1
D
0
P
1
D
1
P
1
D
2
P
1
D
3
D
G
N
D
3
V
R
T
A
G
N
D
V
R
M
3
A
V
C
C
V
R
M
2
V
I
N
A
V
C
C
V
R
M
1
A
G
N
D
V
R
B
D
V
E
E
3
+ -
AG +5V (A)
AG
AG
ANALOG
INPUT
1F
+
AG
2V
AG
+
1F
10F
+
SHORT
SHORT
DG (D)
+5V
4V
10F
+
TTL CLK
(
L
S
B
)

P
2
D
0
P
2
D
1
P
2
D
2
P
2
D
3
P
2
D
4
P
2
D
5
P
2
D
6
(
M
S
B
)

P
2
D
7
(
L
S
B
)

P
1
D
0
P
1
D
1
P
1
D
2
P
1
D
3
P
1
D
4
P
1
D
5
P
1
D
6
(
M
S
B
)

P
1
D
7
SHORT THE ANALOG SYSTEM AND DIGITAL SYSTEM AT ONE POINT IMMEDIATELY
UNDER THE A/D CONVERTER. SEE THE NOTES ON OPERATION
IS THE CHIP CAPACITOR OF 0.1F.
+
-
+
-