Vertical scaling of carbon nanotube eld-effect transistors

using top gate electrodes

S. J. Wind,
a)
J. Appenzeller, R. Martel, V. Derycke, and Ph. Avouris
IBM T. J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598
Received 24 January 2002; accepted for publication 3 April 2002
We have fabricated single-wall carbon nanotube eld-effect transistors CNFETs in a conventional
metaloxidesemiconductor eld-effect transistor MOSFET structure, with gate electrodes above
the conduction channel separated from the channel by a thin dielectric. These top gate devices
exhibit excellent electrical characteristics, including steep subthreshold slope and high
transconductance, at gate voltages close to 1 Va signicant improvement relative to previously
reported CNFETs which used the substrate as a gate and a thicker gate dielectric. Our measured
device performance also compares very well to state-of-the-art silicon devices. These results are
observed for both p- and n-type devices, and they suggest that CNFETs may be competitive with Si
MOSFETs for future nanoelectronic applications. 2002 American Institute of Physics.
DOI: 10.1063/1.1480877
With the end to silicon transistor scaling in sight,
1
a great
deal of research activity is currently focused on identifying
alternatives which would enable continued improvements in
the density and performance of electronic information sys-
tems. Of the various material systems and structures being
investigated, carbon nanotubes CNTs have shown particu-
lar promise.
2,3
Toward the goal of assessing their potential
for future nanoelectronic technologies, we have fabricated
carbon nanotube eld-effect transistors CNFETs in a struc-
ture similar to that of conventional silicon metaloxide
semiconductor eld-effect transistors MOSFETs, with gate
electrodes above the conduction channel separated from the
channel by a thin 1520 nm SiO
2
dielectric, as shown
schematically in Fig. 1a. This geometry allows for opera-
tion at low gate voltage, and it also allows for the switching
of individual devices on the same substrate.
Most CNFETs reported to date use the conductive sub-
strate as a back-gate electrode, usually with gate dielectrics
of considerable thickness 100 nm or more. As a result,
high gate voltages are required to switch the devices on. In
addition, use of the substrate as a gate implies that all de-
vices are turned on simultaneously, precluding operation of
all but the most basic circuits. Recently, Bachtold et al.
4
re-
ported an improved back-gate structure with a very thin
25 nm gate dielectric and with individual eld-effect
transistor FET gating. Those devices did show low gate
voltage operation and individual switchability. However, the
bottom gate structure used in that work, as well as in other
previously published CNFET studies,
2,3,5,6
has an open ge-
ometry, in which the CNT is exposed to air. This presents an
electrostatic disadvantage in that the gate insulator capaci-
tance is diluted by the lower dielectric constant of the air
surrounding the CNT. In contrast, in the top gate geometry,
the CNT is completely embedded within the gate insulator,
offering the full advantage of the gate dielectric. A further
disadvantage of the open geometry is that exposure of CNTs
to air leads to p-type characteristics.
7
Our approach, on the
other hand, allows the fabrication of both n-type as well as
p-type devices. This becomes possible by virtue of an in situ
annealing step prior to the deposition of the gate dielectric
lm. As pointed out by Derycke et al.,
7
thermal treatment in
an inert atmosphere modies the metalnanotube interface at
the contacts and results in n-type behavior. An additional
advantage of the top gate structure is that with only slight
a
Electronic mail: sjwind@us.ibm.com
FIG. 1. a Schematic cross section of top gate CNFET showing the gate
and source and drain electrodes. b Output characteristic of a top gate
p-type CNFET with a Ti gate and a gate oxide thickness of 15 nm. The gate
voltage values range from 0.1 to 1.1 V above the threshold voltage,
which is 0.5 V. Inset: Transfer characteristic of the CNFET for V
ds

0.6 V.
APPLIED PHYSICS LETTERS VOLUME 80, NUMBER 20 20 MAY 2002
3817 0003-6951/2002/80(20)/3817/3/$19.00 2002 American Institute of Physics
Downloaded 21 May 2002 to 128.8.92.125. Redistribution subject to AIP license or copyright, see http://ojps.aip.org/aplo/aplcr.jsp
modication, it can be made suitable for high-frequency op-
eration, which is not possible with back-gated devices due to
the large overlap capacitance between the gate, source, and
drain. These features make the devices presented in this work
the most technologically relevant CNT transistors fabricated
so far, and they allow for a more direct comparison with
mainstream silicon-based MOSFETs. Finally, our device de-
sign allows us to compare the impact of a top gate with a
bottom gate structure on the same device in order to gain
further insight into the capacitive coupling of the gate and
the nanotube channel.
The main goal of this work is to characterize, in detail,
the performance of vertically scaled nanotube transistors.
Both p- and n-type top gate devices are included in our study.
The devices we have fabricated show excellent performance
characteristics when compared with previously reported CN-
FETs. We also compare our CNFETs with silicon devices.
We nd that when appropriately normalized for width, our
measured device characteristics compare well with those of
recently reported state-of-the-art silicon MOSFETs.
Device fabrication proceeded as follows: Single-crystal
Si substrates either p-type or n-type, with resistivities of
0.0050.01 cm, were cleaned and coated with 120 nm of
thermal SiO
2
. Single-wall nanotubes SWNTs produced by
laser ablation
8
were dispersed from a 1,2-dichloroethane so-
lution by spinning onto the substrates after mild sonication.
The density of the solution was adjusted to yield approxi-
mately one CNT in an area 55 m
2
. Atomic force mi-
croscopy of many devices of this type indicates the presence
of a single CNT or a CNT bundle comprised of a small
number of CNTs per device. Ti source and drain electrodes
were patterned by electron-beam lithography and liftoff. The
sourcedrain separation was 200300 nm.
Samples were annealed at 850 C for 100 s to form tita-
nium carbide at the metalnanotube interface, resulting in a
reduced contact resistance.
9
The top gate dielectric was then
deposited from a mixture of SiH
4
and O
2
at 300 C. The
deposited lm thickness was 1520 nm /5%. Contact
holes to the source and drain electrodes were opened in the
oxide lm, followed by a 0.5 h anneal at 600 C in N
2
to
densify the oxide. Gate electrodes were then patterned by
electron-beam lithography and liftoff using 50 nm Al or Ti,
followed by a forming gas anneal to reduce trapped charge at
the oxide interface. Figure 1a shows a cross-sectional sche-
matic of the top gate CNFET structure.
Electrical measurements were performed on the sample
devices using the top gate electrode with the substrate main-
tained at ground potential. Figure 1b shows the output char-
acteristic for a p-type CNFET with a Ti top gate and a gate
oxide of 15 nm. The device shows excellent turn on and
saturation at gate voltages 1 V. The maximum transconduc-
tance is 3.25 S, which is an extremely high value for a
CNFET device as compared to previously reported
CNFETs.
4,5
The inset in Fig. 1b shows the transfer charac-
teristic for the same device. The linearly extrapolated thresh-
old voltage is 0.5 V and the inverse subthreshold slope for
top gate operation is 130 mV/decade.
As these electrical results are exceptional for CNT-based
devices, we believe it is appropriate to gauge their perfor-
mance relative to the dc characteristics of state-of-the-art pla-
nar silicon MOSFETs. Table I shows key performance pa-
rameters for the CNFET shown in Fig. 1b and for two
recently published high performance Si p-channel devices: a
15 nm gate length MOSFET built on bulk Si reported by Yu
et al.,
10
which shows very high transconductance; and a 50
nm gate length device reported by Chau et al.,
11
which is
built using thin silicon-on-insulator SOI technology. The
restricted geometry of the thin SOI in the second device of-
fers a good comparison for the one-dimensional nanotube
channel. For this comparison, we focus on the current carry-
ing capabilities of the CNFET by normalizing the current per
unit width, using the CNT diameter 1.4 nm, which is the
only apparent length scale. We also assume at this point that
only one SWNT is present.
12
Since an optimum device lay-
out may require an array of CNTs, these results can be scaled
to give an appropriate total current per device, bearing in
mind that as the array becomes more densely packed, screen-
ing of the gate charge by neighboring nanotubes in the array
can reduce the actual current per tube by a factor of up to
2.
13
We nd that the CNFET is capable of approximately
three to four times higher drive current per unit width than
the Si p-type MOSFETs at a gate overdrive around 1 V, with
approximately two to four times higher transconductance.
This is particularly striking, since both the channel length
and gate oxide thickness are signicantly larger for the CN-
FET than for the silicon devices. We expect that further scal-
ing of the gatechannel capacitance via reductions in gate
dielectric thickness and/or higher dielectric constant materi-
als, along with reductions in gate length, will lead to addi-
tional improvements in CNT device performance. Thus, our
experimental results advocate strongly for CNTs as candi-
dates for future nanoelectronics technologies.
As mentioned earlier, CNFETs, which normally exhibit
p-type behavior, can exhibit n-type conduction after under-
going treatment at elevated temperatures. Adsorbed oxygen
is driven off from the source and drain contact regions, shift-
ing the Fermi level at the contacts and effectively lowering
the barrier for injection of electrons.
7,9
Samples in this work
were annealed at 425 C in N
2
just prior to deposition of the
gate oxide lm. After deposition of this lm, the CNTs are
protected from further effects of ambient gases, resulting in
stable n-type devices. Figure 2 shows the transfer character-
istic for a top gate n-type CNFET with an Al gate and a 20
nm gate oxide at V
ds
0.5 V. The device turns on nicely at a
gate voltage 1 V, with a threshold voltage of 0.3 V; the
subthreshold slope is 312 mV/decade. It is interesting to note
TABLE I. Comparison of key device performance parameters for a 260 nm
long top gate p-type CNFET, a 15 nm bulk Si p-type MOSFET,
a
and a 50
nm SOI p-type MOSFET.
b
p-type CNFET Ref. 10 Ref. 11
Gate length nm 260 15 50
Gate oxide thickness nm 15 1.4 1.5
V
t
V 0.5 0.1 0.2
I
ON
A/m
(V
ds
V
gs
V
t
1 V)
2100 265 650
I
OFF
nA/m 150 500 9
Subthreshold slope mV/dec 130 100 70
Transconductance S/m 2321 975 650
a
See Ref. 10.
b
See Ref. 11.
3818 Appl. Phys. Lett., Vol. 80, No. 20, 20 May 2002 Wind et al.
Downloaded 21 May 2002 to 128.8.92.125. Redistribution subject to AIP license or copyright, see http://ojps.aip.org/aplo/aplcr.jsp
that the different threshold voltages for the devices with Al
and Ti gates correspond well to the work function differences
between these metals 4.2 eV for Al and 3.9 eV for Ti
14
and
the CNT 4.5 eV.
15
In addition to top gate operation, our devices, built upon
conductive Si substrates with a 120 nm thick oxide, can
function as bottom gate devices as well. Figure 3 shows the
output characteristic of the device in Fig. 1b in bottom gate
operation. The device achieves similar on current to top gate
operation, but at gate voltages nearly 20 V above the thresh-
old voltage of 12.5 V. The maximum transconductance is
0.125 S. These values are similar to the performance
achieved in other back-gated CNFETs reported in
literature.
26
For comparison, we overlay in Fig. 3 two
curves from Fig. 1b gate operation. These curves overlay
nearly exactly. In fact, this is true for the entire range of
measured top and bottom gate voltages, indicating that the
conduction properties of the CNT are fundamentally the
same in either gate conguration. The average ratio of gate
overdrive voltages for each pair of overlying curves implies
a capacitance ratio between the top and bottom gates of 32.
While the bottom gate capacitance may be more greatly in-
uenced by the presence of trapped charge at the Si/SiO
2
interface, this ratio is still considerably greater than the ratio
expected from simple geometric considerations: 1.5 for a
cylinder-plane conguration, and 9 for a parallel plate con-
guration. We believe that a more complete picture of the
electrostatics, which would include effects due to the source
and drain contacts,
16
is required to explain the experimen-
tally observed difference.
In conclusion, we have fabricated both n-type and p-type
SWNT FETs with top gate electrodes in a conventional
MOSFET structure. Due to the relatively thin gate dielectric,
the electrical characteristics of these devices are superior to
previously reported CNFETs. The current carrying capability
is extremely high for CNT devices. Although many chal-
lenges remain before CNFETs can be considered ready for
real technological applications, our results indicate that their
potential performance for future nanoelectronics is indeed
very promising.
The authors thank J. J. Bucchignano for electron-beam
lithography, B. Ek for metal lm deposition and processing,
and R. M. Sicina for low-temperature oxide deposition. The
authors also thank S. Heinze and J. D. Tersoff for insightful
discussions and H.-S. P. Wong, R. G. Viswanathan, and T. N.
Theis for valuable input and support.
1
D. J. Frank, Proc. IEEE 89, 259 2001.
2
S. Tans, A. Verschueren, and C. Dekker, Nature London 393, 49 1998.
3
R. Martel, Appl. Phys. Lett. 73, 2447 1998.
4
A. Bachtold, P. Hadley, T. Nakashini, and C. Dekker, Science 294, 1317
2001.
5
R. Martel, Proceedings IEDM 2001, p. 159.
6
V. Derycke, R. Martel, J. Appenzeller, and P. Avouris, Nano Lett. 1, 453
2001.
7
V. Derycke, R. Martel, J. Appenzeller, and P. Avouris, Appl. Phys. Lett.
unpublished.
8
A. Thess, Science 273, 483 1996.
9
R. Martel, Phys. Rev. Lett. 87, 256805 2001.
10
B. Yu, Proceedings IEDM 2001, p. 937.
11
R. Chau, Proceedings IEDM 2001, p. 621.
12
Due to the presence of the top gate, we were unable to obtain a direct
measurement of the CNT diameter. However, the device characteristics
the steepness of the subthreshold slope in particularare consistent with
the behavior of a single SWNT device. CNFETs with more than a very
small number of nanotubes turn on gradually. Thus, the normalized val-
ues given represent an upper bound.
13
J. Guo, S. Goasguen, M. Lundstrom, and D. Datta private communica-
tion.
14
American Institute of Physics Handbook McGrawHill, New York,
1972.
15
H. Ago, J. Phys. Chem. B 103, 8116 1999; S. Suzuki, C. Bower, and Y.
Watanabe, Appl. Phys. Lett. 76, 4007 2000.
16
J. Appenzeller, J. Knoch, V. Derycke, R. Martel, S. Wind, and Ph. Avouris
unpublished.
FIG. 2. Transfer characteristic of a top gate n-type CNFET with an Al gate
and a gate oxide thickness of 20 nm. V
ds
0.5 V.
FIG. 3. Output characteristic of the p-type FET shown in Fig. 1b using the
conductive Si substrate as a gate open symbols. The gate oxide was 120
nm. The gate voltage values range from 3.5 to 19.5 V above the thresh-
old voltage, which is 12.5 V. For comparison, curves for top gate opera-
tion are shown closed symbols for gate overdrive values of 0.1 V and
0.5 V.
3819 Appl. Phys. Lett., Vol. 80, No. 20, 20 May 2002 Wind et al.
Downloaded 21 May 2002 to 128.8.92.125. Redistribution subject to AIP license or copyright, see http://ojps.aip.org/aplo/aplcr.jsp