POSTER PAPER

International Journal of Recent Trends in Engineering, Vol. 1, No. 4, May 2009

4

Capacitance-Voltage Measurement for
Characterization of a Metal-Gate MOS Process
Viranjay M. Srivastava
Jaypee University of Information Technology, Solan, Himachal Pradesh, India
viranjay@ieee.org


Abstract A procedure to characterize oxide and conductor
layers that are grown or deposited on semiconductor can be
done by studying the characteristics of a MOS capacitor
that is formed of the Conductor (metal)Insulator-
Semiconductor layer. For a capacitor formed of Metal-
Silicon dioxide-Silicon layers with an oxide thickness of
628 (measured optically), some of the calculated material
parameters were far from the expected values. Those errors
might be due several factors like a possible offset
capacitance of the probes due to improper contact with the
wafer which is measured using Visual Engineering
Environment Programming (VEE Pro), a possibility of
undesired deep depletion or due to hysteresis error. To solve
these problems, In this paper it is suggested to recalibrate
the probes, vary the voltage with smaller increments and
perform the measurements by varying the voltage from
+5 V to -5 V and then back to +5 V again and also varying
the frequency from 10 KHz to 1.2 MHz.

Index Terms Capacitance-voltage curve, Capacitance-
frequency curve, Flat band voltage, MOS Capacitor,
VEE Pro, VLSI
I. INTRODUCTION
Suppose we build a parallel plate capacitor, where one
plate is metal, another plate is a semiconductor (e.g.
weakly doped silicon), and the insulator is SiO
2
. Such a
device is called a MOS (metal-oxide-semiconductor)
capacitor. The metal plate is called the gate and is not
always built out of metal. Nowadays, gates are made
from heavily doped polycrystalline silicon (or
polysilicon or just poly). Polysilicon does not have a
rigid crystal lattice and conducts current freely, acting
almost like a metal.
Since the study of MOS capacitors involve material
that is basic in the understanding of MOS transistors
which are the main building blocks in the fabrication of
electronic devices. That is because the gate of MOS
transistor behaves like the MOS capacitor. The study of
the characteristics of those capacitors also enables the
characterization of the layers constituting them [1].
Micro capacitors are created by growing an insulator
on a semiconductor and a conductor on top of that, with
proper wiring and connection elements. The most
common MOS capacitors are formed by growing silicon
dioxide on silicon and depositing metal on top of the
oxide. The usual procedure for characterizing those
capacitors and the material properties of the layers
forming them is the Capacitance-Voltage (C-V) curve
and Capacitance-Frequency (C-F) curve method which
provides the variation of the capacitance with voltage,
applied between the metal and silicon layers, for the three
main regions of operation of the capacitor (accumulation,
depletion and inversion regions).
Using the plot of Capacitance versus Voltage (C-V)
and Capacitance versus Frequency (C-F), we can identify
material properties and calculate many of its parameter.
In this research, we look at the one of the measurement
result and the consequent calculated parameters of the
wafer layer properties, which were found to be different
from the expected. This research will point out the
probable measurement errors and the possible causes of
those errors and suggest the solutions that would
eliminate those causes or diminish their effects [1].
II. EXPERIMENTS
Similar size MOS capacitors were fabricated on a 4
inch diameter & 800 microns thick N-type silicon wafer
and the grown layers were characterized by C-V, C-F and
sheet resistance measurements.
To fabricate metal-oxide-semiconductor, the silicon
wafers were cleaned by following the standard cleaning
procedure to remove insoluble organics and metallic
contaminants. After that, a layer of oxide, approximately
650 thick, was grown on the silicon wafers using a dry
oxidation process at 950
o
C for 2 hour, with a pre-ramp
and post-ramp of 800
o
C with N
2
(12) & O
2
(32). For top
layer we will use Aluminum due to its ease of processing,
ability to reduse native SiO
2
, which is always present in
silicon wafers, exposed to atmosphere and its low
resistivity. About 2000 of aluminium was then
deposited over the oxide layer using a sputtering [2, 3].
Various techniques are used to increase the sputtering
rates, use of magnetic field near the target to increase the
generation of ions. Introduction of electrons by the use of
an electron gun as a third electrode was also tried.
The fabricated capacitors electrically tested to
characterize the material and to inspect the device
performance. The variation of the capacitance (C) with
gate voltage (V
G
) ranging from -5.0 Volts to +5.0 Volts
and the capacitance with frequency ranging from
10 KHz to 1.2 MHz of a 100 m x 100 m capacitor are
shown in following figuers, where Fig. 1 and Fig. 3 are
curves taken before heating and Fig. 2 and Fig. 4 are after
heating the MOS device. For the simplicity, we calculate
the parameters for only one curve and disscuss for both
curves.
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International Journal of Recent Trends in Engineering, Vol. 1, No. 4, May 2009
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For a relatively thick oxide (>600 ), extracting the
oxide thickness is fairly simple. The oxide capacitance
(C
OX
) is the high-frequency capacitance when the device
is biased for strong accumulation. In the strong
accumulation region, the MOS capacitor (MOS-C) acts
like a parallel plate capacitor and the oxide thickness may
be calculated from C
ox
and the gate area using the
following equation:
ox
ox
ox
T A
C

= (1)
Here A is the gate area of metal = 10
-2
cm
2
,

ox
= 34.515*10
-14
F-cm
-1
,
C
ox
is oxide capacitance measured by C-V curve for
Accumulation region = 5.202 pF by Fig. 1, So after the
calculation of (1), value of T
ox
comes 675 .
However, the measured oxide thickness using the
UV method was 628 . So the capacitance measurement


Figure 1. Capacitance vs Gate Voltage (before heating)


Figure 2. Capacitance vs Gate Voltage (after heating)
seems to be low thus giving a thickness value greater
than the actual value.
Next we look at the inversion region, where the total
capacitance per unit area (C
a
,
min
) is the series combination
of the oxide capacitance and the steady minimum
depletion capacitance and the inversion capacitance per
unit area is given by (2) and (3) [4].
1
1
,min
1
2(2 )
Si D
a
ox
q N
C
C

= +





(2)

ln
D
i
N kT
q n

=


(3)


Figure 3. Capacitance vs Frequency (before heating)

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Figure 4. Capacitance vs Frequency (after heating)
Using (2) and (3) in iterative manner [4] with the help
of MATLab [5], we can calculate the doping
concentration of the silicon substrate to be
N
D
= 1.0x10
15
per cm
3
which corresponds to a resistivity
of about 4.1 -cm according to the graph in Fig. 5, which
is pretty higher than expected. This relatively high
resistivity is a result of a relatively low calculated N
D
.
Which is the result of a low measured C
a
,
min
. So again,
we find that our capacitance readings lower than
expected.
From this point forth all calculations are based on the
substrate dopant concentration and are found to be not as
expected.
Now one can identify flat band voltage V
FB
. One way
is to use the flatband capacitance method. In this method,
the ideal value of the flatband capacitance (C
FB
) is
calculated using following (4) and (5). Once the value of
C
FB
is known, the value of V
FB
can be obtained from the
data of C-V curve, by interpolating the closest gate-to-
substrate (V
GS
) values [6, 7].
2
S
D
x
kT
q N

= (4)
Where kT is the thermal energy at room temperature=
4.046 10
21
J, and N
X
= N
A
or N
X
= N
D
and
D
is the
extrinsic Debye length.
Equation (4) calculates the Debye length parameter
() that is used in (5). Based on the doping profile, the
calculation of requires one of the following doping
concentrations, N at 90% of W
MAX
[8], I can put N
A
(bulk
doping concentration for a p-type, acceptor material), or a
N
D
(bulk doping concentration for an n-type, donor
material).
The flatband capacitance method is invalid when the


Figure 5. Electrical resistivity of Silicon vs impurity dopant
concentration for N-type and P-type Si [4]
interfaces trap charge density (D
IT
) becomes very large
(10
12
10
13
per cm
2
or greater). Now for flatband
condition,
OX
OX
C . /
C . /
S D
FB
S D
A
C
A

=
+
(5)
Where C
FB
is the flatband capacitance (pF), C
OX
is the
oxide capacitance = 5.202 pF,
S
is the permittivity of the
substrate material =11.7*8.85*10
-14
Fcm
-1
and A is the
gate area (cm
2
), so by solving (4) and (5), I got the value
of
D
=1.279*10
-5
cm as well as C
FB
= 3.167 pF.
This C
FB
is much less than the ones calculated based
on C
a
,
min
= 5.202 pF.
The extrinsic Debye length is an idea borrowed from
plasma physics [6]. In semiconductors, majority carriers
can move freely. The motion is similar to plasma. Any
electrical interaction has a limited range. The Debye
length is used to represent this interaction range.
Essentially, the Debye length indicates how far an
electrical event can be sensed within a semiconductor.
III. RESULTS AND DISCUSSION
There are various causes of the errors in measurement.
However, the most probable cause is the improper
contact of the probes with the polysilicon capacitor
surface and the solution obviously is making sure of that
the probe tips are in good contact with the wafer before
proceeding with the measurement.
Another possiblity is that the heating temperature for
MOS device should approximatly 200
o
C, because at
lower temperature effect on the oxide charges will be
negligble whereas at high temperature arrangement of
oxide charges will perturb. To solve this problem, take
the two readings of C-V curve one before heating the
device and other reading after heating, so that we can
avoid the dislocation of charges.
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A bit improbable, is that the probes could have an
internal capacitances of their own that has not been
accounted in the software of the machine, so the machine
would actually be reading the series equivalent
capacitance of its probes and the wafer capacitors, to
solve that problem, the machine should be calibrated
using reference wafers whose properties are well known.
A fourth probable cause of the errors in measurement
could be that the rate at which the voltage is varied is
large so that we enter the deep depletion region resulting
in a lower inversion capacitance reading, to avoid this,
we should vary the gate voltage at a lower rate [1].
The readings and calculation of the above said
working regions are shown in the experiment details with
readings which are taken from the data stored, produced
after the execution of VEE programming [9, 10]. This
result is also verified by the SUPREM simulator.
IV. CONCLUSION
Based on the C-V and C-F curve, characterization of a
MOS capacitor which resulted in erroneous values of
material parameters, mainly the substrate dopant
concentration, on which most of the other parameters are
based. And we attributed those errors to incorrect
measurement of the capacitance variation particularly the
inversion minimum capacitance of the capacitor.
We also identified the improper contact of the probes
with the wafer surface as the most probable cause of that
along with the possibility of going unintentionally into
deep depletion or having the equipment improperly
calibrated.
ACKNOWLADGEMENT
The author would like to thank Ms. Rejeena R.Y.,
Fabrication Laboratory, BEL, Bangalore, India where the
devices were made. The author wants to thank Prof. A.B.
Bhattachharaya, Jaypee University, Noida, India and Mr.
Peeyush Tripathi, IBM, Bangalore, India for many
insightful discussions. The author also wants to thank
Ms. Aprna Tripathi, Banasthali University, Jaipur,
Rajasthan, India and Prof. Anshuman Sharma,
Department of International Business Administration,
College of Applied Science, IBRI, Ministry of Higher
Education, Sultanate of Oman for support from their site.
REFERENCES
[1] J.D.Plummer, M.D.deal, P.B.Griffin, Silicon VLSI
Technology, Upper Saddle River, New Jersey, Prentice
Hall Inc. 2000.
[2] S.M.Sze, VLSI Technology, p.p. 381,2
nd
ed., Tata
McGraw Hill, 2003.
[3] S.Gandhi,VLSI Fabrication Principles, Silicon and
Gallium Arsenide John Wiley & Sons, 2002
[4] Koichi Kato, Kenji, Numerical analysis of switching
characteristics in SOI MOSFET, IEEE transaction on
electron devices, vol. 33, pp. 133-139, February 1986
[5] A.I.Akinwande, IC Lab Testing, unpublished.
[6] Sze, S.M., Physics of Semiconductor Devices, 2
nd

edition, Wiley, New York, 1985.
[7] Thamos J. Mego, On line C-V doping profile
measurement of low dose ion implant, IEEE transaction
on electron devices, vol. 27, no.12, pp.1168-1173,
December 1980.
[8] Thamos J. Mego, Guidelines for Interpreting CV data,
Solid State Technology, p.p. 159-163, May 1990.
[9] Agilent VEE pro users Guide", Agilent Company.
[10] Viranjay M. Srivastava, Relevance of VEE Programming
for Measurment of MOS Device Parameter, IEEE
Advanced Computing Conference, India, March 2009, in
press.
Viranjay M. Srivastava (M08)
received the Bachelor degree in
Electronics and Instrumentation
Engineering from the Rohilkhand
University, Bareilly, India and the
Master degree from VLSI Design
Department, Center for Development
of Advanced Computing (C-DAC),
Noida, India and presently pursuing
his doctorate in the field of microelectronics.
He was with the Semiconductor Process and Wafer
Fabrication Center of BEL Laboratories, Bangalore, India,
where he worked on characterization of MOS devices,
fabrication of devices and development of circuit design. He
joined Electronics and Communication Engineering Department
as a faculty, Saroj Educational Group, Lucknow in 2002, where
he becomes a head of department in 2006. Currently he is a
faculty in Jaypee University of Information Technology, Solan,
Himachal Pradesh, India.
His research and teaching interests include VLSI design
and CAD with particular emphasis in low-power design, Chip
designing, VLSI testing and verification. He is member of
IEEE, ACEEE and IACSIT. He has published many papers in
refereed journals and conferences, and is author of the book,
VLSI Technology, Kamal Publishing House, Kanpur, India.

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