Datasheet PDF

Cool SET
- F3R
I CE3BR1065JF
Of f - Li ne SMPS Cur r ent Mode
Cont r ol l er wi t h i nt egr at ed 650V
Cool MOS

and St ar t up cel l
( f r equency j i t t er Mode) i n Ful l Pak
N e v e r s t o p t h i n k i n g .
Power Management & Suppl y
Ver si on 2. 0, 11 Sep 2008
Edition 2008-09-11
Published by
Infineon Technologies AG,
81726 Munich, Germany,
2008 Infineon Technologies AG.
All Rights Reserved.
Legal disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
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be endangered.
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www.infineon.com
CoolMOS
, CoolSET
are trademarks of Infineon Technologies AG.

CoolSET
-F3R
ICE3BR1065JF
Revision History: 2008-09-11 Datasheet
Previous Version: 0.2
Page Subjects (major changes since last revision)
15 Add max. limitation for C
BK
capacitance
17,18 Revise description of protection mode. Add constrains of 25.5V Vcc OVP
19 Revise max. voltage for V
FB
, V
CS
and V
BA
19 Revise I
D_Puls
to T
j
=125C and add the avalanche rating
23 Add Drain Source Avalanche Breakdown Voltage
24~28 Add typical controller performance characteristics
29,30 Add typical CoolMOS
performance characteristics
31 Add input power curve
32 Revise outline dimension
Type Package V
DS
F
OSC
R
DSon
1)
1)
typ @ T
j
=25C
230VAC 15% 85-265 VAC
ICE3BR1065JF PG-TO220-6-247 650V 67kHz 1.0 178
2)
2)
Calculated maximum input power in an open frame design at T
a
=50C, T
j
=125C and R
thSA
(external heatsink) = 2.7K/W. Refer to input power curve for
other T
a
120W
2)

CoolSET
-F3R
ICE3BR1065JF
Version 2.0 3 11 Sep 2008
Off-Line SMPS Current Mode Controller with
integrated 650V CoolMOS

and Startup cell
(frequency jitter Mode) in FullPak
PG-TO220FS-6
PG-TO220-6-247
Product Highlights
TO220 FullPak with low Rdson MOSFET for high power application
Active Burst Mode to reach the lowest Standby Power Requirements
< 100mW
Auto Restart protection for overload, overtemperature, overvoltage
External auto-restart enable function
Built-in soft start and blanking window
Extendable blanking Window for high load jumps
Built-in frequency jitter and soft driving for low EMI
Green Mould Compound
Pb-free lead plating; RoHS compliant
CVCC
CBulk
Converter
DC Output
+
Snubber
Power Management
PWMController
Current Mode
85 ... 270 VAC
Typical Application
RSense
BA
FB
GND
Active Burst Mode
Auto Restart Mode
Control
Unit
-
CS
VCC
Startup Cell
Precise LowTolerance Peak
Current Limitation
Drain
CoolSET
-F3R
( Jitter )
CoolMOS
Description
The CoolSET
-F3R FullPak is the enhanced version of

CoolSET
-F3 and targets for the Off-Line Adapters and

high power range SMPS in DVD R/W, DVD Combi, set top
box, etc. It has a wide Vcc range to 25V by adopting the
BiCMOS technology. With the merit of Active Burst Mode, it
can achieve the lowest Standby Power Requirements
(<100mW) at no load and V
in
= 270VAC. Since the
controller is always active during the Active Burst Mode, it
is an immediate response on load jumps and leads to <1%
voltage ripple voltage at output. In case of protection for
Overtemperature, Overvoltage, Open loop and Overload
conditions, it would enter Auto Restart Mode. Thanks for the
internal precise peak current limitation, it can provide
accurate information to optimize the dimension of the
transformer and the output diode. The built-in blanking
window can provide sufficient buffer time before entering
the Auto Restart Mode. In case of longer blanking time, a
simply addition of capacitor to BA pin can serve the
purpose. Furthermore, the built-in frequency jitter function
can effectively reduce the EMI noise and further reduce the
scale of input filter. The component counts can further be
reduced with the various built-in functions such as soft start,
blanking time and frequency jitter.
Features
650V avalanche rugged CoolMOS
with built-in
Startup Cell
Active Burst Mode for lowest Standby Power
Fast load jump response in Active Burst Mode
67kHz internally fixed switching frequency
Auto Restart Protection Mode for Overload,
Open Loop, VCC Undervoltage,
Overtemperature & Overvoltage
Built-in Soft Start
Built-in blanking window with extendable
blanking time for short duration high current
External auto-restart enable pin
Max Duty Cycle 75%
Overall tolerance of Current Limiting < 5%
Internal PWM Leading Edge Blanking
BiCMOS technology provide wide VCC range
Built-in Frequency jitter and soft driving for low
EMI
CoolSET
-F3R
ICE3BR1065JF
Table of Contents Page

1 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.1 Pin Configuration with PG-TO220-6-247 . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.2 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2 Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.3 Improved Current Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.3.1 PWM-OP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.3.2 PWM-Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.4 Startup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.5 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.5.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.5.2 PWM-Latch FF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.5.3 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6.1 Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.6.2 Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.7 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.7.1 Basic and Extendable Blanking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.7.2 Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.7.2.1 Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.7.2.2 Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.7.2.3 Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.7.3 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.7.3.1 Auto Restart mode with extended blanking time . . . . . . . . . . . . . . . . .17
3.7.3.2 Auto Restart without extended blanking time . . . . . . . . . . . . . . . . . . .18
4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3.1 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3.2 Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.3.3 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.3.4 Soft Start time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.3.5 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.3.6 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.3.7 CoolMOS
Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5 Typical Controller Performance Characteristics . . . . . . . . . . . . . . . . . .24
CoolSET
-F3R
ICE3BR1065JF
Table of Contents Page

6 Typical CoolMOS
Performance Characteristics . . . . . . . . . . . . . . . . . .29

7 Input Power Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
8 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
9 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
10 Schematic for recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . .34

CoolSET
-F3R
ICE3BR1065JF
Pin Configuration and Functionality

1 Pin Configuration and Functionality
1.1 Pin Configuration with PG-TO220-6-
247
Figure 1 Pin Configuration PG-TO220-6-247
(front view)
1.2 Pin Functionality
Drain (Drain of integrated CoolMOS
)
Pin Drain is the connection to the Drain of the internal
CoolMOS
and the HV of the startup cell.

CS (Current Sense)
The Current Sense pin senses the voltage developed
on the series resistor inserted in the source of the
integrated CoolMOS
. If CS voltage reaches the

internal threshold of the Current Limit Comparator, the
Driver output is immediately switched off. Furthermore
the current information is provided for the PWM-
Comparator to realize the Current Mode.
BA (extended Blanking & Auto-restart enable)
The BA pin combines the functions of extendable
blanking time for over load protection and the external
auto-restart enable. The extendable blanking time
function is to extend the built-in 20 ms blanking time by
adding an external capacitor at BA to ground. The
external auto-restart enable function is an external
access to stop the gate switching and force the IC to
enter auto-restart mode. It is triggered by pulling down
the BA pin to less than 0.33V.
VCC (Power Supply)
The VCC pin is the positive supply of the IC. The
operating range is between 10.5V and 25V.
GND (Ground)
The GND pin is the ground of the controller.
FB (Feedback)
The information about the regulation is provided by the
FB Pin to the internal Protection Unit and to the internal
PWM-Comparator to control the duty cycle. The FB-
Signal is the only control signal in case of light load at
the Active Burst Mode.
Pin Symbol Function
1 Drain
650V
1)
CoolMos

Drain
1)
at T
j
=110C
2 CS Current Sense/
650V
1)
CoolMOS
Source
3 BA extended Blanking & external
Auto Restart enable
4 VCC Controller Supply Voltage
5 GND Controller Ground
6 FB Feedback
Package PG-TO220-6-247
1
D
r
a
i
n
2 3 4 5 6
C
S
B
A
V
C
C
G
N
D
F
B
CoolSET
-F3R
ICE3BR1065JF
Representative Blockdiagram


2 Representative Blockdiagram
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CoolSET
-F3R
ICE3BR1065JF
Functional Description

3 Functional Description
All values which are used in the functional description
are typical values. For calculating the worst cases the
min/max values which can be found in section 4
Electrical Characteristics have to be considered.
3.1 Introduction
CoolSET
-F3R FullPak is the further development of

the CoolSET
-F3 for high power application. The

particular enhanced features are built-in features for
soft start, blanking window and frequency jitter. It also
provides the flexibility to increase the blanking window
by simply adding capacitance in BA pin. However, the
proven outstanding features in CoolSET
-F3 are
remained.
The intelligent Active Burst Mode at Standby Mode can
effectively obtain the lowest Standby Power at
minimum load and no load condition. After entering the
burst mode, there is still a full control of the power
conversion by the secondary side via the same
optocoupler that is used for the normal PWM control.
The response on load jumps is optimized. The voltage
ripple on V
out
is minimized. V
out
is on well controlled in
this mode.
The usually external connected RC-filter in the
feedback line after the optocoupler is integrated in the
IC to reduce the external part count.
Furthermore a high voltage Startup Cell is integrated
into the IC which is switched off once the Undervoltage
Lockout on-threshold of 18V is exceeded. This Startup
Cell is part of the integrated CoolMOS
. The external
startup resistor is no longer necessary as this Startup
Cell is connected to the Drain. Power losses are
therefore reduced. This increases the efficiency under
light load conditions drastically.
This version is adopting the BiCMOS technology and it
can increase design flexibility as the Vcc voltage range
is increased to 25V.
For this full package version, the soft start is a built-in
function. It is set at 20ms. Then it can save external
component counts.
There are 2 modes of blanking time for high load
jumps; the basic mode and the extendable mode. The
blanking time for the basic mode is pre-set at 20ms
while the extendable mode will increase the blanking
time at basic mode by adding external capacitor at the
BA pin. During this time window the overload detection
is disabled. With this concept no further external
components are necessary to adjust the blanking
window.
In order to increase the robustness and safety of the
system, the IC provides Auto Restart protection mode.
The Auto Restart Mode reduces the average power
conversion to a minimum under unsafe operating
conditions. This is necessary for a prolonged fault
condition which could otherwise lead to a destruction of
the SMPS over time. Once the malfunction is removed,
normal operation is automatically recovered after the
next Start Up Phase.
The internal precise peak current limitation reduces the
costs for the transformer and the secondary diode. The
influence of the change in the input voltage on the
power limitation can be avoided together with the
integrated Propagation Delay Compensation.
Therefore the maximum power is nearly independent
on the input voltage which is required for wide range
SMPS. There is no need for an extra over-sizing of the
SMPS, e.g. the transformer or the secondary diode.
Furthermore, this full package version implements the
frequency jitter mode to the switching clock such that
the EMI noise will be effectively reduced.
3.2 Power Management
Figure 3 Power Management
The Undervoltage Lockout monitors the external
supply voltage V
VCC
. When the SMPS is plugged to the
main line the internal Startup Cell is biased and starts
to charge the external capacitor C
VCC
which is
connected to the VCC pin. This VCC charge current is
controlled to 0.9mA by the Startup Cell. When the V
VCC
exceeds the on-threshold V
CCon
=18V the bias circuit
are switched on. Then the Startup Cell is switched off
by the Undervoltage Lockout and therefore no power
Internal Bias
Voltage
Reference
Power Management
5.0V
Undervoltage Lockout
18V
10.5V
Power-Down Reset
Active Burst
Mode
Auto Restart
Mode
Startup Cell
VCC Drain
CoolMOS
Soft Start block

CoolSET
-F3R
ICE3BR1065JF

losses present due to the connection of the Startup Cell
to the Drain voltage. To avoid uncontrolled ringing at
switch-on a hysteresis start up voltage is implemented.
The switch-off of the controller can only take place after
Active Mode was entered and V
VCC
falls below 10.5V.
The maximum current consumption before the
controller is activated is about 150A.
When V
VCC
falls below the off-threshold V
CCoff
=10.5V,
the bias circuit is switched off and the soft start counter
is reset. Thus it is ensured that at every startup cycle
the soft start starts at zero.
The internal bias circuit is switched off if Auto Restart
Mode is entered. The current consumption is then
reduced to 250A.
Once the malfunction condition is removed, this block
will then turn back on. The recovery from Auto Restart
Mode does not require re-cycling the AC line.
When Active Burst Mode is entered, the internal Bias is
switched off most of the time in order to reduce the
current consumption below 500A.
3.3 Improved Current Mode
Figure 4 Current Mode
Current Mode means the duty cycle is controlled by the
slope of the primary current. This is done by comparing
the FB signal with the amplified current sense signal.
Figure 5 Pulse Width Modulation
In case the amplified current sense signal exceeds the
FB signal the on-time t
on
of the driver is finished by
resetting the PWM-Latch (see Figure 5).
The primary current is sensed by the external series
resistor R
Sense
inserted in the source of the integrated
CoolMOS
. By means of Current Mode regulation, the

secondary output voltage is insensitive to the line
variations. The current waveform slope will change with
the line variation, which controls the duty cycle.
The external R
Sense
allows an individual adjustment of
the maximum source current of the integrated
CoolMOS
.
To improve the Current Mode during light load
conditions the amplified current ramp of the PWM-OP
is superimposed on a voltage ramp, which is built by
the switch T2, the voltage source V1 and a resistor R1
(see Figure 6). Every time the oscillator shuts down for
maximum duty cycle limitation the switch T2 is closed
by V
OSC
. When the oscillator triggers the Gate Driver,
T2 is opened so that the voltage ramp can start.
In case of light load the amplified current ramp is too
small to ensure a stable regulation. In that case the
Voltage Ramp is a well defined signal for the
comparison with the FB-signal. The duty cycle is then
controlled by the slope of the Voltage Ramp.
By means of the time delay circuit which is triggered by
the inverted V
OSC
signal, the Gate Driver is switched-off
until it reaches approximately 156ns delay time (see
Figure 7). It allows the duty cycle to be reduced
continuously till 0% by decreasing V
FB
below that
threshold.
x3.3
PWM OP
Improved
Current Mode
0.68V

C8
PWM-Latch
CS
FB
R
S
Q
Q
Driver
Soft-Start Comparator
t
FB
Amplified Current Signal
t
on
t
0.68V
Driver
CoolSET
-F3R
ICE3BR1065JF

Version 2.0 10 11 Sep 2008
Figure 6 Improved Current Mode
Figure 7 Light Load Conditions
3.3.1 PWM-OP
The input of the PWM-OP is applied over the internal
leading edge blanking to the external sense resistor
R
Sense
connected to pin CS. R
Sense
converts the source
current into a sense voltage. The sense voltage is
amplified with a gain of 3.3 by PWM OP. The output of
the PWM-OP is connected to the voltage source V
1
.
The voltage ramp with the superimposed amplified
current signal is fed into the positive inputs of the PWM-
Comparator C8 and the Soft-Start-Comparator (see
Figure 6).
3.3.2 PWM-Comparator
The PWM-Comparator compares the sensed current
signal of the integrated CoolMOS
with the feedback

signal V
FB
(see Figure 8). V
FB
is created by an external
optocoupler or external transistor in combination with
the internal pull-up resistor R
FB
and provides the load
information of the feedback circuitry. When the
amplified current signal of the integrated CoolMOS
exceeds the signal V

FB
the PWM-Comparator switches
off the Gate Driver.
Figure 8 PWM Controlling
PWM OP
0.68V
10k
Oscillator
C8
T
2
R
1
FB
PWM-Latch
V
1
Gate Driver
Voltage Ramp
V
OSC
time delay
circuit (156ns)

X3.3
PWM Comparator
t
t
V
OSC
0.68V
FB
t
max.
Duty Cycle
Gate Driver
Voltage Ramp
156ns time delay
X3.3
PWM OP
Improved
Current Mode
PWM Comparator
CS
5V
C8
0.68V
FB
Optocoupler
R
FB
PWM-Latch
CoolSET
-F3R
ICE3BR1065JF

Version 2.0 11 11 Sep 2008
3.4 Startup Phase
Figure 9 Soft Start
In the Startup Phase, the IC provides a Soft Start
period to control the primary current by means of a duty
cycle limitation. The Soft Start function is a built-in
function and it is controlled by an internal counter.
.
Figure 10 Soft Start Phase
When the V
VCC
exceeds the on-threshold voltage, the
IC starts the Soft Start mode (see Figure 10).
The function is realized by an internal Soft Start
resistor, an current sink and a counter. And the
amplitude of the current sink is controlled by the
counter (see Figure 11).
Figure 11 Soft Start Circuit
After the IC is switched on, the V
SOFTS
voltage is
controlled such that the voltage is increased step-
wisely (32 steps) with the increase of the counts. The
Soft Start counter would send a signal to the current
sink control in every 600us such that the current sink
decrease gradually and the duty ratio of the gate drive
increases gradually. The Soft Start will be finished in
20ms (t
Soft-Start
) after the IC is switched on. At the end of
the Soft Start period, the current sink is switched off.
Figure 12 Gate drive signal under Soft-Start Phase
Soft-Start
Comparator
Soft Start
&
G7
C7
Gate Driver
0.68V
x3.3
PWM OP
CS
Soft Start counter
Soft Start
S
o
f
t

S
t
a
r
t

f
i
n
i
s
hSoftS
V
SoftS
V
SoftS2
V
SoftS1
5V
R
SoftS
Soft Start
Counter
I 2I 4I
SoftS
8I 32I
t
V
SOFTS32
V
SoftS
Gate
Driver
t
t
Soft-Start
CoolSET
-F3R
ICE3BR1065JF

Version 2.0 12 11 Sep 2008
Within the soft start period, the duty cycle is increasing
from zero to maximum gradually (see Figure 12).
In addition to Start-Up, Soft-Start is also activated at
each restart attempt during Auto Restart.
Figure 13 Start Up Phase
The Start-Up time t
Start-Up
before the converter output
voltage V
OUT
is settled, must be shorter than the Soft-
Start Phase t
Soft-Start
(see Figure 13).
By means of Soft-Start there is an effective
minimization of current and voltage stresses on the
integrated CoolMOS
, the clamp circuit and the output

overshoot and it helps to prevent saturation of the
transformer during Start-Up.
3.5 PWM Section
Figure 14 PWM Section Block
3.5.1 Oscillator
The oscillator generates a fixed frequency of 67KHz
with frequency jittering of 4% (which is 2.7KHz) at a
jittering period of 4ms.
A capacitor, a current source and current sink which
determine the frequency are integrated. The charging
and discharging current of the implemented oscillator
capacitor are internally trimmed, in order to achieve a
very accurate switching frequency. The ratio of
controlled charge to discharge current is adjusted to
reach a maximum duty cycle limitation of D
max
=0.75.
Once the Soft Start period is over and when the IC goes
into normal operating mode, the switching frequency of
the clock is varied by the control signal from the Soft
Start block. Then the switching frequency is varied in
range of 67KHz 2.7KHz at period of 4ms.
3.5.2 PWM-Latch FF1
The output of the oscillator block provides continuous
pulse to the PWM-Latch which turns on/off the internal
CoolMOS
. After the PWM-Latch is set, it is reset by

the PWM comparator, the Soft Start comparator or the
Current -Limit comparator. When it is in reset mode, the
output of the driver is shut down immediately.
t
t
V
SoftS
t
V
SOFTS32
4.5V
t
Soft-Start
V
OUT
V
FB
V
OUT
t
Start-Up
Oscillator
Duty Cycle
max
Gate Driver
0.75
Clock
&
G9
1
G8
PWM Section
FF1
R
S
Q
Soft Start
Comparator
PWM
Comparator
Current
Limiting
CoolMOS
Gate
Frequency
Jitter
Soft Start
Block
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-F3R
ICE3BR1065JF

Version 2.0 13 11 Sep 2008
3.5.3 Gate Driver
Figure 15 Gate Driver
The driver-stage is optimized to minimize EMI and to
provide high circuit efficiency. This is done by reducing
the switch on slope when exceeding the internal
CoolMOS
threshold. This is achieved by a slope

control of the rising edge at the drivers output (see
Figure 9).
Figure 16 Gate Rising Slope
Thus the leading switch on spike is minimized.
Furthermore the driver circuit is designed to eliminate
cross conduction of the output stage.
During power up, when VCC is below the undervoltage
lockout threshold V
VCCoff
, the output of the Gate Driver
is set to low in order to disable power transfer to the
secondary side.
3.6 Current Limiting
Figure 17 Current Limiting Block
There is a cycle by cycle peak current limiting operation
realized by the Current-Limit comparator C10. The
source current of the integrated CoolMOS
is sensed
via an external sense resistor R
Sense
. By means of
R
Sense
the source current is transformed to a sense
voltage V
Sense
which is fed into the pin CS. If the voltage
V
Sense
exceeds the internal threshold voltage V
csth,
the
comparator C10 immediately turns off the gate drive by
resetting the PWM Latch FF1.
A Propagation Delay Compensation is added to
support the immediate shut down of the integrated
CoolMOS
with very short propagation delay. Thus the

influence of the AC input voltage on the maximum
output power can be reduced to minimal.
In order to prevent the current limit from distortions
caused by leading edge spikes, a Leading Edge
Blanking is integrated in the current sense path for the
comparators C10, C12 and the PWM-OP.
The output of comparator C12 is activated by the Gate
G10 if Active Burst Mode is entered. When it is
activated, the current limiting is reduced to 0.26V. This
voltage level determines the maximum power level in
Active Burst Mode.
VCC
1
PWM-Latch
CoolMOS
Gate Driver
Gate
t
(internal)
V
Gate
5V
ca. t = 130ns
Current Limiting
C10
C12
&
0.26V
Leading
Edge
Blanking
220ns
G10
Propagation-Delay
Compensation
V
csth
Active Burst
Mode
PWM Latch
FF1
10k
D1
1pF
PWM-OP
CS
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ICE3BR1065JF

Version 2.0 14 11 Sep 2008
3.6.1 Leading Edge Blanking
Figure 18 Leading Edge Blanking
Whenever the internal CoolMOS
is switched on, a
leading edge spike is generated due to the primary-
side capacitances and reverse recovery time of the
secondary-side rectifier. This spike can cause the gate
drive to switch off unintentionally. In order to avoid a
premature termination of the switching pulse, this spike
is blanked out with a time constant of t
LEB
= 220ns.
3.6.2 Propagation Delay Compensation
In case of overcurrent detection, there is always
propagation delay to switch off the internal CoolMOS
.
An overshoot of the peak current I
peak
is induced to the
delay, which depends on the ratio of dI/dt of the peak
current (see Figure 19).
Figure 19 Current Limiting
The overshoot of Signal2 is larger than of Signal1 due
to the steeper rising waveform. This change in the
slope is depending on the AC input voltage.
Propagation Delay Compensation is integrated to
reduce the overshoot due to dI/dt of the rising primary
current. Thus the propagation delay time between
exceeding the current sense threshold V
csth
and the
switching off of the integrated CoolMOS
is
compensated over temperature within a wide range.
Current Limiting is then very accurate.
For example, I
peak
= 0.5A with R
Sense
= 2. The current
sense threshold is set to a static voltage level V
csth
=1V
without Propagation Delay Compensation. A current
ramp of dI/dt = 0.4A/s, or dV
Sense
/dt = 0.8V/s, and a
propagation delay time of t
Propagation Delay
=180ns leads
to an I
peak
overshoot of 14.4%. With the propagation
delay compensation, the overshoot is only around 2%
(see Figure 20).
Figure 20 Overcurrent Shutdown
The Propagation Delay Compensation is realized by
means of a dynamic threshold voltage V
csth
(see Figure
21). In case of a steeper slope the switch off of the
driver is earlier to compensate the delay.
Figure 21 Dynamic Voltage Threshold V
csth
3.7 Control Unit
The Control Unit contains the functions for Active Burst
Mode and Auto Restart Mode. The Active Burst Mode
and the Auto Restart Mode both have 20ms internal
Blanking Time. For the Auto Restart Mode, a further
extendable Blanking Time is achieved by adding
t
V
Sense
V
csth
t
LEB
= 220ns
t
I
Sense
I
Limit
t
Propagation Delay
I
Overshoot1
I
peak1
Signal1 Signal2
I
Overshoot2 I
peak2
0,9
0,95
1
1,05
1,1
1,15
1,2
1,25
1,3
0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
with compensation without compensation
dt
dV
Sense
s
V
S
e
n
s
e
V
V
t
V
csth
V
OSC
Signal1 Signal2
V
Sense
Propagation Delay
max. Duty Cycle
off time
t
CoolSET
-F3R
ICE3BR1065JF

Version 2.0 15 11 Sep 2008
external capacitor at BA pin. By means of this Blanking
Time, the IC avoids entering into these two modes
accidentally. Furthermore those buffer time for the
overload detection is very useful for the application that
works in low current but requires a short duration of
high current occasionally.
3.7.1 Basic and Extendable Blanking Mode
Figure 22 Basic and Extendable Blanking Mode
There are 2 kinds of Blanking mode; basic mode and
the extendable mode. The basic mode is just an
internal pre-set 20ms blanking time while the
extendable mode has extra blanking time by
connecting an external capacitor to the BA pin in
addition to the pre-set 20ms blanking time. For the
extendable mode, the gate G5 is blocked even though
the 20ms blanking time is reached if an external
capacitor C
BK
is added to BA pin. While the 20ms
blanking time is passed, the switch S1 is opened by
G2. Then the 0.9V clamped voltage at BA pin is
charged to 4.0V through the internal I
BK
constant
current. Then G5 is enabled by comparator C3. After
the 30us spike blanking time, the Auto Restart Mode is
activated.
For example, if C
BK
= 0.22uF, I
BK
= 13.5uA
Blanking time = 20ms + C
BK
x (4.0 - 0.9) / I
BK
= 70ms
In order to make the startup properly, the maximum C
BK
capacitor is restricted to less than 0.65uF.
The Active Burst Mode has basic blanking mode only
while the Auto Restart Mode has both the basic and the
extendable blanking mode.
3.7.2 Active Burst Mode
The IC enters Active Burst Mode under low load
conditions. With the Active Burst Mode, the efficiency
increases significantly at light load conditions while still
maintaining a low ripple on V
OUT
and a fast response on
load jumps. During Active Burst Mode, the IC is
controlled by the FB signal. Since the IC is always
active, it can be a very fast response to the quick
change at the FB signal. The Start up Cell is kept OFF
in order to minimize the power loss.
Figure 23 Active Burst Mode
The Active Burst Mode is located in the Control Unit.
Figure 23 shows the related components.
3.7.2.1 Entering Active Burst Mode
The FB signal is kept monitoring by the comparator C5.
During normal operation, the internal blanking time
counter is reset to 0. When FB signal falls below 1.22V,
it starts to count. When the counter reach 20ms and FB
signal is still below 1.22V, the system enters the Active
Burst Mode. This time window prevents a sudden
entering into the Active Burst Mode due to large load
jumps.
C3
4.0V
C4
4.5V
C5
1.22V
&
G5
&
G6
0.9V
S1
1
G2
Control Unit
Active
Burst
Mode
Auto
Restart
Mode
5.0V
BA
FB
C
BK
20ms
Blanking
Time
20ms
Blanking
Time
Spike
Blanking
30us
#
IBK
C4
4.5V
C6a
3.6V
C5
1.22V
FB
Control Unit
Active
Burst
Mode
Internal Bias
&
G10
Current
Limiting
&
G6
C6b
3.1V
&
G11
20 ms Blanking
Time
CoolSET
-F3R
ICE3BR1065JF

Version 2.0 16 11 Sep 2008
After entering Active Burst Mode, a burst flag is set and
the internal bias is switched off in order to reduce the
current consumption of the IC to approx. 500uA.
It needs the application to enforce the VCC voltage
above the Undervoltage Lockout level of 10.5V such
that the Startup Cell will not be switched on
accidentally. Or otherwise the power loss will increase
drastically. The minimum VCC level during Active Burst
Mode depends on the load condition and the
application. The lowest VCC level is reached at no load
condition.
3.7.2.2 Working in Active Burst Mode
After entering the Active Burst Mode, the FB voltage
rises as V
OUT
starts to decrease, which is due to the
inactive PWM section. The comparator C6a monitors
the FB signal. If the voltage level is larger than 3.6V, the
internal circuit will be activated; the Internal Bias circuit
resumes and starts to provide switching pulse. In
Active Burst Mode the gate G10 is released and the
current limit is reduced to 0.26V. In one hand, it can
reduce the conduction loss and the other hand, it can
reduce the audible noise. If the load at V
OUT
is still kept
unchanged, the FB signal will drop to 3.1V. At this level
the C6b deactivates the internal circuit again by
switching off the internal Bias. The gate G11 is active
again as the burst flag is set after entering Active Burst
Mode. In Active Burst Mode, the FB voltage is changing
like a saw tooth between 3.1V and 3.6V (see figure 17).
3.7.2.3 Leaving Active Burst Mode
The FB voltage will increase immediately if there is a
high load jump. This is observed by the comparator C4.
As the current limit is appr. 26% during Active Burst
Mode, a certain load jump is needed so that the FB
signal can exceed 4.5V. At that time the comparator C4
resets the Active Burst Mode control which in turn
blocks the comparator C12 by the gate G10. The
maximum current can then be resumed to stabilize
V
OUT.
Figure 24 Signals in Active Burst Mode
1.22V
3.6V
4.5V
V
FB
t
t
0.26V
1.0V
V
CS
10.0V
V
VCC t
t
500uA
I
VCC
t
2.9mA
V
OUT
t
Max. Ripple < 1%
20ms Blanking Time
Current limit level
during Active Burst
Mode
3.1V
Entering
Active Burst
Mode
Leaving
Active Burst
Mode
Blanking Timer
CoolSET
-F3R
ICE3BR1065JF

Version 2.0 17 11 Sep 2008

3.7.3 Protection Modes
The IC provides Auto Restart Mode as the protection
feature. Auto Restart mode can prevent the SMPS from
destructive states. The following table shows the
relationship between possible system failures and the
chosen protection modes.
Before entering the Auto Restart protection mode,
some of the protections can have extended blanking
time to delay the protection and some needs to fast
react and will go straight to the protection. Overload
and open loop protection are the one can have
extended blanking time while Vcc Overvoltage, Over
temperature, Vcc Undervoltage, short opto-coupler
and external auto restart enable will go to protection
right away.
After the system enters the Auto-restart mode, the IC
will be off. Since there is no more switching, the Vcc
voltage will drop. When it hits the Vcc turn off threshold,
the start up cell will turn on and the Vcc is charged by
the startup cell current to Vcc turn on threshold. The IC
is on and the startup cell will turn off. At this stage, it will
enter the startup phase (soft start) with switching
cycles. After the Start Up Phase, the fault condition is
checked. If the fault condition persists, the IC will go to
auto restart mode again. If, otherwise, the fault is
removed, normal operation is resumed.
3.7.3.1 Auto Restart mode with extended
blanking time
Figure 25 Auto Restart Mode
In case of Overload or Open Loop, the FB exceeds
4.5V which will be observed by comparator C4. Then
the internal blanking counter starts to count. When it
reaches 20ms, the switch S1 is released. Then the
clamped voltage 0.9V at V
BA
can increase. When there
is no external capacitor C
BK
connected, the V
BA
will
reach 4.0V immediately. When both the input signals at
AND gate G5 is positive, the Auto Restart Mode will be
activated after the extra spike blanking time of 30us is
elapsed. However, when an extra blanking time is
needed, it can be achieved by adding an external
capacitor, C
BK
. A constant current source of I
BK
will start
to charge the capacitor C
BK
from 0.9V to 4.0V after the
switch S1 is released. The charging time from 0.9V to
4.0V are the extendable blanking time. If C
BK
is 0.22uF
and I
BK
is 13.5uA, the extendable blanking time is
around 50ms and the total blanking time is 70ms. In
combining the FB and blanking time, there is a blanking
window generated which prevents the system to enter
Auto Restart Mode due to large load jumps.
VCC Overvoltage Auto Restart Mode
Overtemperature Auto Restart Mode
Overload Auto Restart Mode
Open Loop Auto Restart Mode
VCC Undervoltage Auto Restart Mode
Short Optocoupler Auto Restart Mode
External auto restart
enable
Auto Restart Mode
C3
4.0V
C4
4.5V
&
G5
0.9V
S1
1
G2
Control Unit
Auto
Restart
Mode
5.0V
BA
FB
C
BK
20ms
Blanking
Time
Spike
Blanking
30us
#
IBK
CoolSET
-F3R
ICE3BR1065JF

Version 2.0 18 11 Sep 2008
3.7.3.2 Auto Restart without extended blanking
time
Figure 26 Auto Restart mode
There are 2 modes of V
CC
overvoltage protection; one
is during soft start and the other is at all conditions.
The first one is V
VCC
voltage is > 20.7V and FB is > 4.5V
and during soft_start period and the IC enters Auto
Restart Mode. The VCC voltage is observed by
comparator C1. The fault conditions are to detect the
abnormal operating during start up such as open loop
during light load start up, etc. The logic can eliminate
the possible of entering Auto Restart mode if there is a
small voltage overshoots of V
VCC
during normal
operating.
The 2nd one is V
VCC
>25.5V and last for 120us and the
IC enters Auto Restart Mode. This 25.5V Vcc OVP
protection is inactivated during burst mode.
The Thermal Shutdown block monitors the junction
temperature of the IC. After detecting a junction
temperature higher than 130C, the Auto Restart Mode
is entered.
In case the pre-defined auto-restart features are not
sufficient, there is a customer defined external Auto-
restart Enable feature. This function can be triggered
by pulling down the BA pin to < 0.33V. It can simply add
a trigger signal to the base of the externally added
transistor, T
AE
at the BA pin. When the function is
enabled, the gate drive switching will be stopped and
then the IC will enter auto-restart mode if the signal
persists. To ensure this auto-restart function will not be
mis-triggered during start up, a 1ms delay time is
implemented to blank the unstable signal.
VCC undervoltage is the Vcc voltage drop below Vcc
turn off threshold. Then the IC will turn off and the start
up cell will turn on automatically. And this leads to Auto
Restart Mode.
Short Optocoupler also leads to VCC undervoltage.
When the FB pin is pulled low, there is no switching
pulse. Then the Vcc will drop to Vcc turn off threshold.
And it leads to Auto Restart Mode.
C1
20.7V
Spike
Blanking
30us
&
G1
Thermal Shutdown
Auto Restart
mode
VCC
C4
4.5V
Voltage
Reference
Control Unit
Auto Restart
Mode Reset
VVCC < 10.5V
FB
C2
120us
Blanking
Time
VCC
25.5V
softs_period
BA Auto-restart
Enable
Signal
T
AE
C9 0.33V
Stop
gate
drive
1ms
counter
UVLO
T
j
>130C
CoolSET
-F3R
ICE3BR1065JF
Electrical Characteristics

Version 2.0 19 11 Sep 2008

4 Electrical Characteristics
Note: All voltages are measured with respect to ground (Pin 5). The voltage levels are valid if other ratings are
not violated.
4.1 Absolute Maximum Ratings
Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction
of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 4
(VCC) is discharged before assembling the application circuit.T
a
=25C unless otherwise specified.
Parameter Symbol Limit Values Unit Remarks
min. max.
Switching drain current, pulse width t
p

limited by max. T
j
=150C
I
s
- 6.59 A
Pulse drain current, pulse width t
p

limited by max. T
j
=150C
I
D_Puls
- 13 A
Avalanche energy, repetitive t
AR
limited
by max. T
j
=150C
1)
1)
Repetitive avalanche causes additional power losses that can be calculated as P
AV
=E
AR
*f
E
AR
- 0.17 mJ I
D
=3A
Avalanche current, repetitive t
AR
limited
by max. T
j
=150C
1)
I
AR
- 3 A
VCC Supply Voltage V
VCC
-0.3 27 V
FB Voltage V
FB
-0.3 5.5 V
BA Voltage V
BA
-0.3 5.5 V
CS Voltage V
CS
-0.3 5.5 V
Junction Temperature T
j
-40 150 C Controller & CoolMOS
Storage Temperature T
S
-55 150 C
Thermal Resistance
Junction -Ambient
R
thJA
- 82 K/W
Thermal Resistance
Junction -case
R
thJC
- 4.4 K/W
Soldering temperature, wavesoldering
only allowed at leads
T
sold
- 260 C 1.6mm (0.063 in.) from
case for 10s
Power dissipation, T
c
=25C P
tot
- 28 W Refer to Figure 57
ESD Capability (incl. Drain Pin) V
ESD
- 2 kV Human body model
2)

2)
According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5k series resistor)
Mounting torque 60 Ncm M2.5 screws
CoolSET
-F3R
ICE3BR1065JF

Version 2.0 20 11 Sep 2008

4.2 Operating Range
Note: Within the operating range the IC operates as described in the functional description.
4.3 Characteristics
4.3.1 Supply Section
Note: The electrical characteristics involve the spread of values within the specified supply voltage and junction
temperature range T
J
from 25 C to 125 C. Typical values represent the median values, which are
related to 25C. If not otherwise stated, a supply voltage of V
CC
= 18 V is assumed.
Parameter Symbol Limit Values Unit Remarks
min. max.
VCC Supply Voltage V
VCC
V
VCCoff
25 V Max. value limited due to Vcc
OVP
Junction Temperature of
Controller
T
jCon
-25 130 C Max value limited due to thermal
shut down of controller
Junction Temperature of
CoolMOS
T
jCoolMOS
-25 150 C
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Start Up Current I
VCCstart
- 150 250 A V
VCC
=17V
VCC Charge Current I
VCCcharge1
- - 5.0 mA V
VCC
= 0V
I
VCCcharge2
0.55 0.9 1.60 mA V
VCC
= 1V
I
VCCcharge3
- 0.7 - mA V
VCC
=17V
Leakage Current of
Start Up Cell and CoolMOS
I
StartLeak
- 0.2 50 A V
Drain
= 600V
at T
j
=100C
1)
1)
The parameter is not subjected to production test - verified by design/characterization
Supply Current with
Inactive Gate
I
VCCsup1
- 1.5 2.5 mA
Supply Current with Active Gate I
VCCsup2
- 2.9 4.2 mA I
FB
= 0A
Supply Current in
Auto Restart Mode with Inactive
Gate
I
VCCrestart
- 250 - A I
FB
= 0A
Supply Current in Active Burst
Mode with Inactive Gate
I
VCCburst1
- 500 950 A V
FB
= 2.5V
I
VCCburst2
- 500 950 A V
VCC
= 11.5V,V
FB
= 2.5V
VCC Turn-On Threshold
VCC Turn-Off Threshold
VCC Turn-On/Off Hysteresis
V
VCCon
V
VCCoff
V
VCChys
17.0
9.8
-
18.0
10.5
7.5
19.0
11.2
-
V
V
V
CoolSET
-F3R
ICE3BR1065JF

Version 2.0 21 11 Sep 2008

4.3.2 Internal Voltage Reference
4.3.3 PWM Section
4.3.4 Soft Start time
min. typ. max.
Trimmed Reference Voltage V
REF
4.90 5.00 5.10 V measured at pin FB
I
FB
= 0
min. typ. max.
Fixed Oscillator Frequency f
OSC1
58 67 75 kHz
f
OSC2
62 67 74.5 kHz T
j
= 25C
Frequency Jittering Range f
jitter
- 2.7 - kHz T
j
= 25C
Frequency Jittering period T
jitter
- 4.0 - ms T
j
= 25C
Max. Duty Cycle D
max
0.70 0.75 0.80
Min. Duty Cycle D
min
0 - - V
FB
< 0.3V
PWM-OP Gain A
V
3.1 3.3 3.5
Voltage Ramp Offset V
Offset-Ramp
- 0.68 - V
V
FB
Operating Range Min Level V
FBmin
- 0.5 - V
V
FB
Operating Range Max level V
FBmax
- - 4.3 V CS=1V, limited by
Comparator C4
1)
1)
FB Pull-Up Resistor R
FB
9 15.4 22 k
min. typ. max.
Soft Start time t
SS
- 20.0 - ms V
FB
> 4.0V

Version 2.0 22 11 Sep 2008
CoolSET
-F3R
ICE3BR1065JF

4.3.5 Control Unit
Note: The trend of all the voltage levels in the Control Unit is the same regarding the deviation except V
VCCOVP
and V
VCCPD
min. typ. max.
Clamped V
BA
voltage during
Normal Operating Mode
V
BAclmp
0.85 0.9 0.95 V V
FB
= 4V
Blanking time voltage limit for
Comparator C3
V
BKC3
3.85 4.00 4.15 V
Over Load & Open Loop Detection
Limit for Comparator C4
V
FBC4
4.28 4.50 4.72 V
Active Burst Mode Level for
Comparator C5
V
FBC5
1.13 1.22 1.31 V
Comparator C6a
V
FBC6a
3.45 3.60 3.74 V After Active Burst
Mode is entered
Comparator C6b
V
FBC6b
2.97 3.10 3.22 V After Active Burst
Mode is entered
Overvoltage Detection Limit for
Comparator C1
V
VCCOVP1
19.6 20.7 21.7 V V
FB
= 5V
Overvoltage Detection Limit for
Comparator C2
V
VCCOVP2
25.0 25.5 26.3 V
Auto-restart Enable level at BA pin
for Comparator C9
V
AE
0.25 0.33 0.42 V
Charging current at BA pin I
BK
10.1 13.5 16.1 A Charge starts after the
built-in 20ms blanking
time elapsed
Thermal Shutdown
1)
T
jSD
130 140 150 C Controller
Built-in Blanking Time for
Overload Protection or enter
Active Burst Mode
t
BK
- 20 - ms without external
capacitor at BA pin
Inhibit Time for Auto-Restart
enable function during start up
t
IHAE
- 1.0 - ms Count when VCC>18V
Spike Blanking Time before Auto
Restart Protection
t
Spike
- 30 - s
1)
CoolSET
-F3R
ICE3BR1065JF

Version 2.0 23 11 Sep 2008

4.3.6 Current Limiting
4.3.7 CoolMOS
Section
min. typ. max.
Peak Current Limitation
(incl. Propagation Delay)
V
csth
0.88 1.06 1.13 V dV
sense
/ dt = 0.6V/s
(see Figure 13)
Peak Current Limitation during
Active Burst Mode
V
CS2
0.22 0.26 0.29 V
Leading Edge Blanking t
LEB
- 220 - ns
CS Input Bias Current I
CSbias
-1.5 -0.2 - A V
CS
=0V
min. typ. max.
Drain Source Breakdown Voltage V
(BR)DSS
650 - - V T
j
= 110C
1)
(Refer to
Figure 65 for other
V
(BR)DSS
in different T
j
)
V
GS
=0V, I
D
=0.25mA
Drain Source Avalanche
Breakdown Voltage
V
(BR)DS
- 700 - V V
GS
=0V, I
D
=3A
Drain Source On-Resistance R
DSon
-
-
-
1.0
2.2
2.7
1.19
2.63
3.21
T
j
= 25C
T
j
=125C
1)
T
j
=150C
1)
at I
D
= 2.6A
1)
Effective output capacitance,
energy related
C
o(er)
- 21 - pF V
DS
= 0V to 480V
1)
Rise Time t
rise
- 30
2)
2)
Measured in a Typical Flyback Converter Application
- ns
Fall Time t
fall
- 30
2)
- ns

Version 2.0 24 11 Sep 2008
CoolSET
-F3R
ICE3BR1065JF
Typical Controller Performance Characteristics

5 Typical Controller Performance Characteristics
Figure 27 Start Up Current I
VCCstart
Figure 28 VCC Charge Current I
VCCcharge1
VCCcharge2
VCCcharge3

Figure 31 VCC Supply Current I
VCCsup1
VCCsup2
Junction Temperature [C]
S
t
a
r
t

U
p

C
u
r
r
e
n
t

I
V
C
C
s
t
a
r
t

[
A
]
P
I-0
0
1
-8
8
8
9
A
2
3
120
128
136
144
152
160
168
176
184
192
200
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
V
c
c

C
h
a
r
g
e

C
u
r
r
e
n
t

I
V
C
C
c
h
a
r
g
e
1

[
m
A
]
P
I-0
0
2
-8
8
8
9
A
2
3
0.60
0.64
0.68
0.72
0.76
0.80
0.84
0.88
0.92
0.96
1.00
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
V
c
c

C
h
a
r
g
e

C
u
r
r
e
n
t

I
V
C
C
c
h
a
r
g
e
2

[
m
A
]
P
I-0
0
3
-8
8
8
9
A
2
3
0.60
0.64
0.68
0.72
0.76
0.80
0.84
0.88
0.92
0.96
1.00
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
V
c
c

C
h
a
r
g
e

C
u
r
r
e
n
t

I
V
C
C
c
h
a
r
g
e
3

[
m
A
]
P
I-0
0
4
-8
8
8
9
A
2
3
0.45
0.49
0.53
0.57
0.61
0.65
0.69
0.73
0.77
0.81
0.85
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
V
c
c

S
u
p
p
l
y

C
u
r
r
e
n
t

I
V
C
C
s
u
p
1

[
m
A
]
P
I-0
0
5
-8
8
8
9
A
2
3
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
V
c
c

S
u
p
p
l
y

C
u
r
r
e
n
t

I
V
C
C
s
u
p
2

[
m
A
]
P
I-0
0
6
-8
8
8
8
A
1
2
_
IC
E
3
B
R
1
0
6
5
J
F
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
CoolSET
-F3R
ICE3BR1065JF

Version 2.0 25 11 Sep 2008

VCCrestart
VCCburst
Figure 35 VCC Turn-On Threshold V
VCCon
Figure 36 VCC Turn-Off Threshold V
VCCoff
Figure 37 Reference Voltage V
REF
Figure 38 Oscillator Frequency f
OSC1
V
c
c

S
u
p
p
l
y

C
u
r
r
e
n
t

I
V
C
C
r
e
s
t
a
r
t

[
u
A
]
P
I-0
0
7
-8
8
8
9
A
2
3
210
220
230
240
250
260
270
280
290
300
310
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
V
c
c

S
u
p
p
l
y

C
u
r
r
e
n
t

I
V
C
C
b
u
r
s
t

[
u
A
]
P
I-0
0
8
-8
8
8
9
A
2
3
400
420
440
460
480
500
520
540
560
580
600
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
V
c
c

T
u
r
n
-
O
n

t
h
r
e
s
h
o
l
d

V
V
C
C
o
n

[
V
]
P
I-0
1
0
-8
8
8
9
A
2
3
17.5
17.6
17.7
17.8
17.9
18.0
18.1
18.2
18.3
18.4
18.5
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
V
c
c

T
u
r
n
-
O
f
f

T
h
r
e
s
h
o
l
d

V
V
C
C
o
f
f

[
V
]
P
I-0
1
0
-8
8
8
9
A
2
3
10.0
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
11.0
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
R
e
f
e
r
e
n
c
e

V
o
l
t
a
g
e

V
R
E
F

[
V
]
P
I-0
1
1
-8
8
8
9
A
2
3
4.80
4.84
4.88
4.92
4.96
5.00
5.04
5.08
5.12
5.16
5.20
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
O
s
c
i
l
l
a
t
o
r

F
r
e
q
u
e
n
c
y

f
o
s
c
1

[
k
H
z
]
P
I-0
1
2
-8
8
8
9
A
2
3
60
61
62
63
64
65
66
67
68
69
70
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125

Version 2.0 26 11 Sep 2008
CoolSET
-F3R
ICE3BR1065JF

Figure 39 Frequency Jittering Range f
jitter
Figure 40 Max. Duty Cycle D
max
Figure 41 PWM-OP Gain A
V
Figure 42 Voltage Ramp Offset V
Offset-Ramp
Figure 43 Feedback Pull-Up resistor R
FB
Figure 44 Clamped V
BA
voltage V
BAclmp
F
r
e
q
u
e
n
c
y

J
i
t
t
e
r

R
a
n
g
e

f
j
i
t
t
e
r

[
+
/
-
k
H
z
]
P
I-0
0
1
-8
8
8
9
A
2
3
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
M
a
x
.

D
u
t
y

C
y
c
l
e

D
m
a
x
P
I-0
1
4
-8
8
8
9
A
2
3
0.720
0.726
0.732
0.738
0.744
0.750
0.756
0.762
0.768
0.774
0.780
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
P
W
M

O
P

G
a
i
n

A
V
P
I-0
1
5
-8
8
8
9
A
2
3
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
3.40
3.45
3.50
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
V
o
l
t
a
g
e

R
a
m
p

O
f
f
s
e
t

V
O
f
f
s
e
t
-
R
a
m
p

[
V
]
P
I-0
1
6
-8
8
8
9
A
2
3
0.63
0.64
0.65
0.66
0.67
0.68
0.69
0.70
0.71
0.72
0.73
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
F
e
e
d
b
a
c
k

P
u
l
l
-
U
p

r
e
s
i
s
t
o
r

R
F
B

[
k
O
h
m
]
P
I-0
1
9
-8
8
8
9
A
2
3
10
11
12
13
14
15
16
17
18
19
20
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
C
l
a
m
p
e
d

V
B
A

V
o
l
t
a
g
e

V
B
A
c
l
m
p

[
V
]
P
I-0
2
0
-8
8
8
9
A
2
3
0.85
0.86
0.87
0.88
0.89
0.90
0.91
0.92
0.93
0.94
0.95
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
CoolSET
-F3R
ICE3BR1065JF

Version 2.0 27 11 Sep 2008

Figure 45 Blanking time voltage limit V
BKC3
Figure 46 Over Load Detection Limit V
FBC4
Figure 47 Active Burst Mode Level V
FBC5
FBC6a
FBC6b
Figure 50 Overvoltage Detection Limit V
VCCOVP1
B
l
a
n
k
i
n
g

t
i
m
e

v
o
l
t
a
g
e

l
i
m
i
t

V
B
K
C
3

[
V
]
P
I-0
2
1
-8
8
8
9
A
2
3
3.90
3.92
3.94
3.96
3.98
4.00
4.02
4.04
4.06
4.08
4.10
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
O
v
e
r

L
o
a
d

d
e
t
e
c
t
i
o
n

l
i
m
i
t

V
F
B
C
4

[
V
]
P
I-0
2
2
-8
8
8
9
A
2
3
4.30
4.35
4.40
4.45
4.50
4.55
4.60
4.65
4.70
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
A
c
t
i
v
e

B
u
r
s
t

m
o
d
e

L
e
v
e
l

V
F
B
C
5

[
V
]
P
I-0
2
3
-8
8
8
9
A
2
3
1.00
1.04
1.08
1.12
1.16
1.20
1.24
1.28
1.32
1.36
1.40
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
A
c
t
i
v
e

B
u
r
s
t

M
o
d
e
l

L
e
v
e

V
F
B
C
6
a

[
V
]
P
I-0
2
4
-8
8
8
9
A
2
3
3.50
3.52
3.54
3.56
3.58
3.60
3.62
3.64
3.66
3.68
3.70
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
A
c
t
i
v
e

B
u
r
s
t

M
o
d
e

L
e
v
e
l

V
F
B
C
6
b

[
V
]
P
I-0
2
5
-8
8
8
9
A
2
3
2.80
2.85
2.90
2.95
3.00
3.05
3.10
3.15
3.20
3.25
3.30
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
O
v
e
r
v
o
l
t
a
g
e

D
e
t
e
c
t
i
o
n

L
i
m
i
t

V
V
C
C
o
v
p
1

[
V
]
P
I-0
2
6
-8
8
8
9
A
2
3
20.0
20.1
20.2
20.3
20.4
20.5
20.6
20.7
20.8
20.9
21.0
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125

Version 2.0 28 11 Sep 2008
CoolSET
-F3R
ICE3BR1065JF

Figure 51 Over Load Detection Limit V
VCCOVP2
Figure 52 Auto-restart Enable Level V
AE
Figure 53 Charging Current at BA pin I
BK
Figure 54 Peak Current Limitation V
csth
Figure 55 Peak Current Limitation V
CS2
Figure 56 Leading Edge Blanking t
LEB
O
v
e
r
v
o
l
t
a
g
e

D
e
t
e
c
t
i
o
n

L
e
v
e
l

V
V
C
C
O
V
P
2

[
V
]
P
I-0
2
7
-8
8
8
9
A
2
3
25.0
25.1
25.2
25.3
25.4
25.5
25.6
25.7
25.8
25.9
26.0
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
A
u
t
o
-
r
e
s
t
a
r
t

E
n
a
b
l
e

L
e
v
e
l

V
A
E

[
V
]
P
I-0
2
8
-8
8
8
9
A
2
3
0.28
0.29
0.30
0.31
0.32
0.33
0.34
0.35
0.36
0.37
0.38
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
C
h
a
r
g
i
n
g

C
u
r
r
e
n
t

a
t

B
A

p
i
n

I
B
K

[
A
]
P
I-0
2
9
-8
8
8
9
A
2
3
10.0
10.5
11.0
11.5
12.0
12.5
13.0
13.5
14.0
14.5
15.0
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
P
e
a
k

C
u
r
r
e
n
t

L
i
m
i
t
a
t
i
o
n

V
C
S
t
h

[
V
]
P
I-0
3
1
-8
8
8
9
A
2
3
0.80
0.84
0.88
0.92
0.96
1.00
1.04
1.08
1.12
1.16
1.20
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
P
e
a
k

C
u
r
r
e
n
t

L
i
m
i
t
a
t
i
o
n

V
C
S
2

[
V
]
P
I-0
3
2
-8
8
8
9
A
2
3
0.20
0.21
0.22
0.23
0.24
0.25
0.26
0.27
0.28
0.29
0.30
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
L
e
a
d
i
n
g

E
d
g
e

B
l
a
n
k
i
n
g

t
L
E
B

[
n
s
]
P
I-0
3
3
-8
8
8
9
A
2
3
190
200
210
220
230
240
250
260
270
280
290
-25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125

Version 2.0 29 11 Sep 2008
CoolSET
-F3R
ICE3BR1065JF
Typical CoolMOS
Performance Characteristics

6 Typical CoolMOS
Figure 57 Power dissipation; P
tot
=f(T
C
)
Figure 58 Safe operation area; I
D
=f(V
DS
), parameter :
D=0, T
C
=25C
Figure 59 Transient thermal impedance;
Z
thJC
=f(t
p
),parameter: D=t
p
/T
Figure 60 Typ. output characteristics;
I
D
=f(V
DS
),T
j
=25C, parameter : V
CC

Figure 61 Typ. output characteristics;
I
D
=f(V
DS
),T
j
=150C, parameter : V
CC
Figure 62 Typ. drain-source on-state resistance;
R
DS(on)
=f(I
D
); T
j
=150C, parameter : V
CC
0
5
10
15
20
25
30
0 40 80 120 160
T
C
[C]
P
t
o
t

[
W
]
1 s
10 s
100 s
1 ms
10 ms
DC
10
3
10
2
10
1
10
0
10
2
10
1
10
0
10
-1
V
DS
[V]
I
D

[
A
]
limited by on-state resistance
single pulse
0.01
0.02
0.05
0.1
0.2
0.5
10
1
10
0
10
-1
10
-2
10
-3
10
-4
10
-5
10
1
10
0
10
-1
t
p
[s]
Z
t
h
J
C

[
K
/
W
]
Ugs 8 V, T 25 C
Vcc > 10.5V
0
3
6
9
12
15
0 5 10 15 20
V
DS
[V]
I
D

[
A
]
Ugs 8 V, T 150 C
Vcc > 10.5V
0
1
2
3
4
5
6
0 5 10 15 20
V
DS
[V]
I
D

[
A
]
Vcc > 10.5 V
2
2.5
3
3.5
4
4.5
5
0 2 4 6 8
I
D
[A]
R
D
S
(
o
n
)

[
]
CoolSET
-F3R
ICE3BR1065JF
Typical CoolMOS

Version 2.0 30 11 Sep 2008

Figure 63 Drain-source on-state resistance;
R
DS(on)
=f(T
j
); I
D
=2.6A;, V
cc
>10.5V
Figure 64 Avalanche energy;
E
AS
=f(T
j
),I
D
=1.7A,V
DD
=50V
Figure 65 Drain-source breakdown voltage;
V
BR(DSS)
=f(T
j
), I
D
=0.25mA
Figure 66 Typ. capacitances;
C=f(V
DS
),V
GS
=0V,f=1MHz
Figure 67 Typ. Coss stored energy; E
oss
=f(V
DS
)
typ
98 %
0.2
0.6
1
1.4
1.8
2.2
2.6
3
-60 -20 20 60 100 140 180
T
j
[C]
R
D
S
(
o
n
)
[
]
0
20
40
60
80
100
120
20 60 100 140 180
T
j
[C]
E
A
S

[
m
J
]
540
580
620
660
700
-60 -20 20 60 100 140 180
T
j
[C]
V
B
R
(
D
S
S
)

[
V
]
Ciss
Coss
Crss
10
0
10
1
10
2
10
3
0 100 200 300 400 500
V
DS
[V]
C

[
p
F
]
0
1
2
3
4
0 100 200 300 400 500 600
V
DS
[V]
E
o
s
s

[
J
]
CoolSET
-F3R
ICE3BR1065JF
Input Power Curve

Version 2.0 31 11 Sep 2008

7 Input Power Curve
Two input power curves giving the typical input power versus ambient temperature are showed below;
Vin=85Vac~265Vac (Figure 68) and Vin=230Vac+/-15% (Figure 69). The curves are derived based on a typical
discontinuous mode flyback model which considers either 50% maximum duty ratio or 100V maximum secondary
to primary reflected voltage (higher priority). The calculation is based on R
thSA
=2.7K/W as heatsink and
R
thCS
=1.1K/W as thermal grease thermal resistance. The input power already includes the power loss at input
common mode choke, bridge rectifier and the CoolMOS. The device saturation current (I
D_Puls
@ T
j
=125C) is also
considered.
To estimate the output power of the device, it is simply multiplying the input power at a particular operating ambient
temperature with the estimated efficiency for the application. For example, a wide range input voltage (Figure 68),
operating temperature is 50C, estimated efficiency is 80%, then the estimated output power is 96W (120W *
80%).
Figure 68 Input power curve Vin=85~265Vac; P
in
=f(T
a
)
Figure 69 Input power curve Vin=230Vac+/-15%; P
in
=f(T
a
)
Ambient Temperature [C]
I
n
p
u
t

p
o
w
e
r

(
8
5
~
2
6
5
V
a
c
)

[
W
]
P
I
-
0
0
3
-
I
C
E
3
B
R
1
0
6
5
J
F
_
8
5
V
a
c
0
15
30
45
60
75
90
105
120
135
150
0 10 20 30 40 50 60 70 80 90 100 110 120 130
Ambient Temperature [C]
I
n
p
u
t

p
o
w
e
r

(
2
3
0
V
a
c
)

[
W
]
P
I
-
0
0
4
-
I
C
E
3
B
R
1
0
6
5
J
F
_
2
3
0
V
a
c
0
20
40
60
80
100
120
140
160
180
200
220
0 10 20 30 40 50 60 70 80 90 100 110 120 130
CoolSET
-F3R
ICE3BR1065JF
Outline Dimension

Version 2.0 32 11 Sep 2008

8 Outline Dimension
Figure 70 PG-TO220-6-247 (PB-free Plating FullPak Package)
Dimensions in mm
PG-TO220-6-247
(PB-free Plating FullPak
Package Outline)
CoolSET
-F3R
ICE3BR1065JF
Marking

Version 2.0 33 11 Sep 2008

9 Marking
Figure 71 Marking for ICE3BR1065JF
Marking
CoolSET
-F3R
ICE3BR1065JF
Schematic for recommended PCB layout

Version 2.0 34 11 Sep 2008

10 Schematic for recommended PCB layout
Figure 72 Schematic for recommended PCB layout
General guideline for PCB layout design using F3/F3R CoolSET (refer to Figure 72):
1. Star Ground at bulk capacitor ground, C11:
Star Ground means all primary DC grounds should be connected to the ground of bulk capacitor C11
separately in one point. It can reduce the switching noise going into the sensitive pins of the CoolSET device
effectively. The primary DC grounds include the followings.
a. DC ground of the primary auxiliary winding in power transformer, TR1, and ground of C16 and Z11.
b. DC ground of the current sense resistor, R12
c. DC ground of the CoolSET device, GND pin of IC11; the signal grounds from C13, C14, C15 and collector of
IC12 should be connected to the GND pin of IC11 and then star connect to the bulk capacitor ground.
d. DC ground from bridge rectifier, BR1
e. DC ground from the bridging Y-capacitor, C4
2. High voltage traces clearance:
High voltage traces should keep enough spacing to the nearby traces. Otherwise, arcing would incur.
a. 400V traces (positive rail of bulk capacitor C11) to nearby trace: > 2.0mm
b. 600V traces (drain voltage of CoolSET IC11) to nearby trace: > 2.5mm
3. Filter capacitor close to the controller ground:
Filter capacitors, C13, C14 and C15 should be placed as close to the controller ground and the controller pin
as possible so as to reduce the switching noise coupled into the controller.
Guideline for PCB layout design when >3KV lightning surge test applied (refer to Figure 72):
1. Add spark gap
Spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulated
charge during surge test through the sharp point of the saw-tooth plate.
a. Spark Gap 3 and Spark Gap 4, input common mode choke, L1:
Gap separation is around 1.5mm (no safety concern)
C11
bulk cap
R11
D11
C12
IC12
R12
C13
C16
C15
C14
D13
R14
R23 R22
IC21
C23
R24
C22
R21
R25
GND
Vo
D21
C21
F3 CoolSET schematic for recommended PCB layout
R13
Z11
TR1
N
L
BR1
C2
Y-CAP
C3
Y-CAP
C1
X-CAP
L1
FUSE1
C4
Y-CAP
GND
Spark Gap 3
Spark Gap 4
D11
Spark Gap 1
Spark Gap 2
FB
CS
GND NC
BA VCC
F3
DRAIN
CoolSET
IC11
*
CoolSET
-F3R
ICE3BR1065JF
Schematic for recommended PCB layout

Version 2.0 35 11 Sep 2008

b. Spark Gap 1 and Spark Gap 2, Live / Neutral to GROUND:
These 2 Spark Gaps can be used when the lightning surge requirement is >6KV.
230Vac input voltage application, the gap separation is around 5.5mm
115Vac input voltage application, the gap separation is around 3mm
2. Add Y-capacitor (C2 and C3) in the Live and Neutral to ground even though it is a 2-pin input
3. Add negative pulse clamping diode, D11 to the Current sense resistor, R12:
The negative pulse clamping diode can reduce the negative pulse going into the CS pin of the CoolSET and
reduce the abnormal behavior of the CoolSET. The diode can be a fast speed diode such as IN4148.
The principle behind is to drain the high surge voltage from Live/Neutral to Ground without passing through the
sensitive components such as the primary controller, IC11.
Qualitt hat fr uns eine umfassende
Bedeutung. Wir wollen allen Ihren
Ansprchen in der bestmglichen
Weise gerecht werden. Es geht uns also
nicht nur um die Produktqualitt
unsere Anstrengungen gelten
gleichermaen der Lieferqualitt und
Logistik, dem Service und Support
sowie allen sonstigen Beratungs- und
Betreuungsleistungen.
Dazu gehrt eine bestimmte
Geisteshaltung unserer Mitarbeiter.
Total Quality im Denken und Handeln
gegenber Kollegen, Lieferanten und
Ihnen, unserem Kunden. Unsere
Leitlinie ist jede Aufgabe mit Null
Fehlern zu lsen in offener
Sichtweise auch ber den eigenen
Arbeitsplatz hinaus und uns stndig
zu verbessern.
Unternehmensweit orientieren wir uns
dabei auch an top (Time Optimized
Processes), um Ihnen durch grere
Schnelligkeit den entscheidenden
Wettbewerbsvorsprung zu verschaffen.
Geben Sie uns die Chance, hohe
Leistung durch umfassende Qualitt zu
beweisen.
Wir werden Sie berzeugen.
Quality takes on an allencompassing
significance at Semiconductor Group.
For us it means living up to each and
every one of your demands in the best
possible way. So we are not only
concerned with product quality. We
direct our efforts equally at quality of
supply and logistics, service and
support, as well as all the other ways in
which we advise and attend to you.
Part of this is the very special attitude of
our staff. Total Quality in thought and
deed, towards co-workers, suppliers
and you, our customer. Our guideline is
do everything with zero defects, in an
open manner that is demonstrated
beyond your immediate workplace, and
to constantly improve.
Throughout the corporation we also
think in terms of Time Optimized
Processes (top), greater speed on our
part to give you that decisive
competitive edge.
Give us the chance to prove the best of
performance through the best of quality
you will be convinced.
h t t p : / / www. i n f i n e o n . c o m
Total Quality Management
Published by Infineon Technologies AG

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Cool SET

are trademarks of Infineon Technologies AG.

-F3R FullPak is the enhanced version of

-F3 and targets for the Off-Line Adapters and

Performance Characteristics . . . . . . . . . . . . . . . . . .29

and the HV of the startup cell.

. If CS voltage reaches the

-F3R FullPak is the further development of

-F3 for high power application. The

Soft Start block

. By means of Current Mode regulation, the

with the feedback

exceeds the signal V

, the clamp circuit and the output

. After the PWM-Latch is set, it is reset by

threshold. This is achieved by a slope

with very short propagation delay. Thus the

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