Electronics 1 of 17

B.Sc (Electronics) Scheme of instruction

S.No. Year Paper Hours/week Total
hours
. THE!"Y
01 First Year Paper#$
Circuit Analysis and Electronic Devices
4hrs/ Week 120 Hours
02 Second
Year
Paper#$$
Analo Circuits and Co!!unications
4hrs/ Week 120 Hours
0" #hird
Year
Paper $$$
Diital Electronics and $icro%rocessor&
"hrs/ Week '0 Hours
04 #hird
Year
Paper $% (Electi&es)
Any one of the following
i) Paper $%
E!(edded Syste!s and A%%lications
ii) Paper $%B
Diital Desin usin )HD*
"hrs/ Week '0 Hours
B. P"'T$'(S
0+ First Year Paper $) Circuit Analysis and
Electronic Devices *a(
"hrs/Week '0 Hours
,"0Sessions-
0. Second
Year
Paper $$) Analo Circuits and
Co!!unication *a(
"hrs/ Week '0 Hours
,"0Sessions-
0/ #hird
Year
Paper $$$) Diital Electronics and
$icro%rocessor *a(

"hrs/ Week '0 Hours
,"0 Sessions-
00 #hird
Year
Paper $% (Electi&es)
n* one of the followin+
Paper # $% ()) E!(edded Syste!s and
A%%lications *a(
Paper # $% (B)) Diital desin 1sin
)HD* *a(

" hrs/Week '0 Hours
,"0 Sessions-
Electronics 2 of 17
ANDHRA UNIVERSITY
ELECTRONICS SYLLABUS ADMITTED BATCH 200!0"
B#S$ I Ye%& !Ele$t&oni$'
PPE"#$ 'ircuit nal*sis an, Electronic -e&ices. ,120 hours-
.N$T#$ ,"0 hours-
AC ()n*%+ent%l') #he Sine 2ave 3Averae and 4$S values3#he 5 o%erator 3 6olar and
rectanular 7or!s o7 co!%le8 nu!(ers 3 6hasor diara! 3 Co!%le8 i!%edance and
ad!ittance&
,%''i-e netwo&.'9 Conce%t o7 voltae and current sources 3 :)* and :C*; A%%lication to
si!%le circuits ,AC and DC- consistin o7 resistors and sources ,one or t2o- ; <ode voltae
analysis and !ethod o7 !esh currents&
Netwo&. theo&e+' (DC %n* AC)9 Su%er%osition #heore!3#hevenin=s #heore!3 <orton=s
#heore!3$a8i!u! %o2er trans7er #heore!3$ill!an #heore!; 4eci%rocity #heore! 3
A%%lication to si!%le net2orks&
.N$T# $$ ,"0 hours-
RC %n* RL Ci&$)it') #ransient res%onse o7 4* and 4C circuits 2ith ste% in%ut3 ti!e
constants& Fre>uency res%onse o7 4C and 4* circuits 3 #y%es o7 Filters9 *o2 %ass 7ilter 3
Hih %ass 7ilter 3 7re>uency res%onse ; 6assive di77erentiatin and interatin circuits&
Re'on%n$e) Series resonance and %arallel resonance 4*C circuits 3 4esonant 7re>uency 3 ?
7actor 3 @and 2idth 3 Selectivity&
.N$T#$$$ ,"0 hours-
,N /)n$tion9 De%letion reion 3 5unction ca%acitance 3 Diode e>uation ,no derivation- 3
E77ect o7 te!%erature on reverse saturation current 3 constructionA 2orkinA );B
characteristics and si!%le a%%lications o7
i- 5unction diode ii- Cener diode iii- #unnel diode and iv- )aractor diode&
Bi0ol%& /)n$tion T&%n'i'to& 1B/T23 6<6 and <6< transistors3current co!%onents in @5# 3
@5# static characteristics ,Bn%ut and Dut%ut- 3 Early e77ect; C@A CCACE con7iurations ,cut
o77A activeA and saturation reions- CE con7iuration as t2o %ort net2ork 3 h;%ara!eters 3
h;%ara!eter e>uivalent circuit& E8%eri!ental arrane!ent to study in%ut and out%ut
characteristics o7 @5# in CE con7iuration& Deter!ination o7 h;%ara!eters 7ro! the
characteristics& @iasin and load line analysis 3 Fi8ed (ias and sel7 (ias arrane!ent&
Electronics 3 of 17
.N$T#$% ,"0 hours-
(iel* Effe$t T&%n'i'to& 1(ET23 Structure and 2orkin o7 5FE# and $DSFE# 3 out%ut and
trans7er characteristics 3 E8%eri!ental arrane!ent 7or studyin the characteristics and to
deter!ine FE# %ara!eters& A%%lication o7 FE# as voltae varia(le resistor and $DSFE# as
a s2itch 3 Advantaes o7 FE# over transistor&
Uni /)n$tion T&%n'i'to& 1U/T29 Structure and 2orkin o7 15#; Characteristics& A%%lication
o7 15# as a rela8ation oscillator&
Sili$on Cont&olle* Re$tifie& 1SCR23 Structure and 2orkin o7 SC4& #2o transistor
re%resentationA Characteristics o7 SC4& E8%eri!ental set u% to study the SC4 characteristics&
A%%lication o7 SC4 7or %o2er control&
,hoto Ele$t&i$ De-i$e'3 Structure and o%eration o7 *D4A 6hoto voltaic cellA 6hoto diodeA
6hoto transistors and *ED&
,N!TE) Sol-ing &el%te* 0&o4le+' in %ll the Unit'-
4e7erence @ooks9
1& Ero(=s @asic Electronics ; $itchel E&SchultF 10
th
Edn& #ata $cEra2 Hill ,#$H-
2& <et2ork lines and 7ields; 4yder; 6rentice Hall o7 Bndia ,6HB-
"& Circuit analysis ; 6&Enanasiva!; 6earson Education
4& Circuits and <et2orks ; A&Sudhaksr G Shya!!ohan S& 6alli ; #$H
+& <et2ork #heory ; S!araHit Ehosh ; 6HB
.& Electronic Devices and Circuits;$ill!an and Halkias ; #$H
/& Electronic Devices and Circuits;Allen $ottershead ; 6HB
0& 6rinci%les o7 Electronics; )&:& $ehta and 4ohit $ehta ; S Chand GCo
'& Electronic Devices and Circuit #heory; 4&*&@oylestad and *&<ashelsky; 6earson Education&
10& 6ulse diital s2itchin 2ave7or!s ;$ill!an G#au( ; #$H&
11& A%%lied Electronics; 4&S&Sedha ; S Chand GCo
12& A First course in Electronics; AA :han G :: Day; 6HB
1"& 6rinci%les o7 Electronic circuits; Stanely E&@urns and 6aul 4& @ond; Ealotia&
14& Electronic 6rinci%les and A%%lications 3 A&@& @hattacharya; <e2 Central @ook Aency 6vt&

Electronics 4 of 17
B#S$ I Ye%& ! Ele$t&oni$'
P"'T$'(S PPE"#$ ,'0 hours;"0 Sessions-
Circuit Analysis and Electronic devices Lab
1& $easure!ent o7 %eak voltaeA 7re>uency and %hase usin C4D&
2& #hevenin=s theore! 3 veri7ication&
"& <orton=s theore! 3 veri7ication&
4& $a8i!u! %o2er trans7er theore! 3 veri7ication&
+& C4 and *4circuits; Fre>uency res%onse; ,*o2 %ass and Hih %ass-&
.& C4 and *4 circuits ; Di77erentiation and interation ; tracin o7 2ave7or!s&
/& *C43Series resonance circuit3Fre>uency res%onse3Deter!ination o7 7
o
A ? and (and
2idth&
0& #o dra2 volt;a!%ere characteristics o7 5unction diode and deter!ine the cut;in
voltaeA 7or2ard and reverse resistances&
'& Cener diode );B Characteristics3 Deter!ination o7 Cener (reakdo2n voltae&
10& )oltae reulator usin Cener diode
11& @5# in%ut and out%ut characteristics ,CE con7iuration- and deter!ination o7 Ih=
%ara!eters&
12& FE# 3Characteristics and deter!ination o7 FE# %ara!eters&
1"& 15# as rela8ation oscillator&
14& *D4; characteristics&
1+& SC4 )olt;a!%ere characteristics&
Note3 St)*ent h%' to 0e&fo&+ %ny 52 e60e&i+ent'#

Electronics 5 of 17
ANDHRA UNIVERSITY
ELECTRONICS SYLLABUS ACADEMIC YEAR 200"!50
B#S$ II Ye%&! Ele$t&oni$'
PPE"$$ nalo+ 'ircuits an, 'ommunications (120 hours-
.N$T# $ ,"0 hours-
,owe& S)00lie'9 4ecti7iers3 Hal72aveA 7ull2ave and (ride recti7iers; E77iciency; 4i%%le
7actor; 4eulation 3 Har!onic co!%onents in recti7ied out%ut 3 #y%es o7 7ilters; Choke
in%ut ,inductor- 7ilter; Shunt ca%acitor 7ilter; * section and section 7ilters 3 @lock diara!
o7 reulated %o2er su%%ly ; Series and shunt reulated %o2er su%%lies 3 #hree ter!inal
reulators ,/0JJ and /'JJ- 3 6rinci%le and 2orkin o7 s2itch !ode %o2er su%%ly
,S$6S-&
.N$T#$$ ,"0 hours-

RC Co)0le* A+0lifie&9 Analysis and 7re>uency res%onse o7 sinle stae 4C cou%led CE
a!%li7ier&
(ee*4%$.9 6ositive and neative 7eed(ack; E77ect o7 7eed(ack on ainA (and 2idthA noiseA
in%ut and out%ut i!%edances&
O0e&%tion%l A+0lifie&'3 Di77erential a!%li7ier; @lock diara! o7 D%;A!%; Bdeal
characteristics o7 D%;A!%; D%;A!% %ara!eters; Bn%ut resistance; Dut%ut resistance;
Co!!on !ode reHection ratio ,C$$4-; Sle2 rate; D77set voltaes 3 Bn%ut (ias current;
@asic D%;A!% circuits; Bnvertin D%;A!%; )irtual round; <on;invertin D%;A!%;
Fre>uency res%onse o7 D%;A!%& Bnter%retation o7 D%;A!% data sheets&
.N$T#$$$ ,"0 hours-
A00li$%tion' of O0!A+0'9 Su!!in a!%li7ier; su(tractor; )oltae 7ollo2er; Bnterator;
Di77erentiator ; Co!%arator; *oarith!ic a!%li7ier; Sine 2ave KWein @rideL and s>uare
2ave KAsta(leL enerators; #rianular 2ave enerator; $onosta(le !ultivi(rator; Solvin
Electronics 6 of 17
si!%le second order di77erential e>uation& @asic D%;A!% series reulator and shunt
reulator&
.N$T#$% ,"0 hours-
Co++)ni$%tion'9 <eed 7or !odulation;#y%es o7 !odulation; A!%litudeA Fre>uency and
6hase !odulation&
A!%litude !odulation;side (ands; !odulation inde8; s>uare la2 diode !odulator;
De!odulation; diode detector&
Fre>uency !odulation 2orkin o7 si!%le 7re>uency !odulator; 4atio detection o7 F$
2aves; Advantaes o7 7re>uency !odulation&
A$ and F$ radio receivers K(lock diara! a%%roachL&
,N!TE) Sol-ing &el%te* 0&o4le+' in %ll the Unit'-
4e7erence @ooks9
1& Electronic Devices and Circuits;$ill!an and Halkias; #ata $c Era2 Hill ,#$H-
2& $icroelectronics; 5& $ill!an and A& Era(el ; #$H
"& D%erational A!%li7iers and *inear Bnterated Circuits; 4a!akant A& Eayak2ad; 6rentice
Hall o7 Bndia ,6HB-&
4& D%erational A!%li7iers and *inear Bnterated Circuits; :& *alkishore ; 6earson Education
+& Analo Electronics; *&:& $ahes2ari and $&$&S& Anand; 6HB
.& A%%lied Electronics; 4&S&Sedha; S Chand GCo
/& 6rinci%les o7 Electronics; )&:& $ehta and 4ohit $ehta ; S Chand GCo
0& A 7irst Course in Electronics 3 A&A&:han G :&:& Dey ; 6HB
'& Electronic Co!!unication Syste!s ; Eeore :ennedy G @ernard Davis ; #$H&
10& Electronic Co!!unication ;D& 4oddy G 5& Coolen; 6HB
11& 6rinci%les o7 Electronic Co!!unication Syste!s 3*ouis E& FrenFel ;#$H

Electronics 7 of 17
N-H" .N$%E"S$TY

B#S$ II Ye%& ! Ele$t&oni$'
P"'T$'(S PPE"#$$ ('0 hours ; "0 Sessions)
Analog Circuits and Communications Lab
1& D&C 6o2er su%%ly and 7ilters&
2& Sinle stae 4C 3 cou%led a!%li7ier 3 7re>uency res%onse&
"& D6;A!% ,BC /41- as
a- Bnvertin a!%li7ier&
(- <on; invertin a!%li7ier&
c- Co!%arator&
4& D6;A!% ,BC /41- as
a- Bnterator&
(- Di77erentiator&
+& D6;A!% as Wien (ride oscillator&
.& Asta(le !ultivi(rator 3 Deter!ination o7 7re>uency ,usin BC/41 D%;A!%-&
/& $onosta(le !ultivi(rator3Deter!ination o7 %ulse 2idth ,usin BC /41D% A!%-&
0& )oltae reulator usin BC; /00+and BC;/'0+&
'& A$ !odulator and De!odulator&
10& F$ !odulator&
11& Si!ulation e8%eri!ents usin a%%ro%riate electronic circuit si!ulation so7t2are&
a- 4C cou%led a!%li7ier&
(- Wien (ride oscillator&
c- Asta(le !ultivi(rator&
d- A!%litude $odulation&
e- Fre>uency $odulation&
Note3 St)*ent h%' to 0e&fo&+ the following e60e&i+ent'
152 Any 7 e60e&i+ent' %+ong the e60e&i+ent n)+4e&'5to50#
122 E60e&i+ent N)+4e& 55 1%848$8* %n* e2 i' $o+0)l'o&y
Electronics 8 of 17
STUDENTS ARE ENCOURA9ED TO DO A SMALL ,RO/ECT :OR; DURIN9 SECOND YEAR
ANDHRA UNIVERSITY
ELECTRONICS SYLLABUS ACADEMIC YEAR 2050!55
B#S$ III Ye%& ! Ele$t&oni$'
PPE" $$$ -i+ital Electronics an, /icroprocessor ,'0 hours-
.N$T#$ ,2" HD14S-

Bntroduction to nu!(er syste!sA *oic ates D4A A<DA <D#A J;D4A <A<DA <D4 ates ;
#ruth ta(les 3 6ositive and neative loic 3 *oic 7a!ilies and their characteristics 3 4#*A
D#*A EC*A ##* and C$DS&3 1niversal (uildin (locks <A<D and <D4 ates& *a2s o7
@oolean ale(ra De $oran=s #heore!s 3 @oolean identities 3 Si!%li7ication o7 @oolean
e8%ressions3 :arnauh $a%s 3 Su! o7 %roducts ,SD6- and 6roduct o7 su!s ,6DS-&
.N$T#$$ ,22 HD14S-
Co+4in%tion%l %n* Se<)enti%l $i&$)it'9 $ulti%le8er and De;$ulti%le8er 3 DecoderA Hal7
adderA Full adder and 6arallel adder circuits& Fli% 7lo%s 3 4SA DA 5: and 5: $aster;Slave
,2orkin and truth ta(les- ; Se!iconductor !e!ories 3 DraniFation and 2orkin;
Synchronous and asynchronous (inary countersA 1%/Do2n counters; Decade counter ,/4'0-
; 2orkinA truth ta(les and ti!in diara!s&
.N$T#$$$ ,2" HD14S-
Int&o*)$tion to Mi$&o$o+0)te& %n* Mi$&o0&o$e''o&9 Bntel 000+ $icro%rocessor 3 central
%rocessin unit C61 3 arith!etic and loic unit A*1 3 ti!in and control unit 3 reister
oraniFation 3 addressA data and control (uses; %in con7iuration o7 000+ and its descri%tion&
#i!in diara!s; Bnstruction cycleA !achine cycleA 7etch and e8ecute cycles&
Bnstruction set o7 000+A instruction and data 7or!ats; classi7ication o7 instructions 3
addressin !odes& Asse!(ly lanuae %rora!!in e8a!%les o7 0 and 1. (it additionA
su(tractionA !ulti%lication and division& Findin the larest and s!allest in a data array&
6rora!!in e8a!%les usin stacks and su(routines&
Electronics 9 of 17
.N$T#$% ,22 HD14S-
Inte&f%$ing 0e&i0he&%l' %n* %00li$%tion'9 6rora!!a(le %eri%heral inter7ace ,02++- ; D/A
and A/D converters and their inter7acin to the $icro%rocessor& Ste%%er !otor control;
seven se!ent *ED&
,N!TE) Sol-ing &el%te* 0&o4le+' in %ll the Unit'-
4e7erence @ooks9
1& Diital 6rinci%les and A%%lications; $alvino G *each; #$H
2& Diital Funda!entals 3 F&*oyd G 5ain; 6earson Education
"& $odern Diital Electronics; 4&6 5ain;#$H
4& Funda!entals o7 Diital Circuits; Anand :u!ar; 6HB
+& Diital Syste!s 3 4aHka!al; 6earson Education
.& Diital Electronic 6rinci%les and Bnterated Circuits; $aini; Willey Bndia
/& Diital Electronics; Eoth!an;
0& Diital Electronics 35&W& @inel G 4o(ert Donova; #ho!son 6u(lishers ,Bndian +
th
Ed-
'& $icro%rocessor Architecture and 6rora!!in 3 4a!esh S& Eoanker; 6enra!
10& Bntroduction to $icro%rocessor 3 Aditya& 6& $athur; #$H
11& $icro%rocessors and $icrocontrollers Hard2are and Bnter7acin; $athivannan; 6HB
12& Funda!entals o7 $icro%rocessors and $icrocontrollers 3 @& 4a!;Dhan%at 4ai G Sons&
1"& Advanced $icro%rocessor and 6eri%heralsA ArchitectureA 6rora!!in and Bnter7ace; A&:&4ay
and :&<& @hurchandi; #$H
14& $icro%rocessor *a( 6re!ier; :&A& :rishna $urthy

Electronics 10 of 17
B#S$ III Ye%& ! Ele$t&oni$'
P"'T$'( PPE"#$$$ ,'0 hours 3 "0 sessions-
Digital Electronics and Microprocessor Lab
) -i+ital E0periments
1& )eri7ication o7 truth ta(les o7 D4A A<DA <D#A <A<DA <D4A EJ;D4 ates ,@y
usin /400;series-
2& Construction o7 ates usin <A<DA <D4 ates&
"& Construction o7 Hal7 and Full adders and veri7yin their truth ta(les&
4& D%eration and veri7yin truth ta(les o7 7li%; 7lo%s; 4SA DA and 5: usin BCs&
+& Construction o7 Decade counters ,/4'0-&
.& Drivin Ste%%er !otor usin 5: 7li%;7lo%
/& Si!ulation e8%eri!ents usin a%%ro%riate electronic circuit si!ulation&
a- 4;(it %arallel adder usin co!(inational circuits&
(- Decade counter usin 5: 7li% 7lo%s&
c- 1%/Do2n counter usin 5: 7li% 7lo%&
d- 1%/Do2n counter usin /4'"&
B) /$'"!P"!'ESS!" (Software)
1& @inary addition G su(traction& ,0;(it G 1.;(it-
2& $ulti%lication G division&
"& 6ickin u% larest/s!allest nu!(er&
4& Arranin 3ascendin/descendin order&
+& Deci!al addition ,DAA- G Su(traction&
.& #i!e delay eneration
') /$'"!P"!'ESS!" (Har,ware)
1& Bnter7acin 4;24 *adder net2ork ,DAC- ,4 (its- to enerate 2ave7or!s&
2& Bnter7acin a ste%%er !otor and rotatin it clock2ise/anti clock2ise throuh a
kno2n anle&
"& Bnter7acin a seven se!ent dis%lay&
4& Bnter7acin ADC 7or te!%erature !easure!ent&
Note3 St)*ent h%' to 0e&fo&+ the following e60e&i+ent'3
,i- Bn Section ,A- any 7our e8%eri!ents a!on e8%eri!ent nu!(ers 1to .
,ii- E8%eri!ent <u!(er / ,aA (A c and d- is co!%ulsory
Electronics 11 of 17
,iii- All e8%eri!ents in section ,@-
,iv- Any t2o e8%eri!ents in section ,C-&
STUDENTS ARE ENCOURA9ED TO DO A SMALL ,RO/ECT :OR; DURIN9 THIRD YEAR

ANDHRA UNIVERSITY
ELECTRONICS SYLLABUS ACADEMIC YEAR 2050!55
B#S$ III Ye%& =Ele$t&oni$'
Electi&e Paper$%()) Em1e,,e, S*stems an, pplications ('0 hours)
.nit $ (22 Hours-
The 2345 /icrocontroller
Int&o*)$tion to +i$&o$ont&olle&' %n* e+4e**e* 'y'te+'9 Dvervie2 and (lock diara! o7
00+1& Architecture o7 00+1& 6rora! counter and !e!ory oranisation& Data ty%es and
directivesA Fla (its and 6SW 4eisterA 4eister (anks and StackM 6in diara!A 6ort
oranisationA B/D 6rora!!inA @it !ani%ulation& Bnterru%ts and ti!er&

.nit$$ ,2" Hours-
,,ressin+ mo,es6 instruction set an, assem1l* lan+ua+e pro+rammin+ of 2345
Addressin !odes and accessin !e!ory usin various addressin !odes& Bnstruction set9
Arith!eticA *oicalA Sinle @itA 5u!%A *oo% and Call Bnstructions and their usae& #i!e
Delay Eeneration and CalculationM #i!er/Counter 6rora!!in& 6rora!!in e8a!%les9
AdditionA !ulti%licationA su(tractionA divisionA arranin a iven set o7 nu!(ers in
ascendin / descendin orderA %ickin the s!allest / larest nu!(er a!on a iven set o7
nu!(ersA Accessin a s%eci7ied %ort ter!inal and eneratin a rectanular 2ave7or!&
.nit $$$ ,22 Hours-
$nterfacin+ of peripherals to /icrocontroller
Bnter7acin o7 ; 66B 02++A DACA ADC& Serial co!!unication; !odes and %rotocols
Electronics 12 of 17
.nit $% ,2" Hours-
pplications of Em1e,,e, S*stems
#e!%erature !easure!entA dis%layin in7or!ation on a *CDA Control o7 a Ste%%er $otorA
Bnter7acin a key(oard and eneration di77erent ty%es o7 2ave7or!s&

"eference Books)
1& #he 00+1 $icrocontrollers and E!(edded Syste!s 3 @y $uha!!ad Ali $aFidi and
5anice Eillis%ie $aFidi; 6earson Education AsiaA 4
th
4e%rintA 2002
2& $icrocontrollers 3 #heory and a%%lications (y AHay )& Desh!ukh;#ata $cEra2;Hill
"& #he 00+1 $icrocontroller ; architectureA %rora!!in G a%%lications @y :enneth 5&
Ayala; 6enra! Bnternational 6u(lishinA 1''+
4& 6rora!!in and Custo!iFin the 00+1 $icrocontroller 3 @y $yke 6redko; #$HA 200"
+& Desin 2ith $icrocontrollers @y ; 5 @ 6eat!an; #$H&
.& #he 00+1 $icrocontroller ; 6rora!!inA inter7acin and a%%lications (y Ho2ard @oyet
and 4on :atF ; ,$BB- $icro%rocessors #rainin Bnc&
/& #he conce%ts G 7eatures o7 $icrocontrollers (y 4aHka!al ; Wheeler 6u(&

Electronics 13 of 17
B#S$ III Ye%& =Ele$t&oni$'
Electi&e Paper $% ()) P"'T$'(S ('0 Hours; "0 Sessions)
Embedded Systems and Applications Lab
/icrocontroller E0periments usin+ 2345 kit
1& $ulti%lication o7 t2o nu!(ers usin $1* co!!and ,later usin counter !ethod 7or
re%eated addition -
2& Division o7 t2o nu!(ers usin DB) co!!and ,later usin counter !ethod 7or re%eated
su(traction -
"& 6ick the s!allest nu!(er a!on a iven set o7 nu!(ers
4& 6ick the larest nu!(er a!on a iven set o7 nu!(ers
+& Arrane In= nu!(ers in ascendin order
.& Arrane In= nu!(ers in descendin order
/& Eenerate a s%eci7ied ti!e delay
0& Bnter7ace a ADC and a te!%erature sensor to !easure te!%erature
'& Bnter7ace a DAC G Eenerate a stair case 2ave 7or! 3 2ith ste% duration and no& o7 ste%s as
varia(les
10& Flash a *ED connected at a s%eci7ied out %ut %ort ter!inal
11& Bnter7ace a ste%%er !otor 3 and rotate it clock 2ise or anti clock 2ise throuh iven anle
ste%s
12& 1sin :eil so7t2are 2rite a %rora! to %ick the s!allest a!on a iven set o7 nu!(ers
1"& 1sin :eil so7t2are 2rite a %rora! to %ick the larest a!on a iven set o7 nu!(ers
14& 1sin :eil so7t2are 2rite a %rora! to arrane a iven set o7 nu!(ers in ascendin order
1+& 1sin :eil so7t2are 2rite a %rora! to arrane a iven set o7 nu!(ers in descendin order
1.& 1sin :eil so7t2are 2rite a %rora! to enerate a rectanular 2ave 7or! at a s%eci7ied %ort
ter!inal
Note3 St)*ent h%' to 0e&fo&+ the following e60e&i+ent'
152 E60e&i+ent' %+ong e60e&i+ent n)+4e&' 5 to 55
122 E60e&i+ent N)+4e&' f&o+ 52 to5> %&e $o+0)l'o&y
Electronics 14 of 17
STUDENTS ARE ENCOURA9ED TO DO A SMALL ,RO/ECT :OR; DURIN9 THIRD YEAR

N-H" .N$%E"S$TY
ELECTRONICS SYLLABUS ACADEMIC YEAR 2050!55
B#S$ III Ye%& =Ele$t&oni$'
Electi&e Paper $% (B) ) -i+ital -esi+n .sin+ %H-( ('0 Hours)
.N$T $ ,22 Hours-
$ntro,uction 7 Beha&ioural /o,elin+
Int&o*)$tion to HDL'9 Di77erence (et2een HD* and other so7t2are lanuaes 3 Di77erent
HD*s in voue& Dvervie2 o7 diital syste! desin usin HD*
B%'i$ VHDL L%ng)%ge Ele+ent'9 Bdenti7iersA Data o(HectsA scalar and co!%osite data
ty%esA D%erators
Beh%-io)&%l Mo*eling with e6%+0le'9 Entity declarationA Architecture (odyA 6rocess
state!ent and se>uential state!ents& Bnertial and trans%ort delay !odelsA creatin sinal
2ave7or!sA sinal driversA e77ect o7 trans%ort and inertial delays on sinal drivers&
.N$T $$ ,2" Hours-
-ata 8low an, Structural /o,elin+
D%t% (low Mo*eling with e6%+0le'9 Concurrent sinal assin!ent state!entA Concurrent
versus se>uential sinal assin!entA Delta delaysA $ulti%le driversA Conditional sinal
assin!ent state!entA selected sinal assin!ent state!entA concurrent assertion state!ent&
St&)$t)&%l Mo*eling with e6%+0le'9 Co!%onent declarationA Co!%onent instantiation and
e8a!%les6 Direct instantiation o7 co!%onent&
.N$T $$$ ,2" Hours-
Su1pro+rams an, Packa+es
Electronics 15 of 17
S)40&og&%+' %n* O-e&lo%*ing9 Functions and %rocedures 2ith si!%le e8a!%les ;
su(%rora! overloadinA D%erator overloadin&
,%$.%ge' %n* Li4&%&ie'9 6ackae declarationA %ackae (odyA desin 7ileA desin li(rariesA
order o7 analysisA i!%licit visi(ilityA e8%licit visi(ilityA li(rary clause and use clause&
A*-%n$e* (e%t)&e'9 Entity state!entsA Eenerate state!entsA Attri(utesA Areate taretsA
%orts and their (ehaviour&
.N$T $% ,22 Hours-
Simulation an, Har,ware mo,elin+
Mo*el Si+)l%tion9 Si!ulation 3 Writin a #est @ench 7or a Hal7 and a Full adder&
H%&*w%&e Mo*eling E6%+0le'9 $odelin entity inter7acesA $odelin si!%le ele!entsA
Di77erent styles o7 !odelinA $odelin reular structuresA $odelin delaysA $odelin
conditional o%erationsA $odelin a clock divider and a %ulse counter&
"eference Books
1& A )HD* 6ri!er ; @y 5&@hasker &A "
rd
edition ; 6HBA <e2 DelhiA 200/
2& Circuit desin 2ith )HD* (y )olnei & 6edroni 3 6HBA <e2 DelhiA 200/
"& Diital Syste!s Desin usin )HD* (y Charles H&4oth 5r&; 6WS 6u(&A1''0
4& Bntroductory )HD* 9 Fro! Si!ulation to Synthesis 3 (y Sudhakar Yala!anchili&;
6earson Education Asia&A 2001
+& )HD* 6rora!!in (y E8a!%le 3 @y Doulas *&6erry&; 4
th
Ed ; #$H&A 2002
.& Funda!entals o7 Diital *oic 2ith )HD* Desin 3 (y Ste%hen @ro2n G Cvonko
)ranesic ; #$H& 2002
7. )HD* 3 Analysis G $odelin o7 Diital Syste!s 3 @y Cainala(edin <ava(i; 2
nd
Ed ;
#$HA 1''0
0& #he Desiner=s Euide to )HD* ; @y 6eter 5& Ashenden ;2
nd
Ed&A 1
st
Bndian 4e%rint;
Harcourt Bndia 6vt& *td&A 2001&

Electronics 16 of 17
B#S$ III Ye%& =Ele$t&oni$'
Electi&e Paper $% (B)) P"'T$'(S ("0 Ho)&'! ?0 Se''ion')
Digital design Using VHDL Lab
%H-( Pro+ram entr*6 simulation 7 implementation ('P(-/ 8P9) usin+ appropriate
H-( Software for the followin+ circuits.
1& All ty%es o7 loic ates ,Data Flo2-
2& Hal7 adder , Data 7lo2A Structural and Sche!atic-
"& Full adder , Data 7lo2A Structural and Sche!atic-
4& Hal7 su(tractor , Data 7lo2A Structural and Sche!atic-
+& Full su(tractor , Data 7lo2A Structural and Sche!atic-
.& #2o control in%ut $u8 3 usin case
/& #2o control in%ut $u8 3 usin conditional sinal assin!ent
0& #2o control in%ut $u8 3 usin selected sinal assin!ent
'& #2o control in%ut D!u8 ; usin case
10& @CD to seven se!ent decoder ,sche!atic-
11& $odelin a 4S;FF 2ith assertionA re%ort G di77erent levels o7 severity ,@ehavioural-
12& $odelin a @CD Counter ,#o% level (ehavioural-
1"& Writin a #est @ench 7or a Hal7 adder
14& Writin a #est (ench 7or Full Adder
Note3 St)*ent h%' to 0e&fo&+ %ny 52 e60e&i+ent'
STUDENTS ARE ENCOURA9ED TO DO A SMALL ,RO/ECT :OR; DURIN9 THIRD YEAR
Electronics 17 of 17