A Linear High Voltage Charge Pump For MEMS Applications

in 0.18µm CMOS Technology

Manuel Innocent∗ , Piet Wambacq,

Stéphane Donnay, Willy Sansen∗∗ , and Hugo De Man∗∗∗
IMEC, Kapeldreef 75, Leuven, Belgium.
∗
Also Ph.D. student at Katholieke Universiteit Leuven.
∗∗
ESAT-MICAS, Katholieke Universiteit Leuven.
∗∗∗
Also professor at Katholieke Universiteit Leuven.
Innocent@imec.be

Abstract
Tunable MEMS components start to appear in wireless
communication systems. They allow for new functionality
such as tunable RF filters or they improve performance
like electrostatically tuned variable capacitors that are
used in voltage-controlled oscillators. However, the re-
quired tuning voltage for these capacitors is often much
higher than the supply voltage of the deep sub-micron
(Bi)CMOS technology which is typically used for these ap-
plications. Therefore we designed a high-voltage charge
pump that can generate an output voltage between -0.7 V
and +14.8 V out of a 1.8 V power supply. It is built in
a 0.18 µm CMOS technology, requires the same control
signals as a regular charge pump and provides a constant
output current of 0.7 µA over its complete voltage range.
This high-voltage charge pump solves the problem of the
high tuning voltage of MEMS variable capacitors at low
power, at a small area cost and in a way which is com-
pletely transparent to the system designer.
1. Introduction
voltage control circuit, we have two options. The first op-
tion is to put the complete high voltage supply over the
output stage. This will either require a dedicated high
voltage technology like Alcatel HBiMOS [5], or dedi-
cated high voltage devices in an (almost) standard tech-
nology [6]. A dedicated high-voltage technology is often
unwanted because of cost reasons. As an alternative, this
paper presents a control circuit for a MEMS variable ca-
pacitor that dynamically adjusts the power supply while
putting only a limited voltage over the output stage. It
does not require any dedicated technology or devices ex-
cept for triple well, which is quite standard in nowadays
CMOS processes with analog options. The output volt-
age is in this case only limited by the N-well to substrate
breakdown voltage. We call this system ”power supply
on demand” and its application to a high-voltage charge
pump for use in a PLL with a MEMS variable capacitor is
the main contribution of the work presented in this paper.
Section 2 discusses the operation of a high voltage
charge pump for use in a phase locked loop (PLL). Section
3 shows the measurement results and section 4 presents
the conclusions.

MEMS components like electrostatically tuned vari- 2. A charge pump with

able capacitors start to appear in RF circuits [1, 2]. Com-
pared to other types of variable capacitors (MOS, PN-
junction), these MEMS variable capacitors can e.g. im-
prove the linearity of tunable RF filters [3] or the phase
noise of voltage controlled oscillators [4]. However, the
tuning voltage required by these devices is typically be-
tween 5 V and 50 V , which is higher than the maximum
supply voltage of a sub-micron CMOS technology. Al-
though the required tuning voltage of these devices can be
changed by design, it is unlikely to go below the rapidly
decreasing supply voltage of scaled CMOS technologies.
Moreover, there is a trade off between the required tun-
ing voltage and other parameters like the mechanical res-
onance frequency, the electrical losses and the linearity of
the device. This implies that the MEMS control circuit
has to generate voltages higher than the supply voltage of
the rest of the system. For the output stage of this high
power supply on demand
The high voltage charge pump (HVCP) is designed for
use as charge pump of a phase-locked loop [7, 8] . It has
the same connections as a standard charge pump [8] (up
and down signals), so to the system designer it acts as a
standard one. It has however a large output voltage range
which is obtained by extending a standard charge pump
with a ”power supply on demand”.
The HVCP (figure 1) consists of two major parts: the
core charge pump with sense amplifier latches and the
high-voltage generator. These two parts are in separate
power supply regions and together they form a closed con-
trol loop. The goal of this loop is to keep the output of the
core charge pump in the middle between it’s high and the
low power supply rail (”high” and ”low” in figure 1). Both
supply rails of the core charge pump region are adjusted,
 Clk
Clkb
LC HVG
(fig.3) Low supply region HVGup
LC High supply region HVGupb C Nwell-sub

Leaf Leaf Leaf Leaf Leaf

UP UP UP UP UP High
HVGdown HVGup Low High

~1.8V
C decouple
Clk Leaf Leaf Leaf Leaf
LC DOWN DOWN DOWN DOWN Low
Up
LC CP+SA MEMS HVGdown C decouple
(fig.2) capacitor HVGdownb
Down
LC

Figure 3. The high voltage generator (HVG) consists of

Figure 1. High-voltage charge pump, consisting of the core
10 identical stages that can pump charge either up or down.
charge pump (CP) (dashed, in the high power supply re-
The last stage is permanently clocked to generate the supply
gion) and the high voltage generator (HVG) (solid lines, in
of the high voltage region.
the low supply region, with an external ground and 1.8V sup-
ply). Signals go from one region to another through a level HVGup HVGupb
converter (LC).

HVGdown HVGup High High Leaf

UP

Clk SA SA
Up Upb
Vupper

Out
In Out
Vlower

Downb Down

Low Low
Leaf
DOWN

Vref1
Vref2
Figure 2. The high supply voltage region contains the core
charge pump and two sense amplifier latches (SA) which
compare the output voltage with its upper and lower limit
and request the high voltage generator to change supply of
the high voltage region accordingly. When the HVCP is used
in a PLL the Up and Down signals come from the phase
frequency detector.
but their difference is constant. This makes the charge
pump very linear over a large voltage range because the
voltage over the output transistors is constant.
The output of the charge pump (figure 2) is the ref-
erence to which the other voltages of the system are ad-
justed. It is buffered with two symmetrical OTAs and then
compared to two reference voltages with sense amplifier
latches [9]. The references are at 40% and 60% between
the high and the low supply rail of the core charge pump.
An output voltage outside this range results in a request
signal (HVGup, HVGdown) to adjust the supply. For ex-
ample, if the output decreases below the lower reference
voltage then the supply voltages of the core charge pump
are decreased until the lower limit drops below the output
again. Thus, an output which is out of range is not cor-
rected by adjusting the output, but by adjusting the power
supply.
HVGdown HVGdownb
Figure 4. Every stage of the high voltage generator consists
of a cell that can pump charge up (top) and a cell that can
pump charge down (bottom).
The supply voltage of the core charge pump is provided
by the high voltage generator (HVG) (figure 3). This HVG
can generate voltages much higher than its own supply
voltage (typically 1.8 V for 0.18 µm CMOS). This is
often realized similarly to the Dickson charge pump of
1976 [10]. However Dickson’s charge pump can only
pump charge to higher voltages; it has no means to lower
the voltage again. The ”power supply on demand” re-
quires that the output voltage can both be increased and
decreased. That is why we use a basic cell with two in-
verters like in [11]. This cell can be connected in reverse
to pump down the charge. Every stage (figure 4) of the
HVG consists of two basic cells connected in parallel; one
to pump charge up and one to pump charge down . Each
stage is located in a separate N-well which is charged to
its own output voltage.
The basic cell of the HVG consists of two capacitors
and two inverters. The inverters are realized with stan-
dard low voltage transistors as none of the voltages over
these transistors exceed the supply voltage. The HVG is
driven by two complementary clock signals. This simple
two-phase clocking scheme allows a high clock frequency
(> 50 MHz ). All stages of the HVG except the last Table 1. Measurement conditions
one, are conditionally clocked. The HVGup and HVG- Supply 1.8 V
down signals are the request signals coming from the core Number of stages 10 + 1
charge pump. The last stage is continuously clocked to Load 22 pF
generate the power supply of the high-voltage region. Clock frequency 50 MHz
The voltage gain ∆V over each stage has two contri- Up and Down signals
butions, as shown by: Frequency 100 kHz
Duty cycle 20 %
C
∆V = Vdd − Rout Iout , (1)
C + Cpar
14
in which the output resistance Rout is
12

1 10
Rout = + Rswitch .

Low supply voltage (V)

(2)
frequency C
8
In the first part, the capacitance C is the coupling capaci-
6
tance in the control lines (HVGup, HVGupb) and Cpar is
parasitic capacitance at the internal nodes of the basic cell, 4
not at the input and output nodes. Hence, the presence of 2
the DOWN cell does not limit the voltage gain of the UP
cell. However, the transistors of the UP cell themselves 0

form a large part of the parasitic capacitance. This implies −2

that these transistors should be small. The second part de-
pends on the output current, so we have to differentiate
between the final stage that generates the supply in high
supply region and the stages that change the absolute volt-
age of that region. The final stage permanently supplies a
current to the circuits in the high supply region, so Rout
has to be small enough to limit the voltage loss in this
stage. This implies transistors with a small on-resistance
and a large capacitor and/or high clock frequency. For the
other stages the situation is different. If this charge pump
is used to control an electrostatically tuned varicap then
only the (dis)charge current of the varicap and the high
supply region has to be delivered. There is no static cur-
rent flowing which means that the maximum voltage is
defined only by the capacitance ratio.
This section explained in a top down way the operation
principle of the high voltage charge pump, the next section
presents the measurement results.
3. Measurements
Our high voltage charge pump is processed in a
0.18 mathitµm CMOS technology. It has a pad-limited
die size of 700µm ∗ 700µm, but the circuit area is only
300µm ∗ 430µm. In this section we will show that the
proposed circuit has a very large output voltage range and
that it is a low power solution which it is scalable to future
CMOS generations.
We measured the high voltage charge pump with a load
capacitance of 22 pF at the output and the oscilloscope
connected to the low supply rail of the high voltage region.
The input resistance of the oscilloscope is 1 MΩ , which
is too low to connect directly to the charge pump output.
Table 1 summarizes the measurement conditions.
Figure 5 shows a transient measurement of the low sup-
ply rail of the high voltage region. From the transient mea-
surement we can calculate the charge pump output cur-
−2 0 2 4 6 8 10
Time (s) −3
x 10
Figure 5. The transient measurement of the low supply rail of
the high voltage region shows that the charge pump is very
linear. The output current is constant over the complete
voltage range.
rent:
Cload ∆V
Iout = , (3)
∆t DutyCycle
The current consumption depends strongly on the op-
erating regime. The maximum current of 1 mA is drawn
when the output is limited by conduction or breakdown of
the N-well to substrate junction. In normal operation this
is also the maximum current that can occur during tran-
sients. In steady state, with a 50 MHz clock signal, but
without up or down pulses, the current is only 85µA and
the leakage current is so small that we could not measure
a difference in output voltage after 1 second. In a PLL in
lock, the up and down pulses are very small so that the
current consumption will be very close to this 85 µA, so
this can be regarded as a low power solution. When the
clock is also turned off, the supply current drops to only a
few nA.
The high voltage generator has 10+1 stages and a sup-
ply of 1.8 V , so the theoretical maximum output voltage
(without parasitic capacitances) is 19.8 V . However, the
measurement shows only 13.2V at the ”Low” node plus
1.6V over the final stage, which is only 14.8 V . This dif-
ference is larger than what is expected based on the para-
sitic capacitance, but it is explained by the characteristics
of the N-well to substrate junction. The high supply volt-
age region is inside an N-well which is charged to the high
supply rail of this region. The highest possible voltage in
the system is the breakdown voltage of the well to sub-
 0.01
0.005
Current (A)
−0.005
−0.01
−2 0 2 4 6 8 10 12 14
Voltage (V)
Figure 6. Measured current through an N-well to substrate
junction as a function of the bias voltage for 0.18µm CMOS.
At negative voltage the diode conducts. At positive voltage
it breaks down. These two voltages limit the output range
of the high voltage charge pump.
Table 2. Measurement results
Output current 0.7 µA
Supply current max 1.0 mA
Supply current idle (50 MHz clock) 85 µA
Supply current leakage (no clock) 2.5 nA
Voltage range (at ”Low” node) −0.7 V . . . +13.2 V
Voltage range (at output) −0.7 V . . . +14.8 V
strate junction which is 14.8 V for the used technology
(figure 6). Any attempt to charge the well to a higher volt-
age results in charge flowing away to the substrate. As
the breakdown voltage poses the fundamental limit on the
output voltage we checked it for several technologies. The
results are all in the same range e.g. 16.2 V for a 0.35 µm
BiCMOS technology and 17.5 V and 18.5 V volts for two
flavors of 0.09 µm CMOS technology. This shows that the
circuit can be used in future technologies. Table 2 summa-
rizes the measurement results.
4. Conclusions
This paper presents a high voltage charge pump de-
signed for use in a charge pump phase locked loop with
a MEMS varicap based voltage controlled oscillator. The
charge pump generates output voltages between −0.7 V
and +14.8 V out of a 1.8 V power supply. It delivers a
constant output current over the complete voltage range.
It is built in 0.18 µm CMOS technology and it is scal-
able to future CMOS generations. The output voltage is
only limited by the (N-)well to substrate breakdown volt-
age. This high voltage charge pump solves the problem
of the high required tuning voltage of MEMS variable ca-
pacitors at low power and at a small area cost. It requires
the same control signals as a regular charge pump so it is
completely transparent to the system designer.
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Figure 7. The high voltage charge pump chip is 700 µm ∗
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