Verilog HDL

Introduction
Evolution of Verilog
1984: Gateway Design Automation introduced Verilog
1989: Gateway merged into Cadence Design Systems
1990: Cadence put Verilog HDL into the public domain
1993: OVI enhanced the Verilog language not well accepted
1995: IEEE standardized the Verilog HDL (IEEE 1364 -1995)
2001: IEEE standardized the Verilog IEEE Std 1364-2001

The revision of the language is also done in 2002 and 2005, but
verilog 1364-2001 is in use.
Typical Design Flow

Design Specification
Design
Design Entry
Design Verification
Synthesis
Design/Timing Verification
Design/Timing Verification
Place & Route
What we use Verilog for ?
Verilog is used for implementation of design
and test-bench
Verifying the design functionality
(verification/validation)
Input to CAD tools (synthesis, Place & Route)

Features of Verilog
Verilog is case sensitive.
key words are defined in lower case.
Most of the syntax is adopted from C (but it
may not work like it works in C).
Verilog can be used to model a digital circuit at
Algorithm, RTL, Gate and Switch level.
It supports advanced simulation features like
TEXTIO, PLI, UDPs.
There is no concept of package.
Comments
Comments can be specified in two ways (exactly the
same way as in C/C++):
Single line Comment : Begins with double slashes
(//).
Block Comment: Enclose comments between the
characters /* and */.

Example
a = c + d; // this is a simple comment

/* however, this comment continues on more
than one line */
Identifier
Identifiers are user-defined words for variables,
function names, module names, block names and
instance names.
The basic rule for identifiers
- May contain letters (A-Z, a-z), digit(0-9), _ and $.
- Must begin with a letter or underscore (Not with a
number or $).
- Identifiers in Verilog are case-sensitive.

Example
Adder, by_8_shifter, _ABC_
Keywords
Special identifiers reserved to define language
constructs.
Must be in lower case.

Example
always, initial, module etc.

Numbers
Types of number specification in verilog:
- Sized Numbers
- Unsized Numbers

Syntax:
<size><base format> <number>

Size : is a decimal no. which specifies the number of bits
present in the number.
Base format:
- d or D for decimal
- f or H for hexadecimal
- b or B for binary
- o or O for octal


Numbers
Signed Numbers
- (s/S) before format specifier will be interpreted as
2C.

X or Z values
X unknown value
Z high impedance value


Number Examples
567 // decimal number by default
h345 // hexadecimal number
o145 // octal number

3b011 // 3-bit binary number
5o121 // 5-bit octal number

8d-5 // illegal syntax
-8d5 // 2C of 5

16h23x // 16-bit hex number, with 8 LSBs are unknown
6bz // 6-bit high impedance binary number

12b1010_0011_1100 // _ is allowed anywhere except in the
beginning, to improve readability of numbers



Module
A module is the principal design unit in Verilog.
Module Declaration:
module <module_name >(port_list);
input [msb:lsb] input_port_list;
output [msb:lsb] output_port_list;
inout [msb:lsb] inout_port_list;
... statements ...
endmodule // no semicolon

- Port list gives details of ports through which module communicates with
the external modules
- Ports can be input, output or inout (bi-directional)
Module (Contd.)
It describes both designer interface to other designs,
and its functional composition.
All the declaration used in the design must be
defined locally with in the module.
Functional composition is the description of
structure using primitive, data flow assignments and
sequential construct.
A module can be instantiated as component in
another module.
Module Definition (Example)
module DFF ( D, Q, Clk);
input D ;
input Clk ;
output Q ;
<Architecture>
endmodule

Modules communicate with the outside world through input,
output and bi-directional (inout) ports.
D
DFF
Q
Clk
Data Types
Value set
Nets
Registers
Integer
Real
Time
Parameter
Arrays


Data Types
Value Set
Verilog supports four basic values
- 0 (logic zero or false condition)
- 1 (logic one or true condition)
- X (unknown logic value)
- Z (High impedance)

Values x and z are case-insensitive
Constant in verilog is made up of four basic
values
Data Type
Net type

Represents a physical connection between structural
elements
If no driver is connected it defaults to value of z
Net declaration is defined as follows
net_kind [msb : lsb] net1,net2,. netN;
Wire is the most widely used net data type
Other net data types are wand, wor, tri, triand, trior etc.

Example
wire sum, cout, a, b;
wire [ 2:0 ] addr;
Data Type
Register Type
represents an data storage element
assigned only within an always or initial statement
Its value is saved from one assignment to the next
Used to model synchronous hardware and to apply stimulus in
testbench
Verilog supports four kinds of register data types:
- reg : unsigned storage of varying bit width
- integer : signed 32-bit integer variable
- time : unsigned 64-bit integer variable
- real : signed double precision floating point variable

Data Type
reg data type

Reg kind of register is most commonly used
It has default value of x
It is declared as
reg [msb : lsb] reg1,reg2,regN;
Value stored in registers is interpreted as unsigned number

Example
reg [3:0] dout;
reg b1;

Data Type
Integer Register

It contains integer values
It can be used as general purpose variable
It holds a min of 32 bits and is implementation dependent
It holds signed values
It is declared as
integer integer1,.integerN [msb:lsb];

Example
integer a;

Data Type
Time Register

It is used to store and manipulate time values
If range is not specified then each identifier specifies one
time value which is atleast 64 bits
It holds unsigned quantity
not supported for synthesis
It is declared as:
time time1, time2,timeN [msb:lsb];

Example
time c;
c=$time; // c= current simulation time

Data Type
Real Register

Default value of real register is 0
A real register is declared as:
real real_reg1,real_reg2.real_regN;

Example
real sum; // define a real variable called sum

Data Types
Parameter
Defined as constant with in the module.
Cant be used as variables.
Can be changed on instance by instance basis.

Example
parameter clk_period = 20;


Arrays
Verilog support one dimensional as well as
multidimensional arrays for
- reg
- integer
- time
- real
- wire
Choosing Correct Data type for ports
Follow these rules while choosing data types
for ports:
- An input and inout port must be a net data
type
- An output port can be declared as reg data
type also.
- A signal assigned a value in procedural block
must be a register data type.
Continuous Assignment

- Used to model combinational circuits
- Assigns a value to net only

- Usage of continuous assignment
assign LHS_target = RHS_expression;

- Continuous assignment statement are always active ie.
Change on any operand results in evaluation of the RHS
expression
- RHS expression may consists of net or reg (scalars or
vectors) or function calls
- Cannot occur in sequential block
- Target in a continuous assignment is one of the following
- Net Scalar
- Net Vector

Continuous Assignment
(Example)

Full
Adder


A
B
Cin
Cout
module full_adder (Sum, Cout, A,
B, Cin);

output Sum;
output Cout;
input A;
input B;
input Cin;

assign {Cout, Sum} = A+B+Cin;

endmodule

Sum
Primitives
Verilog has various built in primitives.
Organized as follows:
- Logic Gates : and, or, nand, xor, nor etc.
- Buffers: buf, pulldown, pullup etc.
- Transistor: nmos, pmos, cmos etc.
First port in built in primitive is output port.
The same primitive can be used for more
number of inputs.
Simple Program for 2:1 Mux
module mux (mux_out, in1, in2,
sel);
output mux_out ;
input in1, in2, sel;

and g1 (out1, in1, sel),
g2 (out2, in2, sel_n);
or g3 (mux_out, out1, out2);
not g4 (sel_n, sel);
endmodule

in2
in1
sel
mux_out
sel_n
out2
out1
g2
g1
g3
g4
2:1 Mux (New ANCI C Style, 2001 )
module mux (output mux_out,
input in1, in2, sel);

and g1 (out1, in1, sel),
g2 (out2, in2, sel_n);
or g3 (mux_out, out1, out2);
not g4 (sel_n, sel);
endmodule

Module Instances
A copy of a module can be interconnected within other modules -
this is known as making an instance of a module
Each instance is a complete, independent and concurrently active
copy of a module
CPU
MEMORY
ALU
MEMORY
glue
logic
SYSTEM
ALU A1
MEM MEM2
C
c
c
c
always
c
c
c
c
module
SYSTEM
endmodule
MEM MEM1
CPU C1
Module Instances (Contd.).
- A module can be instantiated in another module thus creating
hierarchy


- It is of the form
module_name Instance_name (Port_Association_List);

Module Instances (Contd.).
An example :
DFF1
DFF2
D
DFF Q
CLK
D
DFF Q
CLK
SYNCHRO
CLOCK
ASYNC
C1_ASYNC
SYNC
Module port connection by order
module SYNCHRO (ASYNC , SYNC , CLOCK ) ;
input ASYNC ;
input CLOCK ;
output SYNC ;
DFF DFF1 (
ASYNC ,
C1_ASYNC ,
CLOCK
) ;
DFF DFF2 (
C1_ASYNC ,
SYNC ,
CLOCK
) ;
endmodule

Module port connection by Name
module SYNCHRO (ASYNC , SYNC , CLOCK ) ;
input ASYNC ;
input CLOCK ;
output SYNC ;
DFF DFF1 (
.D (ASYNC) ,
.Q(C1_ASYNC) ,
.CLK (CLOCK)
) ;
DFF DFF2 (
.D(C1_ASYNC) ,
.Q(SYNC) ,
.CLK(CLOCK)
) ;
endmodule

Instance names
It is only the instance name that uniquely identifies a
particular element in a module
Instance names used within a module should be unique


For example,
module A ( ) ;
DFF DFF1 ( ) ;
DFFE DFF1 ( ) ;
endmodule
IS NOT ALLOWED

Assignment
Write the code for single bit full adder and
extend it up to 4-bit using the idea of
component instantiation.
Write the program of D latch using gate
primitives.
Operators
Arithmetic
Relational
Equality
Logical
Bit-wise
Reduction
Shift
Concatenation
Replication
Conditional
Operators
Depending on number of operands
Unary
Binary
Ternary

Arithmetic Operators(Binary)
+ (addition)
- (subtraction)
* (multiplication)
/ (division)
% (modulus)
** (exponent)
Arithmetic Operators - Example
A = 4b0010; B = 4b1101;// vector of wire/reg type
D = 3; E = 5; F =2; G = 5; // integer type

A + B // evaluates to 4b1111
A - B // evaluates to 4b1011
B - A // evaluates to 4b0101
A * B // evaluates to 4b1111
D + E // evaluates to 4b1111
E / D // evaluates to 1, i.e. truncates fractional part
E ** F // evaluates to 25
E % G // evaluates to 0
E % D // evaluates to 2


Arithmetic Operators - Example
If any operand has x/z value, then the result of entire
expression is x.

Example:
A = 4b0010; B = 4b1x01;// vector of wire/reg type

A + B // evaluates to 4bx


Relational Operators
Compare two operands and return a single bit
(1,0,X)
< (less than)
<= (less than or equal to)
> (greater than)
>= (greater than or equal to)
Equality Operators
Logical Equality (return 1,0,x)
== (equal to)
!= (not equal to)

Case Equality (return 1,0)
=== (equal to)
!== (not equal to)

Logical Operators
! (logical NOT or negation) - Unary
&& (logical AND) - binary
|| (logical OR) - binary
Logical Operators
return a single bit (1,0,X)
If operand is not equal to zero, it is equivalent
to a logical 1 (true condition).
If operand is equal to zero, it is equivalent to a
logical 0 (false condition).
If any operand bit is x or z, it is equivalent to x
(ambiguous condition) and is normally treated
by the simulator as a false condition.


Bit-wise Operators
Operates on each bit of a vector
~ (bitwise NOT)
& (bitwise AND)
| (bitwise OR)
^ (bitwise XOR)
~^ or ^~(bitwise XNOR)

Example
4b0011 & 4b1100 //0000
Unary Reduction Operators
& (reduction AND)
| (reduction OR)
~& (reduction NAND)
~| (reduction NOR)
^ (reduction XOR)
~^ or ^~(reduction XNOR)
Shift Operators
The shift operators shift the given number to left or
right, by the right operand
<< (shift left)
>> (shift right)

Example
8b00110111<<2 //11011100
8b00110111>>2 //00001101
8b00110111<<-2 //00000000
8b00110111<<1bx //xxxxxxxx
8b00110111<<2bz //xxxxxxxx





Concatenation Operator
Combines two or more operands to form a larger
vector
{} (concatenation)
Example
reg [7:0] a,b,c,z;
a = 8b11110000;
b = 8b11010000;
c = 8b11110011;
z = {a[1:0],b[5:3], c[7:5]}; //00_010_111


Replication Operator
{n{item}} (n fold replication of an item)

Example
Wire [1:0] a;
Wire [4:0] y;

assign y = {a,2{1b0}}; //aa00
Conditional Operator
(cond) ? (result if cond true):(result if cond false)

Example
module mux (mux_out, in1, in2, sel);

output mux_out;
input in1, in2, sel;

assign mux_out = sel ? in1 : in2;

endmodule

Assignment
Design 4:16 decoder using shift operator.
Design 8:3 priority encoder.
Test bench
Test bench generates stimulus and checks for response

Coupled with Design Under Test (DUT)

Pair is run simultaneously
Testbench
Design Under Test
(DUT)
Stimulus
Response Result checker
Test Bench for MUX 2:1
module TB_mux ;
reg in1, in2, sel;
wire mux_out;

// Instantiating the design of MUX
mux m1 ( .mux_out (mux_out), .in1(in1), .in2(in2), .sel(sel));
initial
begin
in1=0; in2=0; sel=0;
# 50 sel=1;
# 50 in1=1;
# 50 sel=0; in2=1;
# 50 sel=1; in1=0;
# 100 $finish;
end
endmodule