EXPERIMENT NO: DATE:

Department of BCA and B.Sc (CS),KSCD

REALISATION OF LOGIC GATES

AIM: Using NAND gate IC7400, Set up the following gates:
NOT
AND
OR
NOR
XOR(Exclusive-OR)
Write their logic symbol, Boolean expression and verify the truth table.

APPARATUS: 2 input NAND gate IC7400,Digital Trainer Kit(DTK) and
connecting wires.

THEORY:
Logic gates are the basic elements that make up a digital system. The electronic gate
is a circuit that is designed to perform a specific logic function. On a more technical
term, a logic gate is an electronic circuit that accepts one or more binary inputs and
produces a single binary output .
Operation of a logic gate can be clearly understood with the help of the truth table.
A truth table is a tabular representation that depicts all possible combination of
input(s)
and the corresponding output.
NAND gate is known as a universal gate since all other gates can be realized using
NAND gate IC 7400 is a 14 pin chip, having four 2 input NAND gates housed in a
single package

NOT Gate: It performs basic inversion function i.e., it changes logic 0 to logic 1 and
logic 1 to logic 0. Hence it is also called an inverter. This is the simplest form of a
logic gate.

AND Gate: It performs logical multiplication. It produces a HIGH output only
when all the inputs are HIGH. If any one of the input is LOW, then the output will
be LOW.

OR Gate: It performs logical addition. It produces a HIGH output when at least one
of the inputs is HIGH. The output is LOW only when all the inputs are LOW.

EXPERIMENT NO: DATE:
Department of BCA and B.Sc (CS),KSCD
NOR Gate: This is also one of the universal gates along with NAND gate. NOR gate
is a combination of OR and NOT gate. Hence the output is the compliment of an OR
gate i.e., it produces a HIGH output only when all of the inputs are LOW. If any of
the inputs is HIGH, then the output is LOW.
XOR (Exclusive-OR) Gate: It produces a LOW output only when all the inputs have
the same value, either LOW or HIGH. For all other combinations the output is
HIGH.

PIN DIAGRAM OF IC 7400(2 INPUT NAND gate):














TRUTH TABLE FOR 2 INPUT NAND GATE:

INPUT OUTPUT
A B Y=A.B
0 0 1
0 1 1
1 0 1
1 1 0


Symbol of NOT gate





EXPERIMENT NO: DATE:
Department of BCA and B.Sc (CS),KSCD


Here bubble indicates inversion.
Boolean expression: Y=A (NOT of A / Complement of A)

NOT gate using NAND gate





Truth table

INPUT OUTPUT
A Y=A
0 1
1 0


Symbol of AND gate:




Boolean Expression: Y = A . B ( A AND B)

AND gate using NAND gate:




Truth Table:
INPUT OUTPUT
A B Y = A . B
0 0 0
0 1 0
1 0 0
1 1 1

EXPERIMENT NO: DATE:
Department of BCA and B.Sc (CS),KSCD
Symbol of OR gate:



Boolean Expression: Y = A + B ( A OR B)
OR gate using NAND gate:










Truth Table:
INPUT OUTPUT
A B Y = A + B
0 0 0
0 1 1
1 0 1
1 1 1

Symbol of NOR gate:





Boolean Expression : Y = A + B ( A NOR B / Complement of A OR B))

NOR gate using NAND gate:






EXPERIMENT NO: DATE:
Department of BCA and B.Sc (CS),KSCD





Truth Table:
INPUT OUTPUT
A B Y = A + B
0 0 1
0 1 0
1 0 0
1 1 0

Symbol of XOR gate:




Boolean Expression: Y = A + B( A Exclusive OR B)

XOR gate using NAND gate:















Here,
Y1 = AB
Y2 = AB . A = AB + A = AB + A
EXPERIMENT NO: DATE:
Department of BCA and B.Sc (CS),KSCD
Y3 = AB . B = AB + B = AB + B




Now , Y = Y2 . Y3
Y = (A + AB) . ( B + AB )

= (A + AB) + (B + AB)

= ( A . AB) + (B . AB)

= ( A . AB ) + ( B . AB)

= ( A . (A + B)) + ( B . ( A + B))

= AA + AB + BA + BB

= AB + AB

Hence , Y = A + B


Truth Table:

INPUT OUTPUT
A B Y = A + B
0 0 0
0 1 1
1 0 1
1 1 0






EXPERIMENT NO: DATE:
Department of BCA and B.Sc (CS),KSCD
HALF ADDER AND FULL ADDER

AIM:- To design and test half adder and full adder circuit during two input NAND gate.
APPARUTS:- IC 7400 , Digital trainer kit (DTK), connecting wires etc.
THEORY:- Half Adder
When we want to add two binary numbers each having one bit we require two inputs
that produce a sum and carry output as in figure(1). The sum is exclusive or of two input,
while carry is AND of same two inputs. This is due to fact that X-OR produces zero outputs.
When both inputs are different output of X-OR gate is, one AND gate
Produces a high output only when both input are high. Therefore equation for sum (S) and
carry (C) are
S= A B
C
O
= AB
Here NAND gates are from X-OR gate AND gate. The half adder circuit designed using NAND
gate is in fig(11) truth table of half adder is as in the table shown
Half Adder logic symbol:-




Half Adder using NAND GATE.





EXPERIMENT NO: DATE:
Department of BCA and B.Sc (CS),KSCD
Truth table:-
Input Output
A B S C
O





FULL ADDER:
THEORY:- A combination circuit that performs the addition of 3 bits C2 significant bit A
1
and
B
1
and previous carry is a full adder as the logic symbol is as shown in figure (a). It accepts 3
inputs and generate the sum output S
i
and a carry output C
O.
Two input out of 3 are denoted
by A
1
+B
1
represents 2 significant bits to be added the third input C1 is the carry at the
previous stage output two Boolean function that represents the sum
S
i
= A
1
B
1
C
1

C
0
= AB+BC+CA
Here NAND gates are used to realize these 2 Boolean functions full
adder circuit designed using NAND gate is as shown in figure (b). Truth table of full adder is
shown in table (2) K map used to arrive at above Boolean functions are also written in table

Truth table:
INPUTS OUTPUTS
A B C
in
S C
O










EXPERIMENT NO: DATE:
Department of BCA and B.Sc (CS),KSCD



FULL ADDER logic symbol




FULL ADDER using NAND gate.












Conclusion:


EXPERIMENT NO: DATE:
Department of BCA and B.Sc (CS),KSCD
MONSTABLE MULTIVIBRATOR

AIM:- Set up monostable multivibrator using IC 555 timer calculate the pulse width of the
output & compare it with observed pulse width.

APPARATUS:- IC 555 timer, resister, capacitors, CRO,dtk.

FORMULA:- Pulse width = on state period = 1.1 R
A
C Sec
Where R
A
= Resistance in
C = Capacitance in farad

THEORY:- Monostable multivibrator is also often called as one-shot multivibrator. It is the
pulse generating circuit. Width of pulse generated by multivibrator is determined by the R
A
C
network connected internally to 555 timer. It generates a single pulse out for each time a
rigger pulse is applied to pin (2) monostable scale the output of circuit is approximately zero
or at logical low state.


EXPERIMENT NO: DATE:
Department of BCA and B.Sc (CS),KSCD

CRO cathode pass oscilloscope
C & C
1
Capacitors of 0.1F R
A
- Resistor
Nature of input & output trigger waveform:



EXPERIMENT NO: DATE:
Department of BCA and B.Sc (CS),KSCD
When a external trigger pulse is applied the output is forced to high (

V
cc
) The time
of the output remains high is determined by external R
AC
network connected to timer R
AC

time constant controls the width of the output pulse.
At the end of the timing internal output automatically reverts back to
.0 its logic low state. This output low state remains low until the trigger pulse is
applied again then cycle repeats.
Monostable circuit has only one stable state output low hence it is called monostable.
The time period during which output remains high is called on state period or pulse width
represented by
Tp = 1.1 R
A
C sec
Here R
A
must be in ohms & C in farad. The input trigger & output waveforms are as
shown in figure. Once monostable multivibrator is triggered the output will remain in the
high state until the set time T
P
collapses.
The output will not change its state even if the input trigger is applied again during
this time interval T
P
.
Observations:-
Capacitance of capacitor c =
Sl.
No
Resistance RA
in K
Calculate pulse
O/P
TP =
Width of
O/P pulse A
in div
Position of time
base S with B
O/P pulse
width T =



EXPERIMENT NO: DATE:
Department of BCA and B.Sc (CS),KSCD






Calculation: -