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Date of Performance:08-04-2014
Registration No:11102590
Exp.No:10
Roll No:B47
Aim:Impliment moore mealy sequence
Attach Graph/Simulation Waveforms:
1.Mealy
Program code:
1.Moore
module sd0110(out,count,nst,pst,din,reset,clk);
input din,reset,clk;
output reg out;
output reg [2:0] count,pst,nst;
parameter s0=3'b000;
parameter s1=3'b001;
parameter s2=3'b010;
parameter s3=3'b011;
parameter s4=3'b100;
always@(posedge clk)
begin
if(reset)
begin
out<=0;
count<=0;
pst<=s0;
end
else
pst<=nst;
if(out)
count=count+1;
end
always @(pst or din)
begin
case(pst)
s0:begin
out<=0;
if(din)
nst<=s0;
else
nst<=s1;
end
s1:begin
out<=0;
if(din)
nst<=s2;
else
nst<=s1;
end
s2:begin
out<=0;
if(din)
nst<=s3;
else
nst<=s1;
end
s3:begin
out<=0;
if(din)
nst<=s0;
else
nst<=s4;
end
s4:begin
out<=1;
if(din)
nst<=s2;
else
nst<=s1;
end
endcase
end
endmodule
2.Mealy
module mely10110(out,count,nst,pst,din,reset,clk);
input din,reset,clk;
output reg out;
output reg [2:0] count,pst,nst;
parameter s0=3'b000;
parameter s1=3'b001;
parameter s2=3'b010;
parameter s3=3'b011;
parameter s4=3'b100;
always@(posedge clk)
begin
if(reset)
begin
out<=0;
count<=0;
pst<=s0;
end
else
pst<=nst;
if(out)
count=count+1;
end
always @(pst or din)
begin
case(pst)
s0:begin
if(din)
begin
nst<=s1;
out<=0;
end
else
begin
nst<=s0;
out<=0;
end
end
s1:begin
if(din)
begin
nst<=s2;
out<=0;
end
else
begin
nst<=s1;
out<=0;
end
end
s2:begin
if(din)
begin
nst<=s3;
out<=0;
end
else
begin
nst<=s0;
out<=0;
end
end
s3:begin
if(din)
begin
nst<=s3;
out<=0;
end
else
begin
nst<=s2;
out<=0;
end
end
s4:begin
if(din)
begin
nst<=s1;
out<=0;
end
else
begin
nst<=s2;
out<=1;
end
end
endcase
end
endmodule
Testbench:
1.Moore
module TB_SD0110_v;
// Inputs
reg din;
reg reset;
reg clk;
// Outputs
wire out;
wire [2:0] count;
wire [2:0] nst;
wire [2:0] pst;
// Instantiate the Unit Under Test (UUT)
SD0110 uut (
.out(out),
.count(count),
.nst(nst),
.pst(pst),
.din(din),
.reset(reset),
.clk(clk)
);
initial begin
$monitor($time,"reset=%b,din=%b,out=%b,count=%b",reset,din,out,count);
// Initialize Inputs
din = 0;
reset = 1;
clk = 0;
// Wait 100 ns for global reset to finish
#10 reset=0;
din=1;
#10 din=0;
#10 din=1;
#10 din=1;
#10 din=0;
#10 din=1;
#10 din=1;
#10 din=0;
#10 din=1;
#10 din=1;
#10 din=0;
#10 din=1;
#20 $stop;
// Add stimulus here
end
initial begin
forever
#5 clk=~clk;
end
endmodule
2.Mealy
module tb_mele_v;
// Inputs
reg din;
reg reset;
reg clk;
// Outputs
wire out;
wire [2:0] count;
wire [2:0] nst;
wire [2:0] pst;
// Instantiate the Unit Under Test (UUT)
mely10110 uut (
.out(out),
.count(count),
.nst(nst),
.pst(pst),
.din(din),
.reset(reset),
.clk(clk)
);
initial begin
$monitor($time,"reset=%b,din=%b,out=%b,count=%b",reset,din,out,count);
// Initialize Inputs
din = 0;
reset = 1;
clk = 0;
// Wait 100 ns for global reset to finish
#10
reset=0;
din=1;
#10 din=0;
#10 din=1;
#10 din=1;
#10 din=0;
#10 din=1;
#10 din=1;
#10 din=0;
#10 din=1;
#10 din=1;
#10 din=0;
#20 $stop;
// Add stimulus here
end
initial begin
forever
#5 clk=~clk;
end
for a Mealy machine, each arc (transition) is labeled with an output value.
To be filled by Faculty
S.No.
Max. Marks
Marks Obtained
and 10 excellent)
20
20
Completion* of experiment,
Discipline and Cleanliness
10