Escolar Documentos
Profissional Documentos
Cultura Documentos
I.
INTRODUCCIN
library ieee;
use ieee.std_logic_1164.all;
entity MOORE is
port (CLK: in std_logic;
Z: out std_logic);
end MOORE;
end case;
end process proceso1;
proceso2: process (CLK) begin
if (CLK'event and CLK = '1')then
Edo_Pres <= Edo_Fut;
end if;
end process proceso2;
end ARQ_MOORE;
VI. BIBLIOGRAFA
[1]
T.L. Floyd, Digital Fundamentals, 9th Edition,
Prentice Hall, 2006.
[2]
Peter J. Ashenden. The VHDL Cookbook.
First Edition. Department of Computer Science.
University of Adelaide. South Australia. 1990.
[3]
[4]
Alteras FPGA development boards DE1 and
DE2, User manuals. Available at www.altera.com and
www.terasic.com
[5]
IEEE Standard VHDL Language Reference
Manual. IEEE Std 1076-2002.