Int. J. Electron. Commun.

(AE) 65 (2011) 458467

Contents lists available at ScienceDirect

International Journal of Electronics and

Communications (AE)
journal homepage: www.elsevier.de/aeue

A low power, low phase noise, square wave LC quadrature

VCO and its comprehensive analysis for ISM band
Mojtaba Atarodi, Pooya Torkzadeh , Baktash Behmanesh
SICAS Group, Electrical Engineering Department, Sharif University of Technology, Azadi Ave., Tehran, Iran

a r t i c l e

i n f o

Article history:
Received 6 February 2010
Accepted 7 July 2010
Keywords:
Voltage-controlled oscillators (VCO)
Third harmonic tank
Phase noise amount
Power consumption

a b s t r a c t
This paper presents a phase-noise reduction technique for voltage-controlled oscillators (VCOs) using
a harmonic tuned (HT) LC tank. The phase-noise suppression is achieved through almost rectangularshaped VCO oscillating signal which effectively maximizes oscillating signal slope at zero crossing points
resulting in-phase-noise degradation. In addition, by shortening down converted noise power around
oscillating signal second harmonic, more phase-noise suppression has been achieved. A comprehensive
analysis for frequency and amplitude deviations as high as 20% for third harmonic and its effect on
output phase-noise suppression has been discussed. In the followings, a comprehensive analysis on timevariant theory of phase noise where a more simplistic time-invariant approach fails to explain numerical
simulation results even at the qualitative level has been exposed. General closed-form formulas are
derived for the phase noise generated by LC tanks losses and MOS transistors noisy current. It is also shown
that by using third harmonic tank on VCO and steering coupling and coupled section current sources by
quadrature signals, total phase-noise improvement will be as high as 9 dB compared to conventional
structures. Designed harmonic tuned LC Quadrature VCO has been fabricated using 0.18 um 1P6M CMOS
technology operating at 1.8 V for frequency band of 2.42.6 GHz with achieved phase noise of 136 dBc/Hz
at frequency offset of 3 MHz. Total current drawn by VCO is 3.9 mA making the power consumption as
low as 7 mW with the silicon area of 500 um 500 um. Implemented HT VCO gure-of-merit (FOM) is
186 dB making the implemented VCO superior compared to the recently published VCOs. An extensive
spectreRF simulation covering a wide range of operating conditions has been used to verify the theoretical
analyses.
2010 Elsevier GmbH. All rights reserved.

1. Introduction
In the wireless industry, the great challenge is the high-level
integration of functional blocks using low-cost CMOS technology.
Among the efforts for the single-chip radio integration, the implementation of a low phase-noise voltage-controlled oscillator (VCO)
attracts a lot of attention as long as VCO phase noise is one of the
most critical parameters for information transfer function quality
of service (QOS). As CMOS downscaling is in progress, the corner
frequency of transistors tends to be increased resulting in more
problems for CMOS based VCO blocks. Moreover, the integration of
a high-LC tank is not too facile due to the low resistivity of silicon
substrate and this greatly affects the phase-noise performance. In
this paper an optimization technique for decreasing phase noise
together with keeping power consumption as low as possible will
be presented. The phase-noise suppression is achieved through

Corresponding author. Tel.: +98 912 3495 492; fax: +98 21 8868 5347.
E-mail addresses: torkzadeh.submission@gmail.com, p torkzadeh@ee.sharif.edu
(P. Torkzadeh).
1434-8411/$ see front matter 2010 Elsevier GmbH. All rights reserved.
doi:10.1016/j.aeue.2010.07.001

almost rectangular-shaped cross-coupled differential pair output

signal which effectively maximizes the slope of oscillating signal at
zero crossing points. The most usual and conventional methods to
improve phase noise is increasing power consumption and changing transistors parameters in usual architectures while remaining
in current-limited regime and by switching current source transistor resulting on shifting the generated icker noise toward upper
frequencies and decreasing phase noise [14]. According to previous explanations, in this paper, phase-noise improvement has
been achieved by using rectangular-shaped oscillating signal which
increases signal slope at zero crossing points and decreasing signal
slope at signal extreme points (zeniths). On the other hand, by using
a shortening tank on second harmonic, down converted icker
noise will be eliminated resulting in less phase noise amount. In [5],
the same technique without any analytical models has been published and the most possible phase-noise improvement has been
obtained. In that article, no analysis for any mismatch between frequency and amplitude of fundamental and third harmonics have
been addressed which does not satisfy the general theory of using
third harmonic specially for process variations and corner processes case. On the other hand, in [5], output frequency does not

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459

have any tuning range and the oscillator has been designed and
optimized just for a single frequency. This paper is organized as
follows. Section 2 gives the phase noise minimization method and
explains the effect of any mismatch between fundamental and
third harmonic on phase-noise improvement. In this section, the
mean and standard deviation of phase-noise improvement for each
mismatch will be presented. Section 3 contains the analysis of
harmonic tuned LC Quadrature VCO, deriving closed-form expressions for phase noise generated by the most signicant white noise
sources. Section 4 illustrates the implemented QVCO architecture
and compares it with conventional congurations. Section 5 shows
the time and frequency domains simulations in spectreRF environment along with experimental measurements and nally Section 6
gives the conclusion.
2. Phase-noise minimization and mismatch effect on
improvement factor

Fig. 1. Transistors as noise sources in conventional VCO architecture.

2.1. Phase-noise minimization

In recent years, the theory and analysis for the physical processes of the phase noise in differential LC oscillators have made
signicant progress and various techniques to lower it have been
demonstrated [6,7]. The phase noise is mainly induced from various mixing phenomena of the negative switching differential
pair which one of main mixing phenomena is up- and downconversions from the thermal noise component at the base-band
and the harmonics of the oscillation frequency. In this condition,
each existing transistor in VCO architecture behaves as a noise
source and induces its thermal noise signal on output signal resulting in AM and PM modulations. The other source is up-conversion
from the transistors icker noise in base-band to the phase noise
in the fundamental frequency. There are many proposed theories
to analyze this phenomenon all discussed with the presumption of
stationary and time invariant system, resulting in a semi-predictive
phase-noise amount for output oscillating signal which are not adequate precise. The most precise theory and modeling for phase
noise and relation between interfering parameters is brought in [8],
in which system behavior (output signal) versus thermal and icker
noises is a Cyclo-Stationary linear time-variant system. According
to Hajimiris theory and his analysis, phase noise L(w)(dB) generated by thermal noise on specic frequency offset of w resulted
by one noise source will be


L(w)dB = 10 Log10

2
eff-rms
in2 /f
2
qmax 4w2


(1)

where qmax is the maximum charge on tank capacitor,  Eff-RMS is

root mean square of effective impulse sensitivity function (ISF) of
oscillator structure and in2 /f is thermal noise PSD amount. ISF(x)
is a dimensionless, frequency and amplitude-independent periodic
function with period 2 describing how much phase shift results
from applying a unit impulse at time (t). This function is dependent
to oscillating signal waveform or equivalently the shape of the limit
cycle which in turn is governed by the nonlinearity and the topology
of the oscillator and existing time of corresponding noise source.
Thus, this function can be shown as
eff (t) =  (t) (t)

(2)

where  (t) is just dependent on signal wave form and (t) depends
on existing time of noise source. (t) is a dimension less function
which its magnitude is between 0 and 1 and illustrates the ON time
of each noise source versus oscillating signal. It is apparent that by
decreasing the ON time of each noise source or by phase shifting
the noise source time by 90 degree versus (t), the total effective

amount will be decreased resulting in less phase noise. In order to

calculate  (t) from main oscillating signal, Eq. (3) can be applied:
 (t) =

(v(t)/t)
2

((v(t)/t) + (2 v(t)/t 2 ) )

(3)

where v(x) is oscillator output signal. According to (3), it can be

seen that  (t) is always perpendicular to v(x) (means the existing phase difference of 90 degree) and by increasing the oscillating
signal slope at zero crossing points,  (t) magnitude and its RMS
amount will be decreased. Based on Eq. (3), in order to achieve the
least amount of  (t) RMS, oscillating wave form should be in square
wave form making  (t) be zero toward 2. As long as for a symmetric oscillating signal (for the most conventional oscillators)  (t) has
phase difference of 90 with oscillating signal. In this condition to
choose an appropriate (t), all of transistors (noise sources) should
be turned on in-phase with oscillating signal resulting in the least
amount of  Eff-RMS . Fig. 1 shows the noise sources in a conventional
LC coupled oscillator. In this gure, each transistor has been dened
as thermal and icker noise source corrupting the output phase in a
random process and behavior. According to this gure, by switching
each noise source, its existing time is diminished and in the case
which the corresponding switching is performed in proper time,
(in-phase with oscillating signal) phase noise will be the least possible amount. As long as cross-coupled n-mos and p-mos transistors
are turning on in-phase with output signal, these transistors are not
required to be by-passed by extra switches. In contrary, current
source transistor which is always ON should be switched in proper
timing versus output signal. In quadrature VCOs (QVCO), coupling
section transistors derived by quadrature section are turning on
in 90 phase difference with output signal which can increase the
phase noise as much as possible. Thus, coupling transistors current
should be selected at least resulting in the least thermal and icker
noise PSD. Selecting coupling transistors current as low as possible, 90 degree phase difference between in-phase and quadrature
signals is corrupted. Therefore, there is a trade-off between output
phase noise and phase precision between two existing sub-cores.
As long as  (t) is periodic signal, it can be expanded to its Fourier
series which is
c0 
cn Cos(nt + n )
+
2

 (t) =

(4)

n=1

In this condition, phase noise generated by icker noise from each

noise source will be

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M. Atarodi et al. / Int. J. Electron. Commun. (AE) 65 (2011) 458467


L(w)dB = 10 Log10

c02 in2 /f w1/f

2
qmax 8w2 w

1
, c0 =


2
 (t)(t)
0

(5)
where w1/f is device icker noise corner frequency. According to
(5), the lower C0 , the less phase noise resulted by icker noise
will be. Setting output common-mode to VDD /2 in complementary
structure, the oscillating signal generates the same slope on rising
and falling edges resulting in symmetric  (t) and the least amount
of C0 . If in each half cycle of output signal, one of coupled n-mos
transistors and one of coupled p-mos transistor are ON, then (t)
will be symmetric. In order to make a square wave on output node,
extra tanks along with the following conditions on third and fth
harmonics should be used:
Oscillator should be able to oscillate on fundamental, third, and
higher order desired frequency bands.
Oscillating signal swing at each frequency harmonic should be
inversely proportional to its center frequency versus fundamental frequency.

RMS = 0
n

RMS = 0

In this condition, by calculating the  RMS and its derivations with

respect to n and A, optimum parameters will be


2

2

(1/2) ((An sin(n0 t) sin(0 t)/0 (1 + nA)2 ))
0


2

2

(1/2) ((An sin(n0 t) sin(0 t)/0 (1 + nA)2 ))
0

By using varactors on fundamental tank, third and higher tanks

should consist of corresponding varactor to change the higher
order harmonics center frequency related to fundamental center
frequency.

Using higher order harmonics (5th and 7th) in addition with the
third one in VCO structure makes the oscillator more complicated
and more sensitive to process and temperature variations. Applying
just the third harmonic and shaping output signal toward square
wave, signal slopes at both edges rises and  Eff-RMS will be 0.35
of traditional amount resulting in 9 dB phase-noise degradation.
Fig. 2 shows the output signal in traditional VCO (just fundamental)
and by using third harmonic tank and corresponding ISF for output
signal with fundamental frequency of 2.4 GHz. While process and
temperature variations besides the mismatch between capacitors
exist, varactors and spiral inductors are not zero and thus applying a
tank exactly on desired harmonic is impossible. Thus, it is preferable
to extract the frequency and amplitude mismatch effect on phase
noise for third harmonic. Assuming f0 as fundamental frequency
with normalized amplitude, VCO output signal will be

v(t) = cos(0 t) A cos(n0 t)

(6)

According to (3), the time dependence of  (t) is as follows:

 (t) =

An sin(n0 t) sin(0 t)
0 (1 + nA)2

0 = 2f0

Fig. 2. Traditional and third harmonic applied output signals and ISF.

(7)

=0n=3
(8)

= 0 A = 1/3

2.2. Mismatch between fundamental and third harmonic tanks

As long as all of lumped elements such as capacitors and
varactors have a limited precision and they are altered by process variation especially in corner cases, implementing an LC
tank on exact third harmonic center frequency (3f0 ) with signal swing of A/3 is impossible. In following, frequency and
amplitude deviation for a maximum of 20% mismatch error
and their effect on phase-noise improvement will be investigated.
Figs. 3 and 4 show the output signal for different third harmonic
frequencies and amplitudes and corresponding  RMS amount.
According to these gures, it can be seen that frequency and amplitude mismatch affect the output signal, ISF RMS amount, and
phase-noise improvement factor. Comparing these gures with
each other, amplitude mismatch exacerbates improvement factor much more than frequency mismatch. Third harmonic swing
depends on inductor and capacitor quality factors as well as transistors parameters. In order to extract the effect of amplitude and
frequency mismatch in complete analysis, a Monte-Carlo analysis for more than 106 points (1 million points) for mismatch
amount of 20% for both parameters has been performed. In this
condition, frequency and amplitude PDF (Probability Density Function) have been assumed to be in Gaussian form with standard
deviation of 20% of desired one. Table 1 shows the Monte-Carlo
simulation result for third harmonic frequency and amplitude deviation effect on phase-noise improvement. According to this table,
phase-noise improvement mean in worst condition is more than
8 dB.

M. Atarodi et al. / Int. J. Electron. Commun. (AE) 65 (2011) 458467

461

Fig. 5. Complementary LC QVCO.

Fig. 3. Third harmonic mismatch in amplitude and ISF RMS amount.

voltage at the node where it is calculated and this form for the
ISF explains the various phase-noise contributions in such oscillators. Fig. 5 shows the complementary LC QVCO composed of two
differential LC tank oscillators coupled to each other via two additional differential pairs. Quadrature oscillation is achieved by the
combination of direct-coupling and cross-coupling between two
differential oscillators (otherwise they will oscillate in-phase, acting as a single differential oscillator). An analysis of the phase noise
generated by both the switching and coupling transistors (to be
called hereafter as M1,2 and M3,4 ) might try to utilize what is already
known about the differential LC tank oscillator. After all, each half
of shown architecture contains two differential pairs that do not
interact with each other and can therefore be treated separately.
In the following, it is also assumed that the voltages at the transistor gates are quasi-square wave (by using fundamental and third
harmonic tanks). We start by dening the parameter KCoupling as
KCoupling =

Fig. 4. Third harmonic mismatch in frequency and ISF RMS amount.

3. Time-variant phase-noise analysis

Presuming last section discussions, coupled and coupling transistors noises are totally converted into phase noise, as is indeed the
case in differential oscillators. This can be performed by injecting
a small disturbance into an oscillator node (e.g., a current impulse
charging a tank capacitor) and then measuring the phase deviation of the perturbed waveform from a reference waveform. By
sweeping the instant when the disturbance is injected across a
whole oscillation period, it is possible to get quite an accurate
image of when the phase of the waveform is most sensitive to
noise. It is well known [8,12] that in a conventional differential
LC tank oscillator the ISF is sinusoidal and in quadrature with the

IB,Coupling

(9)

IB,Coupled

where IB,Coupling and IB,Coupled are coupling and coupled transistor

current sources, respectively. The parameter KCoupling is called coupling current co-efcient. Turning to shown architecture in Fig. 5,
Fig. 6 shows the normalized phase excess, caused by a small current
impulse injected into node I+, together with the relative node voltage (semi-square wave), for K = 1. While the phase excess is very
well approximated by corresponding ISF function, there is a substantial deviation from quadrature. In fact, the best curve t for the
data has a 47.5 phase shift from quadrature. A good approximation
of phase deviation from ideal quadrature undergone by the ISF is
[13]:
= arctan(KCoupling )

(10)

Therefore, the amount of phase shift for ISF function versus ideal
quadrature signal depends on coupling current co-efcient parameter KCoupling . According to (2), by deviating the ISF function phase
from ideal one, total  Eff-RMS will be increased and total phase noise
rises. Fig. 7 shows the effective ISF function for phase shifted signal
versus ideal one for K = 1. In this gure RMS signal is shown to be
1.7 times ideal one. Thus, increasing coupling current co-efcient
KCoupling results in more  Eff-RMS . Assuming the node voltages ver-

Table 1
Initial frequency and swing mismatch effect on phase-noise improvement amount.
Non-ideal effect

Center frequency
Swing
Both effects

Input parameters

Phase-noise improvement

Mean

Std

PDF

Mean (dB)

Std (dB)

PDF

7.5 Ghz
1/3
7.5 GHz, 1/3

15.5 GHz
0.067
1.5 GHz, 0.057

Gaussian
Gaussian
Gaussian

8.2
8.9
8

1.6
0.91
1.9

N/A
Gaussion
Quasi Gaussian

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M. Atarodi et al. / Int. J. Electron. Commun. (AE) 65 (2011) 458467

3.1. Tanks losses

We start by considering the simple case of the noise generated
by the tank losses, whose stationary white noise current is given
by the well-known expression of
iR2 = 4KB T

1
4KB T
f =
f
RP
Q0 L

(14)

where KB is Boltzmanns constant, T is the absolute temperature,

RP the equivalent parallel tank resistance accounting for all tank
losses, Q tank quality factor, L tank inductance amount and w0 is
angular frequency. The parameter  R is, by denition, the same as
in (12); therefore, the square RMS value of  iR is

2
iR,Eff,RMS
=

2
I+
( )d =

(15)

16N 2 Cos2 ( )

Using (1), (14) and (15) and making use of the relation qmax = CA,
one can write:
Fig. 6. Phase shifted ISF signal for semi-square wave signal.

LiR

2
iR,Eff,RMS
iR2 /f

4q2max w2

sus phase are in the form of:

VI+ () = VI () = A Sin() A/3 Sin(3)

(11)

VQ + () = VQ () = A Cos() + A/3 Cos(3)

Cos( + ) Cos(3 + )

I+ () = I () =
4N Cos( )

Q + () = Q () = Sin( + ) Sin(3 + )

L(w)dB = 10 Log10

PL,iR + PL,I+ + PL,Q

|A Sin() 1/3 Sin(3)|ICoupled RP d



(17)

20ICoupled Q0 L
9

and

where N(=4) is the number of LC tanks in VCO and the angle

0 2 is used instead of (1 t) for simplicity. 1 t is the angular
fundamental frequency of oscillating signal. According to (12), by
decreasing (K), ISF denominator rises and phase shift from ideal ISF
function is decreased and results in better phase-noise condition.
Due to the symmetry of the quadrature oscillator, we focus on I+
part of it, all results being transferable to Q+ part via a 90 phase shift.
In fact, it is sufcient to calculate the phase-noise contribution of
just one-half of I+ part, again because of symmetry. Therefore, we
will concentrate on what occurs at node I+ (Fig. 5), using (1) and
(2), the total phase noise can thereafter be calculated as [12]:

Replacing oscillation amplitude by

(12)

4N Cos( )

16N 2 C 2 A2 Q0 L Cos2 ( )w2

1
A =
2

Then, the approximated expressions for ISF functions will be

(16)

KB T



5A2 /9

1
1
2
=
= 1 + KCoupling
cos2 ( )
cos2 (Arctan(KCoupling ))

(18)

Thus, output phase noise generated by tank loss will be

LiR (dB)|N=4 = 10 Log10

2
2 KB T (1 + KCoupling
)

2
1264C 2 ICoupled
(Q0 L)3 w2

(19)

Thus, according to above equation, phase noise generated by tank

resistance is proportional with:

2
)
LiR (1 + KCoupling
 1 
LiR

(20)

Q3

(13)

where N is the number of LC tanks in VCO, PL,X is the phase noise that
produces the noise power and 5A2 /9 is each node power amount.
According to Eq. (13), each tank resistance and one of coupled and
coupling transistors thermal noise effect on output phase noise will
be considered.

Thus, by increasing tank quality factor, phase noise generated by its

noise will be degraded considerably. On the other hand, coupling
current co-efcient plays an important role in the total phase noise.
3.2. Coupled transistors
In this sub-section coupled transistor thermal noise effect on
output phase noise is considered. As previously mentioned, switching pair (coupled) and coupling pair are independent of each other,
thus, they can be studied separately. Calling iI+ and iI the currents in the switching pair (see Fig. 5) and neglecting all parasitic
components at the common source, one can obtain:
iI ( ) + iI+ ( ) = ICoupled

(21)

Using Eqs. (12) and (21), coupled transistors current as a function

of corresponding phase ( ) will be

Fig. 7. Effective actual ISF signal versus ideal function.

iI+ ( ) = Coupled A2 ( 2 Sin2 (Coupled ) S()2 + S())

2


Coupled
iI ( ) =
A2 ( 2 Sin2 (Coupled ) S()2 S())
2

(22)

M. Atarodi et al. / Int. J. Electron. Commun. (AE) 65 (2011) 458467

where

hI (0, Coupled ) =

(23)

Coupled = Arc sin

2Coupled A2

in Eq. (23), Coupled =

n Cox WCoupled /LCoupled where
n and Cox
are electron mobility and gate oxide capacitance per unit area,
respectively. WCoupled and LCoupled are width and length of coupled
transistors too. Coupled has been dened to specify the differential pair working in saturation region, otherwise one of them in
turned off. Using Eq. (22), one can calculate coupled transistors
trans-conductance values to be

gmI+ ( ) = Coupled A( 2Sin2 (Coupled ) S( )2 + S( ))



gmI ( ) = Coupled A( 2Sin2 (Coupled ) S( )2 S( ))

(25)

Considering (25), thermal noise power generated by in,I+ will be

2
in,I+

= 4KB TgmI+ f = 4KB TCoupled A

2Sin2 (Coupled ) S()2 + S())

(26)

2

= in,I+ 2 ()
where
2

i n,I+ = 4KB TCoupled Af



() =

(27)
2Sin2 (Coupled ) S()2 + S()

From (2), (25) and (26) effective ISF of inI+ will be drawn as
iI+,Eff ()

Cos( + ) Cos(3 +
4N Cos( )

2gmI+ ( )
gmI+ ( ) + gmI ( )



(28)

2Sin2 (Coupled ) S()2 + S()

By a few simplications and mathematical manipulations,

2
iI+,Eff-RMS
can be written as
2
iI+,Eff-RMS

1
=
2


2
iI+,Eff
()d

1
8N 2

Cos2 ( )

hI ( , Coupled )

), hI ( , Coupled )

) = Cos()Cos( ) Sin()Sin( )

Cos(3 +

) = Cos(3)Cos( ) Sin(3)Sin( )

hI ( , Coupled ) = 2Cos ( )

(32)

ICoupled

Coupled A2

Applying (1), (26), (29) and (32), the nal phase noise generated by
switching (coupled) transistors will be


LiI+ (dB)

N=4

= 10 Log10

2
2
iI+,Eff-RMS
in,I+
/f

4q2max w2


= 10 Log10

2 KB T

 (33)

2
(Q0 L)3 w2
702C 2 ICoupled

Eq. (31) shows that the output phase noise generated by coupled
transistors (switching transistors) thermal noise is independent of
coupling current co-efcient (K) and is inversely proportional to
tank quality factor. It is interesting to note that generated phase
noise by switching transistors does not depend on transistor sizes
(Coupled ).
3.3. Coupling transistors
Referring to Fig. 5, it is apparent that one can repeat the whole
analyses of the previous section for the coupling pair as well, provided that all equations for transistor currents, trans-conductances
and noise are time shifted by T/4 (i.e., phase shifted by 90 degree)
and coupled transistors current ICoupled is substituted with ICoupling .
The only equation that should not be phase shifted is I+ ( ) in (25),
as I+ ( ) depends on output voltage signal and it is independent
and same for all noise sources owing into node I+. However, each
transistor equation and its relative derivations are not interested to
2
be calculated again. The main purpose is obtaining the iQ
,Eff-RMS
parameter for achieving the nal phase noise generated by cou2
pling pair thermal noise. The simplest way to calculate iQ
,Eff-RMS
is just shifting the phase of  I+ ( )  I+ ( + /2) and using other
achieved equations in previous section. In this condition each coupling transistor trans-conductance will be

gmQ ( ) = Coupling A( 2Sin2 (Coupling ) S( )2 + S( ))



gmQ + ( ) = Coupling A( 2Sin2 (Coupling ) S( )2 S( ))

(34)

WCoupling

Coupling =
n Cox LCoupling





ICoupling
KCoupling ICoupled
1
Coupling = Sin1
= Sin

(35)

2Coupling A2

Using Eq. (25) for coupling pair we have:


=

(Cos( +

) Cos(3 +

))

iQ + () = I+

) and Cos(3 +

2Coupling A2

where
hI ( , Coupled )

(31)

where

(29)

Cos( +

(24)

Using result demonstrated in [14], ISF function of iI+ versus output

nodes will be
2gmI+ ()
gmI+ () + gmI ()

ICoupled
Coupled A2

By extending the factors Cos( +

can be achieved as

S() = Sin() 1/3 Sin(3)

iI () = I+ ()

= 0), hI (0, Coupled ) will be

Using the initial condition (

WCoupled

Coupled =
n Cox

LCoupled

ICoupled

463

2Sin2 (Coupled ) S()2 S()

2Sin2 (Coupled ) S()2
2

[Sin (Coupled ) S() ]d

(30)

2gmQ ( )
+
2 gmQ ( ) + gmQ + ( )

(36)

2
Repeating the same sequence to achieve iQ
as performed
Eff-RMS
in previous sub-section, we have:
2
iQ,Eff-RMS
=

3
ICoupled
KCoupling

4N 2 A2 Coupling

(37)

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M. Atarodi et al. / Int. J. Electron. Commun. (AE) 65 (2011) 458467

Fig. 9. Proposed and implemented complementary LC QVCO.

Fig. 8. Coupling current co-efcient effect on phase-noise degradation.


LiQ (dB)


N=4

= 10 Log10

4q2max w2


= 10 Log10

2
iQ
i2
/f
,Eff-RMS n,Q

3
2 KCoupling
KB T

 (38)

2
702C 2 ICoupled
(Q0 L)3 w2

It is noteworthy that, LiQ does not depend on Coupling as LiI+

did not depend on Coupled . On the other hand LiQ is very strong
function of KCoupling , while LiI+ is independent of it. In this condition, dependency of phase noise generated by tank loss, coupled
and coupling transistors versus coupling current co-efcient will
be
2
3
) :  : KCoupling

LiR : LiI+ : LiQ = (1 + KCoupling

(39)

Fig. 8 shows coupling current co-efcient effect on coupling transistors and tank resistor phase-noise degradation. According to (13),
having all of phase noise equivalent power of tank resistor, coupled
and coupling transistors, one can calculate the VCO total output
phase noise.

Fig. 10. In-phase sub-core output signals versus Vs.

zero crossing points [9]. Fig. 10 depicts Vs versus output signals. As

long as existing delay between current transistors gate node and
Vs is frequency independent, by tuning the frequency, phase difference between output signals and Vs node is altered and in the
worst condition, it will be
T =

1
2.4 GHz

 

1
2.5 GHz

= 16.7ps  = 15 deg

(40)

4. VCO architecture and circuit design

Applying (2) and (3), the calculated 15 degree phase difference

results in 0.2 dB phase-noise increment.

4.1. VCO core

4.2. VCO tanks

In order to generate the quadrature signal for QPSK applications,

coupled LC oscillator has been implemented and for decreasing the icker noise produced by coupled transistors, symmetric
complementary architecture with switched n-mos current source
transistors at bottom has been used as shown in Fig. 9. According
to this gure, QVCO core consists of two separate complementary
VCOs coupled to each other by coupling section formed by two nmos transistors (M1 and M2 ). As can be observed, each VCO sub-core
has p-mos and n-mos coupled transistors making the architecture symmetric and decrease the impact of icker noise on output
phase noise. On the other hand, negative resistance seen by output node will be greater compensating the energy loss in LC tank
and makes oscillation condition easier with less necessary current.
According to this gure, each sub-core and coupling section has
its own separated current source blocks controlled by quadrature
each sub-core output nodes. By controlling current source transistors with quadrature sub-core signals, Vs (dened in Fig. 9) will be
in-phase with output signals resulting in least phase distortion at

The architecture of this block has been illustrated in Fig. 11.

According to this gure, tank architecture should be symmetric to
affect the same capacitance load on output nodes. On third harmonic tuned tanks, varactor blocks can be used optional to reduce
mismatch between third and fundamental harmonics. External sec-

Fig. 11. LC tank architecture.

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465

Fig. 13. VCO output in-phase and quadrature signals.

Fig. 12. Microphotograph of fabricated HT VCO.

ond harmonic tank in serial form has been applied to alleviate

the second harmonic spurs generated by Vs node to improve output phase noise. Flicker noise from current source blocks can be
injected to output nodes and exacerbate phase-noise amount. This
phenomenon can be compensated by applying second harmonic
tuned tank in serial form. As long as each sub-core signal can oscillate in fundamental harmonic easier than third one, by choosing
main harmonic swing amount as 1.5 V for supply voltage of 1.8 V,
third harmonic swing amount will be 0.5 V accordingly. Applied
spiral inductors in third harmonic tank with ordinary quality factor
(Q = 7) are so tuned resulting in oscillating signal in 7.5 GHz center
frequency with its appropriate signal level. In addition, VCO total
current is tuned resulting in minimum power consumption with
proper swing for both harmonics. For fundamental tank, L1 , C1 and
CVar-1 should be calculated to obtain in 200 MHz tuning range and
swing of 1.5 V. Hence, it will be

C1 + CVar1Max
CVar1 = CVar1Min foutput = 2.6 GHz
= 1.17

CVar1 = CVar1Max foutput = 2.4 GHz

C1 + CVar1Min

(41)

C1 + CVar1 + CVar1 /2
= 1.17 (C1 + CVar1 )
C1 + CVar1 CVar1 /2
= 6.9 CVar1

Fig. 14. Fundamental harmonic and HT VCO phase noise.

the more phase noise will be generated. By choosing coupling coefcient as 0.2, phase precision of 1 degree is resulted. According to
Fig. 13, output differential signal swing is more than 2 V Peak-ToPeak which is appropriate for output buffers. In order to obtain the
third harmonic swing level equal to 1/3 of fundamental harmonic,
coupled and coupling n-mos transistors sizes have been chosen by
minimum possible amount resulting in VCO oscillating in third harmonic with appropriate swing level and producing lowest value
of thermal noise power spectral density and power consumption.
Fig. 12 illustrates the microphotograph of fabricated HT VCO. In
this gure, fundamental and third harmonic spirals inductors with

(42)

Having each varactor maximum tuning range (CVar-1 ) applied as

AMOS varactor, one can calculate the extra capacitor versus CVar-1
and its initial amount. Extra capacitors have been implemented
using Metal-Insulator-Metal (MIM) capacitors (Fig. 12).
5. Simulation and measurement results
Proposed QVCO was fabricated by 0.l8 um 1P6M CMOS technology in ADS environment. A supply voltage of 1.8 V was employed
resulting in QVCO tuning voltage in the range of 0.41.4 V. Fig. 13
shows the main output signal which is a square wave form signal
with frequency and amplitude matching of 94% and 92%, respectively resulting in 1 degree phase shifting from ideal one. Based
on previous explanations, the more coupling section current, the
more phase precision between in-phase and quadrature signals and

Fig. 15. Current drawn by each VCO sub-core.

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M. Atarodi et al. / Int. J. Electron. Commun. (AE) 65 (2011) 458467

Table 2
Performance comparison between proposed and previous works.
Design

Process

Hsia [7]
Perraud [10]
Kim [5]
Adreant [11]
This work

0.18 um CMOS
0.18 um CMOS
0.35 um CMOS
0.35 um CMOS
0.18 um CMOS

Phase noise

Frequency
range (GHz)

139 dBc/Hz at 3 MHz

96 dBc/Hz at 100 MHz
135 dBc/Hz at 1 MHz
139 dBc/Hz at 3 MHz
136 dBc/Hz at 3 MHz

0.892.5
8.510.73
0.81.1
0.91.2
2.42.6

other implemented blocks are dened. It can be seen that fundamental inductor has 3.25 turns while third harmonic working in
7.5 GHz frequency has 1.25 turns. Having selected appropriate transistors sizes resulting in minimum power consumption, achieved
phase noise in output frequency of 2.5 GHz in frequency offsets
of 1 MHz and 3 MHz for simulated and measured VCO are 129.5,
139, 125 and 136 dBc/Hz, respectively. Fig. 14 illustrates both
simulated and measured VCO output phase noise in corresponding
frequency offsets in both conditions of using just fundamental tank
and harmonic tuned tank. According to this gure, by using third
harmonic tank and adjusting its parameters resulting in appropriate oscillating frequency and by steering coupling and coupled
current source transistors with quadrature signals, phase noise has
been reduced as high as 9 dB in ideal condition and 6 dB for measured VCO. Fig. 15 shows the drawn current by each VCO sub-core
from supply voltage of 1.8 V. According to this gure, the average
of current drawn by each VCO sub-core is 1.95 mA resulting in total
power consumption of 7 mW which is much lower compared to
the published VCOs with equal achieved phase noise. As dened in
[10], the gure-of-merit (FOM) of a VCO is
FOM(dB) = L(Offset) + 10Log

 P 
DC
1 mW

20Log

 f

Osc
fOffset

(43)

The achieved FOM for fabricated QVCO at offset frequency of 3 MHz

is 186 dB at 2.5 GHz. Table 2 shows the comparison results of the
proposed and recently published VCOs. From this table, proposed
QVCO demonstrates an excellent performance to realize multiband applications at low power consumption.

6. Conclusion
In this article, a low power, low phase noise LC Quadrature
VCO operating at a 1.8 V supply for ISM band applications using
0.18um CMOS technology has been demonstrated. The architecture of proposed QVCO using third harmonic on VCO tank and
steering coupling and coupled section current sources by quadrature signals has resulted in the lowest value of power consumption
and output phase noise. Shaping the output signal toward square
wave, increases signal slope at zero crossing points and results in
less ISF RMS amount. A comprehensive analysis for frequency and
amplitude deviations as high as 20% for third harmonic and its
effect on output phase-noise improvement was discussed and it
was indicated that at worst case (most possible mismatch) phasenoise improvement corrupts by 2 dB. In addition, an extensive
analysis on time-variant theory of phase noise was performed. General closed-form formulas have been derived for the phase noise
caused by LC tanks losses and noisy currents in the MOS transistors. Designed harmonic tuned (HT) LC Quadrature VCO was
implemented using 0.18 um 1P6M CMOS technology operating at
1.8 V for frequency band of 2.42.6 GHz with achieved phase noise
of 136 dBc/Hz at frequency offset of 3 MHz. Total current drawn
by VCO is 3.9 mA resultinga low power consumption of 7 mW. Fab-

Power
(mW)
31
14
15
12
7

DOM (dB)
178
183
183
185.3
186

ricated HT VCO gure-of-merit (FOM) is obtained to be 186 dB,

making the implemented VCO superior compared to the previously
published VCOs.

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Mojtaba Atarodi received his Ph.D. degree from the University of Southern California (USC) on the subject of
analog IC design in 1993. He received the M.Sc. degree
in electrical engineering from the University of California,
Irvine, in 1987 and B.S.E.E. from Amir Kabir University of
Technology (Tehran Polytechnic) in 1985.
From 1993 to 1996 he worked with Linear Technology
Corporation as a senior analog design engineer and produced 2 IC product in the eld of high frequency high
dynamic range continuous-time Gm-C lters. Since then,
he has been consulting with different IC companies. He
is currently an Associate professor at Sharif University
of Technology. He has published more than 80 technical
journal and conference papers in the area of analog/RF and mixed-signal integrated
circuit design. He is the author of a book in Analog CMOS IC Design. He has managed
several IC design projects and come up with 5 IC Products, namely: a SIMCARD IC, a
Smartcard IC, a PCM CODEC etc.
He holds one US patent. His main research interests are integrated bioelectronics,
RF/analog/mixed-signal ICs, and integrated circuits for digital TV receivers.

M. Atarodi et al. / Int. J. Electron. Commun. (AE) 65 (2011) 458467

Pooya Torkzadeh was born in Isfahan, in 1980. He

received the B.Sc. degree from Isfahan University of Technology (IUT), Iran, in 2002 and the M.Sc. degree from
the Sharif University of Technology (SUT), Iran, in 2004
both in electrical engineering. He is currently pursuing the Ph.D. degree at Sharif University of Technology
in the eld of analogue integrated circuits designing
and developing. In 2005 he joint to Sharif Integrated
Circuit And System Group (SICAS) working on continuous/discrete time sigma-delta modulators with low
power consumption for low power appliances. He has
received many patents in the eld of sigma-delta modulator designing and optimizing. He is the author and
coauthor of more than 15 international journal and conference publications on analog integrated circuits. His research interests include ADC signal converters, low
power phase locked loops (PLLs) with low phase noise amount for broad-band
appliances.

467

Baktash Behmanesh was born in Borujerd, Iran, in 1984.

He received the B.Sc. and M.Sc. degrees in electrical and
electronics engineering from the Sharif University of Technology (SUT), Tehran, Iran, in 2006, and 2008, respectively.
He is currently pursuing his Ph.D. in electronics engineering at SUT. From 2008, he is an Analog/Mixed-Signal
Integrated Circuit Designer with the Sharif Integrated
Circuits and Systems (SICAS) group at EE Department
of SUT. His research interests include analog/RF circuits
for wireless communications and low noise applications,
data converters, and mixed-signal circuits for biomedical
applications.