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EE-234
Technical notes on using Analog Devices DSPs, processors and development tools
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Introduction
This EE-Note describes how to interface
Blackfin processors to standard T1 or E1
encoded signals. The proposed template assumes
that a Blackfin processor is functionally located
between two T1/E1 streams to perform the
required processing, such as line echo canceling.
However, the Blackfin processor can be adapted
easily to other functional architectures. As shown
in this EE-Note, most standard backplane PCM
data streams interface directly to the processors
serial port(s), without any external hardware.
This document provides schematics, layout
suggestions, and a software framework for
receiving, processing, and transmitting PCM
streams between two T1/E1 transceivers/
framers.
The chosen framing device is the PMC-Sierra
PM4351 COMET. The PCM streams are
connected to one of the processors synchronous
serial ports (SPORTs), which can handle two
input streams and two output streams. The
COMET is configured via the processors
asynchronous memory interface in the external
bus interface unit (EBIU).
The schematics are intended to be for a daughterboard that plugs into an EZ-KIT Lite
evaluation system available from Analog
Devices, Inc.
The application was implemented on and is
described herein for the ADSP-BF533 processor
System Architecture
Figure 1 shows a block diagram of a typical
application. The board is designed to plug into an
existing T1/E1 connection via two RJ48C
connectors. This leads to two streams (stream 1
and stream 2), both carrying incoming and
outgoing data (RIN, ROUT, SIN, and SOUT). In the
most basic mode of operation (pass-through),
RIN and SIN are copied unaltered to ROUT and
SOUT, respectively, such that the whole resembles
the original single T1/E1 connection.
Copyright 2004, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application of
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of their respective holders. Information furnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable, however
no responsibility is assumed by Analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices Engineer-to-Engineer Notes.
a
T1/E1 Interface Board
T1/E1 Stream 1
T1/E1 Stream 2
Rout
Rin
Framing and
processing
Sout
Sin
RS232 to Host
Interfacing T1/E1 Transceivers/Framers to Blackfin Processors via the Serial Port (EE-234)
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Sout
CLK
2.048MHz
RS232
Protection
Line Interface
Protection
&
&
UART
DSP
Isolation
Isolation
EZ-KIT Lite
via
Expansion
Connectors
COMET1
RJ48C
Line Interface
RJ48C
Rin
Rout
Sin
COMET2
EBIU
SPORT
PM4351
PM4351
PCM data streams
Interfacing T1/E1 Transceivers/Framers to Blackfin Processors via the Serial Port (EE-234)
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a
RIN[Number_of_channels-1], SIN[Number_of_channels-1]
for frame 0, and similarly for the other frames.
Note that the two receive lines (RIN and SIN) are
re-organized as they come in to the SPORT
without any intervention of the core. The attached
code
example
acquires
a
block
of
Number_of_Samples frames, set by default to 40,
such
that
an
interrupt
occurs
every
(Number_of_Samples * 125) s (5 ms for the
provided example). The interrupt signals that the
acquired frames are available for processing, but
the DMA continues to acquire new frames in a
different memory area. When this second block is
acquired, another interrupt is generated and the
DMA places new frames into the first memory
area, overwriting the ones already there. This
mechanism is sometimes referred to as double
buffering and allows the Blackfin processor to
process half the incoming data (the first
Interfacing T1/E1 Transceivers/Framers to Blackfin Processors via the Serial Port (EE-234)
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a
Ordering represents
increasing 16-bit
word addresses
Frame
[0]
Frame
[1]
Rin[0]
Sin[0]
Rin[0]
Sin[0]
Rin[1]
Sin[1]
Rin[1]
Sin[1]
...
...
...
...
Rin[Number_of_channels-1]
Sin[Number_of_channels-1]
Rin[Number_of_channels-1]
Sin[Number_of_channels-1]
Rin[0]
Sin[0]
Rin[0]
Sin[0]
Rin[1]
Sin[1]
Rin[1]
Sin[1]
...
...
...
...
Rin[Number_of_channels-1]
Sin[Number_of_channels-1]
Rin[Number_of_channels-1]
Sin[Number_of_channels-1]
...
...
...
...
...
...
...
...
...
...
...
...
Rin[0]
Sin[0]
Rin[0]
Sin[0]
Sin[1]
Rin[1]
Sin[1]
...
...
...
...
Rin[Number_of_channels-1]
Sin[Number_of_channels-1]
Rin[Number_of_channels-1]
Sin[Number_of_channels-1]
Frame
Rin[1]
[Number_of_Samples-1]
Repeat from
beginning
1st Half
2nd Half
Figure 4. PCM samples allocation in L1 Data Memory see text on how 2D-DMA fills the buffers
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a
forced to synchronize all four PCM streams. They
come from, and go to, the SPORTs primary and
secondary transmitter, and primary and secondary
receiver, respectively.
Software Framework
Figure 5 shows a high-level flowchart of the
provided framework. Because the code is modular
and well commented, this EE-Note provides only
a brief outline. More importantly, this section
gives an overview on the possible operating
modes and options that are implemented.
After the initialization of the hardware (Blackfin
processors PLL, SDRAM, asynchronous memory
controllers, SPORT, DMA and exception handler;
COMET devices; and the UART interface), the
main loop performs three basic tasks:
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a
compile time. All of them are controlled by
(un)commenting or assigning values to #define
clauses in one file system.h. The most important
ones are:
!
COMPANDING_LAW
(available
only
if
hardware companding is selected): sets the
SPORTs companding law
or
initializeCOMET_E1_75()
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a
Main()
ProcessData()
No
Copy SIN to SOUT
(Number_of_Samples *
Number_of_channels)
words
Start Transfers
Process Loop
(Infinite)
Voice
Channel?
Message from
Host?
Yes
Yes
Semaphore:
new Block of
Samples?
Semaphore is set by
DMA interrupt every
Number_of_samples * 125usec
Sout() =
Algorithm(Rin,
Sin)
Copy expanded
Sin to Sout
(Number_of_Samples *
Number_of_channels)
words
Yes
Clear Semaphore
ProcessData()
Compress Sout
with a-law or u-law
return
End Process Loop
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a
Memory Allocation Data Cache
The software framework has been structured
knowing that most algorithms will work with
relatively small amounts of code but operate on
large amounts of data. Therefore, the code is
assumed to be small enough to fit into L1
instruction memory thus, executing at the
processors core clock frequency. The software
framework enables data caching for eventual large
data buffers in external SDRAM. This is simply
done by the initial definition of the int __cplb_ctrl
control variable in main.c. The data cache
organization is done in the cplbtab533.s file and
excludes external asynchronous memory from
being cached (such that there are no caching
effects on the COMETs configuration and status
registers).
The data buffers for the incoming and outgoing
PCM data streams are placed into (non-cached)
L1 memory since they are modified by DMA
transfers, which are independent of the cache
system.
In conclusion, the framework places instructions
and all necessary data into non-cacheable L1
memory and sets up the upper half of L1 Data
Bank A as cache buffer for data placed in
SDRAM. This approach has been tested on a line
Command Syntax
Purpose
READ_MEM_8 <addr>
READ_MEM_16 <addr>
READ_MEM_32 <addr>
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a
Both tools take a configuration file as input and
produce C code. Lex produces a scanner that
tokenizes incoming strings, and Yacc produces a
program that parses lists of tokens to identify
meaningful patterns (i.e., valid commands). The
Lex/Yacc suite allows for automatic filtering of
incoming strings that do not have commands
associated with them. For general information on
Lex and Yacc, refer to [8].
[yacc_gmr.txt]
...
%token INTEGER
%token COMET_READ_REG
...
COMET_READ_REG INTEGER INTEGER
{
size = sprintf(str,
"COMET_READ_REG 0x%x 0x%x;\n\r", $2, $3);
YY_OUTPUT(str, size);
// echo the command to acknowledge
temp = COMET_readReg($2, $3);
// pass the parameters to a function that
// actually does the COMET access
where
<base addr> is the base address of the COMET
size = sprintf(str,
"COMET_READ_REG (0x%x, 0x%x) -> 0x%x;\n\r",
$2, $3, temp);
YY_OUTPUT(str, size);
// echo the output
and
<reg addr> is the address of the MMR in the
COMET memory space
Lex Configuration File
[lex_spec.txt]
...
COMET_READ_REG {
return COMET_READ_REG;
// string COMET_READ_REG
returns a distinct token
}
{integer}
yylval = atoi(yytext);
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Results
Figure 6 shows a screenshot of the implemented
UART interface protocol. Shown are the initial
status message with the addresses of control
variables and two write_mem commands.
Figure 7 shows a graphical visualization of the
output data in pass-through mode. Inputs are
generated externally (1 kHz sine waves) on a
subset of the 24 T1 channels. ROUT is looped back
externally to SIN, such that all four streams contain
the same data, only delayed in time.
Figure 8 shows an example of how the debugging
flag pins (PF1 and PF3) can be used to show, for
instance, the execution time for the processing of
all channels, or any other useful time in a
relatively straightforward way. The example was
taken from an application where the algorithm
was a line echo canceller (128 ms tail length).
Each of the 32 channels is processed, although
channels 24-31 are not used by a T1 connection.
Conclusions
This EE-Note, along with schematic drawings and
software framework provides design ideas for a
variety of T1/E1 communication lines.
The main focus is to interface the Blackfin
processors serial ports to standard backplane
formats and to show how to process the PCM
data. This is demonstrated on PCM streams from a
framer device such as the PM4351.
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Figure 7. ROUT and SOUT (channel 0) in pass-through mode (RIN is a 1kHz sine-wave for channels 0,1 and 2),
SIN is looped back externally from ROUT.
Figure 8. Execution time (signal PF1, trace 1) and individual channel convergence indicator (signal PF3, trace 4)
in the case of a line echo canceller algorithm. See RESULTS section for more details
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a
References
[1] ADSP-BF531/ADSP-BF532/ADSP-BF533 Blackfin Embedded Processor Data Sheet. Rev 0, March 2004.
Analog Devices, Inc.
[2] ADSP-BF533 Blackfin Processor Hardware Reference Manual. Revision 1.0, December 2003.
Analog Devices, Inc.
[3] ADSP-BF561 Blackfin Processor Hardware Reference Manual. Preliminary Revision 0.2, November 2003.
Analog Devices, Inc.
[4] PM4351 COMET Combined E1/T1 Transceiver Datasheet. Issue10, November 2000. PMC-Sierra, Inc.
[5] PM4351 COMET Combined E1/T1/J1 Transceiver/Framer Device Errata. Issue6, April 2002.
PMC-Sierra, Inc.
[6] PM4351 COMET Reference Design. Rev. 2.0, Issue1, November 1998. PMC-Sierra, Inc.
[7] PM4351 COMET Programmers Guide. Issue2, September 2000. PMC-Sierra, Inc.
[8] Lex and Yacc for Embedded Programmers. Embedded Systems Programming.
http://www.embedded.com/story/OEG20030220S0036
Document History
Revision
Description
Initial Release
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