Chapter 1: CMOS Transistor Theory

KIRAN KUMAR.V.G

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CMOS inverter

Figure-3.6: CMOS inverter

The most commonly used inverter circuit is CMOS inverter.
Advantages

No current flows either for logical 0 or logical 1 inputs.

Full logic 1 and logic 0 levels are present as outputs.VOH = VDD and VOL = 0V
For devices of similar dimensions p-channel is slower than n-channel.
Body effect is zero (ie; Substrate bias effects is zero)

Chapter 1: CMOS Transistor Theory

KIRAN KUMAR.V.G

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CMOS inverter Voltage transfer characteristics:while the substrate of the pMOS transistor is connected to the supply voltage VDD in order to reverse bias the source and drain
junctions. Since VSB = 0 for both devices there is no substrate bias effect for either device.
Figure-3.6: voltage transfer characteristic of CMOS inverter.
Region A: Vin = logic 0, p transistor is fully turned ON,
while the n transistor is fully turned OFF. No current flows
through inverter and output is directly connected to VDD
through p transistor. So logic 1 is the output.
Region B: The input voltage has increased to a level which
exceeds the threshold voltage of n transistor. The n transistor
conducts and has a large voltage between source and drain so
it is in saturation, the p transistor is also conducting but with
only a small voltage across it, it operates in the linear region.
A small current flows through the inverter from VDD to VSS.
Region C: In this region the inverter exhibits gain in which
both transistors are in saturation. Large current flows in
region C. Most of the energy consumption in switching from
one state to another is in this region.
Region D: In this region pMOS is in saturation and nMOS is
in linear operating regions. The current magnitude is small.
Region E: Vin = logic! The nMOS is fully turned ON, while pMOS is fully turned OFF, no current flows and a good logic 0 appears at
the output.

Chapter 1: CMOS Transistor Theory

KIRAN KUMAR.V.G

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Figure-3.7: IDS V/s Vin curve.

In region C the inverter exhibits gain in which both transistors are in saturation. The currents in each device must be the same.
IDSp = - IDSn
Where IDSn = n/2 (VGS Vtn)2, and
IDSp = p/2 (Vin VDD -Vtp)2
ie; p/2 (Vin VDD -Vtp)2 = - n/2 (VGS Vtn)2
-Vin + VDD +Vtp = (n/p) (Vin Vtn)
VDD +Vtp = Vin [1 + (n/p)] - Vtn(n/p)

Since both transistors are in saturation, they act as current sources so that the equvivalent circuit in this region is two current sources in
series between VDD and VSS with the putput voltage coming from their common point. The region is inherently unstable in
consequence and the change over from one logic level to the other is rapid.
Assuming | Vtp| = | Vtn| and n = p,

Vin = VDD/2
And n = p
p Wp/LP = n Wn/Ln
Since mobilities are unequal and taking Lp = Ln
p/ n = Wp/ Wn = 1/ 2.5
or Wp= 2.5 Wn.
Thus when Vin = VDD//2 , Wp= 2.5 Wn

Chapter 1: CMOS Transistor Theory

KIRAN KUMAR.V.G

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Latch up in CMOS circuits.

Latch up is a condition in which the parasitic components give rise to the establishment of low resistance conducting path between
VDD and VSS causing excessive damage and even permanent device damage with disastrous results careful control during
fabrication is necessary to avoid this problem. Latch up may be induced by glitches on the supply rails or by incident radiation.
The Figure 3.8 shows the mechanism which shows the key parasitic components associated with a p-well structures in which an
inverter circuit has been formed.

Figure 3.8. Latch-up in CMOS circuits.

There are in effect two transistors and two resistances which forms a path between VDD and VSS. If a sufficient substrate current flows to
generate enough voltage across RS to turn ON transistor T1 this will then draw current RP and if the voltage developed is sufficient, T2 will also
turn ON, establishing a self sustaining low resistance path between the supply rails. If the current gains of the two transistors are such that 1
2>1 latch up may occur. Figure 3.9 shows equivalent circuits with no injected current, the parasitic transistor will exhibit high resistance but
sufficient substrate current will flow will cause switching low resistance.

Chapter 1: CMOS Transistor Theory

KIRAN KUMAR.V.G

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Once latched up in this condition will be maintained until the latch up current drops below IL . This is essential for CMOS that VL and IL are not
readily achieved in normal mode of operation.

Figure 3.9. A 4-layer pnpn structure

How to avoid latch-up:

An increase in substrate doping level a consequent drop in value of RS.

Reducing RP by control of fabrication parameters and by ensuring a low contact resistance to VSS.
Other elaborate measures such as introduction of guard rings.
Use minimum area p-wells so that p-wells so that p-well photocurrent can be minimized during transient pulses.
Include an n-Well contact every time a pMOS is connected to the power supply VDD, and
Include a p-substrate contact every time an nMOS is connected to a ground rail.

Chapter 1: CMOS Transistor Theory

Figure 3.10. Layouts for avoiding latch-up.

KIRAN KUMAR.V.G1-1