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ML4803
8-Pin PFC and PWM Controller Combo
Features
General Description
Block Diagram
7
VEAO
7V
VCC
PFC OFF
COMP
17.5V
16.2V
35A
REF
+
VREF
VCC OVP
GND
COMP
M3
M4
M1
PFC
CONTROL
LOGIC
M2
R1
C1
30pF
PFC OUT
1
M7
LEADING
EDGE PFC
ONE PIN ERROR AMPLIFIER
3
ISENSE
VCC
OSCILLATOR
PFC 67kHz
PWM 134kHz
26k
DUTY CYCLE
LIMIT
PWM COMPARATOR
COMP
40k
1.2V
6
TRAILING
EDGE PWM
PFC/PWM UVLO
VREF
VDC
SOFT START
PFC ILIMIT
1V
COMP
ILIMIT
PWM
CONTROL
LOGIC
COMP
PWM OUT
8
M6
1.5V
DC ILIMIT
ML4803
PRODUCT SPECIFICATION
Pin Configuration
ML4803
8-Pin PDIP (P08)
8-Pin SOIC (S08)
PFC OUT
PWM OUT
GND
VCC
ISENSE
ILIMIT
VEAO
VDC
TOP VIEW
Pin Description
PIN
NAME
PFC OUT
FUNCTION
PFC driver output
GND
Ground
ISENSE
VEAO
VDC
ILIMIT
VCC
PWM OUT
Min
Max
Unit
40
mA
18.3
-5
GND 0.3
VCC + 0.3
ISENSE Voltage
Voltage on Any Other Pin
1.5
Junction Temperature
150
150
260
110
160
C/W
C/W
-65
Operating Conditions
Temperature Range
ML4803CX-X
0C to 70C
ML4803IX-X
-40C to 85C
PRODUCT SPECIFICATION
ML4803
Electrical Characteristics
Unless otherwise specified, VCC = 15V, TA = Operating Temperature Range (Note 1)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TA = 25C, VEAO = 6V
33.5
35.0
36.5
Line Regulation
0.1
0.3
16.3
16.8
TA = 0C to 70C
15.5
-0.9
Delay to Output
-1
-1.15
150
300
ns
1.5
1.6
150
300
ns
67
74
kHz
DC ILIMIT Comparator
Threshold Voltage
1.4
Delay to Output
Oscillator
Initial Accuracy
TA = 25C
Voltage Stability
62
Temperature Stability
Total Variation
60
67
74.5
kHz
Dead Time
PFC Only
0.3
0.45
0.65
90
95
PFC
Minimum Duty Cycle
0
8
15
IOUT = 100mA
0.8
1.5
0.7
1.5
15
%
%
Rise/Fall Time
CL = 1000pF
TA = 0C to 70C, ML4803-2
0-43
TA = 0C to 70C, ML4803-1
0-49.5
13.5
14.2
50
ns
PWM
0-47
8
0-50
0-50
15
IOUT = 100mA
0.8
1.5
0.7
1.5
15
Rise/Fall Time
CL = 1000pF
ICC = 10mA
Start-up Current
Operating Current
13.5
14.2
50
ns
Supply
16.7
17.5
18.3
VCC = 11V, CL = 0
0.2
0.4
mA
VCC = 15V, CL = 0
2.5
mA
11.5
12
12.5
2.4
2.9
3.4
Note:
1. Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
ML4803
Functional Description
The ML4803 consists of an average current mode boost
Power Factor Corrector (PFC) front end followed by a synchronized Pulse Width Modulation (PWM) controller. It is
distinguished from earlier combo controllers by its low pin
count, innovative input current shaping technique, and very
low start-up and operating currents. The PWM section is
dedicated to peak current mode operation. It uses conventional trailing-edge modulation, while the PFC uses leadingedge modulation. This patented Leading Edge/Trailing Edge
(LETE) modulation technique helps to minimize ripple current in the PFC DC buss capacitor.
The ML4803 is offered in two versions. The ML4803-1
operates both PFC and PWM sections at 67kHz, while the
ML4803-2 operates the PWM section at twice the frequency
(134kHz) of the PFC. This allows the use of smaller PWM
magnetics and output lter components, while minimizing
switching losses in the PFC stage.
In addition to power factor correction, several protection features have been built into the ML4803. These include soft
start, redundant PFC over-voltage protection, peak current
limiting, duty cycle limit, and under voltage lockout
(UVLO). See Figure 12 for a typical application.
ISENSE
This pin ties to a resistor or current sense transformer which
senses the PFC input current. This signal should be negative
with respect to the IC ground. It internally feeds the pulseby-pulse current limit comparator and the current sense feedback signal. The ILIMIT trip level is 1V. The ISENSE feedback is internally multiplied by a gain of four and compared
against the internal programmed ramp to set the PFC duty
cycle. The intersection of the boost inductor current
downslope with the internal programming ramp determines
the boost off-time.
VDC
This pin is typically tied to the feedback opto-collector. It is
tied to the internal 5V reference through a 26k resistor and
to GND through a 40k resistor.
ILIMIT
This pin is tied to the primary side PWM current sense resistor or transformer. It provides the internal pulse-by-pulse
current limit for the PWM stage (which occurs at 1.5V) and
the peak current mode feedback path for the current mode
4
PRODUCT SPECIFICATION
control of the PWM stage. The current ramp is offset internally by 1.2V and then compared against the opto feedback
voltage to set the PWM duty cycle.
VCC
VCC is the power input connection to the IC. The VCC startup current is 150A . The no-load ICC current is 2mA. VCC
quiescent current will include both the IC biasing currents
and the PFC and PWM output currents. Given the operating
frequency and the MOSFET gate charge (Qg), average
PFC and PWM output currents can be calculated as IOUT =
Qg x F. The average magnetizing current required for any
gate drive transformers must also be included. The VCC pin
is also assumed to be proportional to the PFC output voltage.
Internally it is tied to the VCCOVP comparator (16.2V)
providing redundant high-speed over-voltage protection
(OVP) of the PFC stage. VCC also ties internally to the
UVLO circuitry, enabling the IC at 12V and disabling it at
9.1V. VCC must be bypassed with a high quality ceramic
bypass capacitor placed as close as possible to the IC.
Good bypassing is critical to the proper operation of the
ML4803.
VCC is typically produced by an additional winding off the
boost inductor or PFC Choke, providing a voltage that is proportional to the PFC output voltage. Since the VCCOVP max
voltage is 16.2V, an internal shunt limits VCC overvoltage to
an acceptable value. An external clamp, such as shown in
Figure 1, is desirable but not necessary.
VCC
1N4148
1N4148
1N5246B
GND
VCC is internally clamped to 16.7V minimum, 18.3V maximum. This limits the maximum VCC that can be applied to
the IC while allowing a VCC which is high enough to trip the
VCCOVP. The max current through this zener is 10mA.
External series resistance is required in order to limit the
current through this Zener in the case where the VCC voltage
exceeds the zener clamp level.
REV. 1.1.3 8/3/01
PRODUCT SPECIFICATION
ML4803
GND
Leading/Trailing Modulation
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn ON right after the trailing edge of the system clock.
The error amplier output voltage is then compared with the
modulating ramp. When the modulating ramp reaches the
level of the error amplier output voltage, the switch will be
turned OFF. When the switch is ON, the inductor current will
ramp up. The effective duty cycle of the trailing edge modulation is determined during the ON time of the switch. Figure
2 shows a typical trailing edge control scheme.
SW2
L1
I2
I1
I3
I4
VIN
RL
SW1
DC
C1
RAMP
VEAO
REF
U3
+
EA
TIME
DFF
RAMP
OSC
U4
CLK
U1
R
Q
D U2
Q
CLK
VSW1
TIME
ML4803
PRODUCT SPECIFICATION
Typical Applications
CCOMP =
SW2
L1
I2
I1
(1)
CCOMP =
Pin
R p V BOOST VEAO COUT (2 f)
(2)
300W
11.3M 400V 0.5V 220F (2 30Hz)2
CCOMP = 16nF
I3
I4
VIN
RL
SW1
DC
C1
RAMP
VEAO
U3
+
EA
REF
RAMP
OSC
U4
CLK
VEAO
+
U1
TIME
DFF
CMP
R
Q
D U2
Q
CLK
VSW1
TIME
PRODUCT SPECIFICATION
ML4803
RCOMP =
CZERO =
RCOMP =
1
f
RCOMP
2
10
1
= 016
. F
CZERO =
6.28 3Hz 330k
60
VO
40
11.3M
20
RLOAD
667
330k
IVEAO
35A
15nF
GAIN (dB)
220F
VEAO +
ML4803
VEAO
IOUT
ML4803
20
0.15F
POWER
STAGE
Power Stage
Overall Gain
Compensation
Network Gain
COMPENSATION
40
60
0.1
10
1000
100
FREQUENCY (Hz)
50
Power Stage
Overall
Compensation
Network
FF @ 55C
TYP @ 55C
40
PHASE ()
50
100
150
TYP @ 155C
30
SS @ 155C
20
10
200
0.1
10
100
FREQUENCY (Hz)
1000
VEAO (V)
ML4803
PRODUCT SPECIFICATION
UVLO
PFC Start-Up and Soft Start
During steady state operation VEAO draws 35A. At start-up
the internal current mirror which sinks this current is defeated
until VCC reaches 12V. This forces the PFC error voltage to
VCC at the time that the IC is enabled. With leading edge
modulation VCC on the VEAO pin forces zero duty on the
PFC output. When selecting external compensation components and VCC supply circuits VEAO must not be prevented
from reaching 6V prior to VCC reaching 12V in the turn-on
sequence. This will guarantee that the PFC stage will enter
soft-start. Once VCC reaches 12V the 35A VEAO current
sink is enabled. VEAO compensation components are then
discharged by way of the 35A current sink until the steady
state operating point is reached. See Figure 8.
Once VCC reaches 12V both the PFC and PWM are enabled.
The UVLO threshold is 9.1V providing 2.9V of hysteresis.
Generating VCC
An internal clamp limits overvoltage to VCC. This clamp
circuit ensures that the VCC OVP circuitry of the ML4803
will function properly over tolerance and temperature while
protecting the part from voltage transients. This circuit
allows the ML4803 to deliver 15V nominal gate drive at
PWM OUT and PFC OUT, sufcient to drive low-cost
IGBTs.
It is important to limit the current through the Zener to avoid
overheating or destroying it. This can be done with a single
resistor in series with the VCC pin, returned to a bias supply
of typically 14V to 18V. The resistor value must be chosen
to meet the operating current requirement of the ML4803
itself (4.0mA max) plus the current required by the two gate
driver outputs.
10V/div.
VCC
C23
0.01F
0
10V/div.
VEAO
0
PFC
GATE
200V/div.
VBOOST
CR16
1N4148
C16
1F
R4
1k
R19
10k
ISENSE
10V/div.
VOUT
R28
20k
R29
20k
R3
0.15
3W
C5
0.0082F
VCC
RTN
0
200ms/Div.
PRODUCT SPECIFICATION
ML4803
VCC OVP
Component Reduction
VISENSE
VC1 RAMP
GATE
DRIVE
OUTPUT
VOUT = 400V
RP
VC1
VEAO
4
C1
30pF
RCOMP
CCOMP
35A
GATE
OUTPUT
COMP
5V
R1
CZERO
ISENSE
VI SENSE
ML4803
PRODUCT SPECIFICATION
LINE F1 5A 250V
J1-1
R24
470k
0.5W
C19
4.7nF
250VAC
102T
L2
TH1
10
5A
C4
0.47F
250VAC
Q5
R1
BR1
600V
4A
36
Q2
NEUTRAL
J1-2
1000H
R2
L3
C20
4.7nF
250VAC
C1
220F
450V
36
R22
10k
C16
0.01F
CR5
16V
0.5W
R3 0.15 3W
Q4
CR18 51V
R8 36
CR7
CR3
R30 200
T2
R13
5.8M
10
C3
1F
R14
150
2W
J2-2
L1 25H
R26
20k
3W
C26
0.01F
500V
CR8
R29 20k
R28
20k
1
2
3
CR12
C8
0.15F
CR2
30A, 60V
12VRET
R4 1k
L2
C9
1F
C22
1F
R19
10k
ML4803
PFC
PWM
GND
VCC
ISENSE ILIMIT
VEAO
VDC
CR10
C28
1F
C21
1F
CR15
R6 1.2k
CR11
C27
0.01F
U3
CR9
R21
10k
R37
330
C17
0.1F
R32 100
C14
4.7F
R9
1.5k
Q3
R5 36
R11 150
C10
2.2nF
C6
1F
4T
C5
8.2nF
C15
0.015F
J2-1
C2
2200F
R31
10
7.0V
12V
CR2
30A
60V
R27
20k
3W
C7
0.1F
CR16
IN4148
R25
390k
C25
0.01F
500V
R36 220
T1
C11
1000F
R12
5.8M
C18 4.7nF
R23
10k
C29 0.01F
R7
10
C23
0.01F
Q1
R38 22
R10
0.75
3W
R15
9.09k
C13 1nF
R17 3.3k
CR4
R20
510
3
1
U2
C12 0.1F
R18 1k
R16
2.37k
Figure 12. Typical Application Circuit. Universal Input 240W 12V DC Output
10
PRODUCT SPECIFICATION
ML4803
0.240 - 0.260
(6.09 - 6.60)
PIN1 ID
0.020 MIN
(0.51 MIN)
(4 PLACES)
0.299 - 0.335
(7.59 - 8.50)
1
0.100 BSC
(2.54 BSC)
0.015 MIN
(0.38 MIN)
0.170 MAX
(4.32 MAX)
0.125 MIN
(3.18 MIN)
0.016 - 0.020
(0.40 - 0.51)
0 - 15
0.008 - 0.012
(0.20 - 0.31)
SEATING PLANE
Package: S08
8 Pin SOIC
0.189 - 0.199
(4.80 - 5.06)
8
PIN 1 ID
1
0.017 - 0.027
(0.43 - 0.69)
(4 PLACES)
0.050 BSC
(1.27 BSC)
0.059 - 0.069
(1.49 - 1.75)
08
0.055 - 0.061
(1.40 - 1.55)
0.012 - 0.020
(0.30 - 0.51)
0.004 - 0.010
(0.10 - 0.26)
0.015 - 0.035
(0.38 - 0.89)
0.006 - 0.010
(0.15 - 0.26)
SEATING PLANE
11
ML4803
PRODUCT SPECIFICATION
Ordering Information
Part Number
PFC/PWM Frequency
Temperature Range
Package
ML4803CP-1
67kHz / 67kHz
0C to 70C
ML4803CS-1
67kHz / 67kHz
0C to 70C
ML4803IP-1*
67kHz / 67kHz
-40C to 85C
ML4803IS-1*
67kHz / 67kHz
-40C to 85C
ML4803CP-2
67kHz / 134kHz
0C to 70C
ML4803CS-2
67kHz / 134kHz
0C to 70C
ML4803IP-2*
67kHz / 134kHz
-40C to 85C
ML4803IS-2*
67kHz / 134kHz
-40C to 85C
*Available 2002
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
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8/3/01 0.0m 003
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2001 Fairchild Semiconductor Corporation