82C55A

TM

CMOS Programmable
Peripheral Interface

June 1998

Features

Description

Pin Compatible with NMOS 8255A

The Intersil 82C55A is a high performance CMOS version of

the industry standard 8255A and is manufactured using a
self-aligned silicon gate CMOS process (Scaled SAJI IV). It
is a general purpose programmable I/O device which may be
used with many different microprocessors. There are 24 I/O
pins which may be individually programmed in 2 groups of
12 and used in 3 major modes of operation. The high
performance and industry standard configuration of the
82C55A make it compatible with the 80C86, 80C88 and
other microprocessors.

24 Programmable I/O Pins

Fully TTL Compatible
High Speed, No Wait State Operation with 5MHz and
8MHz 80C86 and 80C88
Direct Bit Set/Reset Capability
Enhanced Control Word Read Capability
L7 Process

Static CMOS circuit design insures low operating power. TTL

compatibility over the full military temperature range and bus
hold circuitry eliminate the need for pull-up resistors. The
Intersil advanced SAJI process results in performance equal
to or greater than existing functionally equivalent products at
a fraction of the power.

2.5mA Drive Capability on All I/O Ports

Low Standby Power (ICCSB) . . . . . . . . . . . . . . . . . 10A

Ordering Information
PART NUMBERS
5MHz

8MHz

CP82C55A-5

CP82C55A

IP82C55A-5

IP82C55A

CS82C55A-5

CS82C55A

IS82C55A-5

IS82C55A

CD82C55A-5

CD82C55A

ID82C55A-5

ID82C55A

PACKAGE
40 Ld PDIP
44 Ld PLCC

MD82C55A-5/B MD82C55A/B
8406601QA

8406602QA

MR82C55A-5/B MR82C55A/B
8406601XA

8406602XA

40 Ld
CERDIP

TEMPERATURE PKG.
RANGE
NO.
0oC to 70oC

E40.6

-40oC to 85oC

E40.6

0oC to 70oC

N44.65

-40oC to 85oC

N44.65

0oC to 70oC

F40.6

-40oC to 85oC

F40.6

-55oC to 125oC

F40.6

SMD#
44 Pad
CLCC

F40.6
-55oC to 125oC

J44.A

SMD#

J44.A

Pinouts
RD
PA0
PA1
PA2
PA3
NC
PA4
PA5
PA6
PA7
WR
30 D7
29 NC

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002. All Rights Reserved

7
8
9
10
11
12
13
14
15
16
17

39
38
37
36
35
34
33
32
31
30
29

RESET
D0
D1
D2
D3
NC
D4
D5
D6
D7
VCC

18 1920 21 22 23 24 25 26 27 28
PB2
NC
PB3
PB4
PB5
PB6
PB7

37 D0
36 D1
35 D2
34 D3
33 D4
32 D5
31 D6

6 5 4 3 2 1 44 43 42 41 40
CS
GND
A1
A0
PC7
NC
PC6
PC5
PC4
PC0
PC1

PC2
PC3
PB0
PB1

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

RD

WR

39 NC
38 RESET

NC

VCC

PB7

PB6

PB5

PB4

PB3

PB2

13
14
15
16
17
18
19
20

31
30
29
28
27
26
25
24
23
22
21

82C55A (PLCC)
TOP VIEW

PA4
6 5 4 3 2 1 44 43 42 41 40
PA5
PA6
7
GND
PA7
NC 8
WR
A1 9
RESET
A0 10
D0
PC7 11
D1
PC6 12
D2
PC5 13
D3
PC4 14
D4
PC0 15
D5
PC1 16
D6
PC2 17
D7
18 19 20 21 22 23 24 25 26 27 28
VCC
PB7
PB6
PB5
PB4
PB3
PB1

5
6
7
8
9
10
11
12

40
39
38
37
36
35
34
33
32

PB0

1
2
3
4

PC3

PA3
PA2
PA1
PA0
RD
CS
GND
A1
A0
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
PB0
PB1
PB2

82C55A (CLCC)
TOP VIEW
CS

82C55A (DIP)
TOP VIEW

FN2969.2

82C55A
Pin Description
SYMBOL

PIN
NUMBER

VCC

26

GND

D0-D7

27-34

I/O

RESET

35

RESET: A high on this input clears the control register and all ports (A, B, C) are set
to the input mode with the Bus Hold circuitry turned on.

CS

CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the
Data Bus for CPU communications.

RD

READ: Read is an active low input control signal used by the CPU to read status
information or data via the data bus.

WR

36

WRITE: Write is an active low input control signal used by the CPU to load control
words and data into the 82C55A.

A0-A1

8, 9

ADDRESS: These input signals, in conjunction with the RD and WR inputs, control
the selection of one of the three ports or the control word register. A0 and A1 are
normally connected to the least significant bits of the Address Bus A0, A1.

PA0-PA7

1-4, 37-40

I/O

PORT A: 8-bit input and output port. Both bus hold high and bus hold low circuitry are
present on this port.

PB0-PB7

18-25

I/O

PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port.

PC0-PC7

10-17

I/O

PORT C: 8-bit input and output port. Bus hold circuitry is present on this port.

TYPE

DESCRIPTION
VCC: The +5V power supply pin. A 0.1F capacitor between pins 26 and 7 is
recommended for decoupling.
GROUND
DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the
system data bus.

Functional Diagram

POWER
SUPPLIES

+5V
GND

GROUP A
PORT A
(8)

GROUP A
CONTROL

GROUP A
PORT C
UPPER
(4)

BI-DIRECTIONAL
DATA BUS
D7-D0

DATA BUS
BUFFER
8-BIT
INTERNAL
DATA BUS

RD
WR
A1

READ
WRITE
CONTROL
LOGIC

GROUP B
CONTROL

GROUP B
PORT C
LOWER
(4)

GROUP B
PORT B
(8)

A0
RESET

CS

I/O
PA7-PA0

I/O
PC7-PC4

I/O
PC3-PC0

I/O
PB7-PB0

82C55A
Functional Description
POWER
SUPPLIES

Data Bus Buffer

This three-state bi-directional 8-bit buffer is used to interface
the 82C55A to the system data bus. Data is transmitted or
received by the buffer upon execution of input or output
instructions by the CPU. Control words and status information are also transferred through the data bus buffer.

+5V
GND

BI-DIRECTIONAL
DATA BUS
DATA
BUS
D7-D0
BUFFER

Read/Write and Control Logic

The function of this block is to manage all of the internal and
external transfers of both Data and Control or Status words.
It accepts inputs from the CPU Address and Control busses
and in turn, issues commands to both of the Control Groups.

RD
WR
A1
A0
RESET

READ
WRITE
CONTROL
LOGIC

GROUP A
CONTROL

GROUP A
PORT A
(8)

GROUP A
PORT C
UPPER
(4)
8-BIT
INTERNAL
DATA BUS

GROUP B
CONTROL

GROUP B
PORT C
LOWER
(4)

GROUP B
PORT B
(8)

I/O
PA7PA0

I/O
PC7PC4
I/O
PC3PC0

I/O
PB7PB0

(CS) Chip Select. A low on this input pin enables the

communcation between the 82C55A and the CPU.
CS

(RD) Read. A low on this input pin enables 82C55A to send

the data or status information to the CPU on the data bus. In
essence, it allows the CPU to read from the 82C55A.

FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER,

READ/WRITE, GROUP A & B CONTROL LOGIC
FUNCTIONS

(WR) Write. A low on this input pin enables the CPU to

write data or control words into the 82C55A.

(RESET) Reset. A high on this input initializes the control

register to 9Bh and all ports (A, B, C) are set to the input
mode. Bus hold devices internal to the 82C55A will hold
the I/O port inputs to a logic 1 state with a maximum hold
current of 400A.

(A0 and A1) Port Select 0 and Port Select 1. These input
signals, in conjunction with the RD and WR inputs, control
the selection of one of the three ports or the control word
register. They are normally connected to the least significant
bits of the address bus (A0 and A1).

Group A and Group B Controls

82C55A BASIC OPERATION

A1

A0

RD

WR

CS

The functional configuration of each port is programmed by

the systems software. In essence, the CPU outputs a control word to the 82C55A. The control word contains
information such as mode, bit set, bit reset, etc., that initializes the functional configuration of the 82C55A.

INPUT OPERATION
(READ)
Port A Data Bus

Port B Data Bus

Port C Data Bus

Control Word Data Bus

Each of the Control blocks (Group A and Group B) accepts

commands from the Read/Write Control logic, receives
control words from the internal data bus and issues the
proper commands to its associated ports.
Control Group A - Port A and Port C upper (C7 - C4)
Control Group B - Port B and Port C lower (C3 - C0)

OUTPUT OPERATION
(WRITE)
0

Data Bus Port A

Data Bus Port B

Data Bus Port C

Data Bus Control

The control word register can be both written and read as

shown in the Basic Operation table. Figure 4 shows the
control word format for both Read and Write operations.
When the control word is read, bit D7 will always be a logic
1, as this implies control word mode information.

DISABLE FUNCTION
X

Data Bus Three-State

Data Bus Three-State

82C55A
register will contain 9Bh. During the execution of the system
program, any of the other modes may be selected using a
single output instruction. This allows a single 82C55A to
service a variety of peripheral devices with a simple software
maintenance routine. Any port programmed as an output
port is initialized to all zeros when the control word is written.

Ports A, B, and C
The 82C55A contains three 8-bit ports (A, B, and C). All can
be configured to a wide variety of functional characteristics
by the system software but each has its own special features
or personality to further enhance the power and flexibility of
the 82C55A.

ADDRESS BUS

Port A One 8-bit data output latch/buffer and one 8-bit data
input latch. Both pull-up and pull-down bus-hold devices
are present on Port A. See Figure 2A.

CONTROL BUS
DATA BUS

Port B One 8-bit data input/output latch/buffer and one 8-bit

data input buffer. See Figure 2B.
Port C One 8-bit data output latch/buffer and one 8-bit data
input buffer (no latch for input). This port can be divided into
two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal
output and status signal inputs in conjunction with ports A
and B. See Figure 2B.

RD, WR

C
B
8

A
I/O

PB7-PB0

INPUT MODE
MODE 1

MODE 2
OUTPUT MODE

VCC

I/O

I/O

PA7-PA0

A
I/O

8
CONTROL CONTROL
OR I/O
OR I/O
C

I/O

PA7-PA0

A
BIDIRECTIONAL

I/O

PB7-PB0

PC7-PC4

PC3-PC0

B
8

FIGURE 2A. PORT A BUS-HOLD CONFIGURATION

I/O

PB7-PB0

INTERNAL
DATA OUT
(LATCHED)

B
8

EXTERNAL
PORT A PIN

RESET
OR MODE
CHANGE

A0-A1
CS

82C55A
MODE 0

MASTER
RESET
OR MODE
CHANGE
INTERNAL
DATA IN

D7-D0

CONTROL

PA7-PA0

FIGURE 3. BASIC MODE DEFINITIONS AND BUS INTERFACE

CONTROL WORD

INTERNAL
DATA IN

D7 D6 D5 D4 D3 D2 D1 D0

EXTERNAL
PORT B, C
PIN

INTERNAL
DATA OUT
(LATCHED)

GROUP B
PORT C (LOWER)
1 = INPUT
0 = OUTPUT

OUTPUT MODE

PORT B
1 = INPUT
0 = OUTPUT

FIGURE 2B. PORT B AND C BUS-HOLD CONFIGURATION

MODE SELECTION
0 = MODE 0
1 = MODE 1

FIGURE 2. BUS-HOLD CONFIGURATION

Operational Description
GROUP A

Mode Selection
PORT C (UPPER)
1 = INPUT
0 = OUTPUT

There are three basic modes of operation than can be

selected by the system software:
Mode 0 - Basic Input/Output
Mode 1 - Strobed Input/Output
Mode 2 - Bi-directional Bus

PORT A
1 = INPUT
0 = OUTPUT
MODE SELECTION
00 = MODE 0
01 = MODE 1
1X = MODE 2

When the reset input goes high, all ports will be set to the
input mode with all 24 port lines held at a logic one level by
internal bus hold devices. After the reset is removed, the
82C55A can remain in the input mode with no additional initialization required. This eliminates the need to pullup or pulldown resistors in all-CMOS designs. The control word

MODE SET FLAG

1 = ACTIVE

FIGURE 4. MODE DEFINITION FORMAT

82C55A
This function allows the programmer to enable or disable a
CPU interrupt by a specific I/O device without affecting any
other device in the interrupt structure.

The modes for Port A and Port B can be separately defined,

while Port C is divided into two portions as required by the
Port A and Port B definitions. All of the output registers,
including the status flip-flops, will be reset whenever the
mode is changed. Modes may be combined so that their
functional definition can be tailored to almost any I/O
structure. For instance: Group B can be programmed in
Mode 0 to monitor simple switch closings or display computational results, Group A could be programmed in Mode 1 to
monitor a keyboard or tape reader on an interrupt-driven
basis.

INTE Flip-Flop Definition

(BIT-SET)-INTE is SET - Interrupt Enable
(BIT-RESET)-INTE is Reset - Interrupt Disable
NOTE: All Mask flip-flops are automatically reset during mode selection and device Reset.

Operating Modes

The mode definitions and possible mode combinations may

seem confusing at first, but after a cursory review of the
complete device operation a simple, logical I/O approach will
surface. The design of the 82C55A has taken into account
things such as efficient PC board layout, control signal definition vs. PC layout and complete functional flexibility to support almost any peripheral device with no external logic.
Such design represents the maximum use of the available
pins.

Mode 0 (Basic Input/Output). This functional configuration

provides simple input and output operations for each of the
three ports. No handshaking is required, data is simply written to or read from a specific port.
Mode 0 Basic Functional Definitions:
Two 8-bit ports and two 4-bit ports
Any Port can be input or output

Single Bit Set/Reset Feature (Figure 5)

Outputs are latched

Any of the eight bits of Port C can be Set or Reset using a

single Output instruction. This feature reduces software
requirements in control-based applications.

Input are not latched

16 different Input/Output configurations possible

When Port C is being used as status/control for Port A or B,

these bits can be set or reset by using the Bit Set/Reset
operation just as if they were output ports.

MODE 0 PORT DEFINITION

A

CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
X

DONT
CARE

BIT SET/RESET
1 = SET
0 = RESET
BIT SELECT
0 1 2 3 4
0 1 0 1 0
0 0 1 1 0
0 0 0 0 1

5
1
0
1

6
0
1
1

7
1 B0
1 B1
1 B2

BIT SET/RESET FLAG

0 = ACTIVE

FIGURE 5. BIT SET/RESET FORMAT

Interrupt Control Functions

When the 82C55A is programmed to operate in mode 1 or
mode 2, control signals are provided that can be used as
interrupt request inputs to the CPU. The interrupt request
signals, generated from port C, can be inhibited or enabled
by setting or resetting the associated INTE flip-flop, using the
bit set/reset function of port C.

GROUP A
PORT C
PORT A (Upper)

GROUP B
#

PORT C
PORT B (Lower)

D4

D3

D1

D0

Output

Output

Output

Output

Output

Output

Output

Input

Output

Output

Input

Output

Output

Output

Input

Input

Output

Input

Output

Output

Output

Input

Output

Input

Output

Input

Input

Output

Output

Input

Input

Input

Input

Output

Output

Output

Input

Output

Output

Input

Input

Output

10

Input

Output

Input

Output

11

Input

Input

Input

Input

12

Output

Output

Input

Input

13

Output

Input

Input

Input

14

Input

Output

Input

Input

15

Input

Input

82C55A
Mode 0 (Basic Input)
tRR

RD
tIR

tHR

INPUT
tAR

tRA

CS, A1, A0

D7-D0
tRD

tDF

Mode 0 (Basic Output)

tWW
WR
tWD

tDW
D7-D0
tAW

tWA

CS, A1, A0

OUTPUT
tWB

Mode 0 Configurations
CONTROL WORD #0

CONTROL WORD #2

D7 D6 D5 D4 D3 D2 D1 D0
1

D7 D6 D5 D4 D3 D2 D1 D0

1
8

A
82C55A

8
B

82C55A

PC7 - PC4

PA7 - PA0
PC7 - PC4

D7 - D0

PC3 - PC0

PB7 - PB0

PC3 - PC0

PB7 - PB0

CONTROL WORD #3

D7 D6 D5 D4 D3 D2 D1 D0

1
8

A
82C55A

D7 - D0

D7 D6 D5 D4 D3 D2 D1 D0
0

CONTROL WORD #1

PA7 - PA0

D7 - D0

8
B

1
8

PA7 - PA0

A
82C55A

PC7 - PC4

C
4

D7 - D0

8
B

PC7 - PC4

PC3 - PC0

PB7 - PB0

PA7 - PA0

PC3 - PC0

PB7 - PB0

82C55A
Mode 0 Configurations (Continued)
CONTROL WORD #4

CONTROL WORD #8

D7 D6 D5 D4 D3 D2 D1 D0
1

D7 D6 D5 D4 D3 D2 D1 D0

1
8

A
82C55A

8
B

82C55A

8
B

82C55A

PB7 - PB0

82C55A

PC7 - PC4

PA7 - PA0
PC7 - PC4

D7 - D0

PC3 - PC0

PB7 - PB0

PC3 - PC0

PB7 - PB0

D7 D6 D5 D4 D3 D2 D1 D0
1

8
B

0
8

PA7 - PA0

A
82C55A

PC7 - PC4

PA7 - PA0
PC7 - PC4

D7 - D0

PC3 - PC0

PB7 - PB0

CONTROL WORD #7

PC3 - PC0

PB7 - PB0

CONTROL WORD #11

D7 D6 D5 D4 D3 D2 D1 D0
0

D7 D6 D5 D4 D3 D2 D1 D0

1
8

A
82C55A

D7 - D0

D7 - D0

0
8

PC3 - PC0

CONTROL WORD #10

PA7 - PA0

D7 D6 D5 D4 D3 D2 D1 D0

PB7 - PB0

CONTROL WORD #6

PC7 - PC4

D7 - D0
PC3 - PC0

PA7 - PA0

D7 D6 D5 D4 D3 D2 D1 D0

PC7 - PC4

D7 - D0

82C55A

1
8

CONTROL WORD #9

D7 D6 D5 D4 D3 D2 D1 D0
0

CONTROL WORD #5

PA7 - PA0

D7 - D0

8
B

1
8

PA7 - PA0

A
82C55A

PC7 - PC4

C
4

D7 - D0

8
B

PC7 - PC4

PC3 - PC0

PB7 - PB0

PA7 - PA0

PC3 - PC0

PB7 - PB0

82C55A
Mode 0 Configurations (Continued)
CONTROL WORD #12

CONTROL WORD #14

D7 D6 D5 D4 D3 D2 D1 D0
1

D7 D6 D5 D4 D3 D2 D1 D0

1
8

A
82C55A

8
B

0
8

82C55A

PA7 - PA0

PC7 - PC4

PC7 - PC4

D7 - D0

PC3 - PC0

PC3 - PC0

PB7 - PB0

PB7 - PB0

CONTROL WORD #15

D7 D6 D5 D4 D3 D2 D1 D0
0

CONTROL WORD #13

PA7 - PA0

D7 - D0

D7 D6 D5 D4 D3 D2 D1 D0

1
8

A
82C55A

D7 - D0

8
B

1
8

PA7 - PA0

PA7 - PA0

A
82C55A

PC7 - PC4

C
4

PC7 - PC4

D7 - D0

PC3 - PC0

PC3 - PC0

PB7 - PB0

PB7 - PB0

Operating Modes

MODE 1 (PORT A)

Mode 1 - (Strobed Input/Output). This functional configuration provides a means for transferring I/O data to or from a
specified port in conjunction with strobes or hand shaking
signals. In mode 1, port A and port B use the lines on port C
to generate or accept these hand shaking signals.

CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1

1/0

INTE
A

PC6, PC7
1 = INPUT
0 = OUTPUT

Mode 1 Basic Function Definitions:

Two Groups (Group A and Group B)
Each group contains one 8-bit port and one 4-bit
control/data port
The 8-bit data port can be either input or output. Both
inputs and outputs are latched.
The 4-bit port is used for control and status of the 8-bit
port.

PA7-PA0
PC4

STBA

PC5

IBFA

INTRA

PC3
RD

PC6, PC7

I/O

MODE 1 (PORT B)
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0

Input Control Signal Definition

PB7-PB0
INTE
B

(Figures 6 and 7)

PC2

STBB

PC1

IBFB

PC0

INTRB

STB (Strobe Input)

A low on this input loads data into the input latch.
RD

IBF (Input Buffer Full F/F)

FIGURE 6. MODE 1 INPUT

A high on this output indicates that the data has been

loaded into the input latch: in essence, and acknowledgment. IBF is set by STB input being low and is reset by the
rising edge of the RD input.

82C55A
tST
STB
tSIB
IBF
tSIT

tRIB

INTR

tRIT

RD
tPH
INPUT FROM
PERIPHERAL
tPS

FIGURE 7. MODE 1 (STROBED INPUT)

INTR (Interrupt Request)

INTE A

A high on this output can be used to interrupt the CPU

when and input device is requesting service. INTR is set by
the condition: STB is a one, IBF is a one and INTE is a
one. It is reset by the falling edge of RD. This procedure
allows an input device to request service from the CPU by
simply strobing its data into the port.

Controlled by Bit Set/Reset of PC6.

INTE B
Controlled by Bit Set/Reset of PC2.
NOTE:
1. To strobe data into the peripheral device, the user must operate
the strobe line in a hand shaking mode. The user needs to send
OBF to the peripheral device, generates an ACK from the peripheral device and then latch data into the peripheral device on
the rising edge of OBF.

INTE A
Controlled by bit set/reset of PC4.
INTE B

MODE 1 (PORT A)

Controlled by bit set/reset of PC2.

PA7-PA0

CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0

Output Control Signal Definition

(Figure 8 and 9)

1/0

OBF - Output Buffer Full F/F). The OBF output will go low
to indicate that the CPU has written data out to be specified
port. This does not mean valid data is sent out of the part at
this time since OBF can go true before data is available.
Data is guaranteed valid at the rising edge of OBF, (See
Note 1). The OBF F/F will be set by the rising edge of the
WR input and reset by ACK input being low.

PC4, PC5
1 = INPUT
0 = OUTPUT

INTE
A

PC7

OBFA

PC6

ACKA

INTRA

PC3
WR

ACK - Acknowledge Input). A low on this input informs the

82C55A that the data from Port A or Port B is ready to be
accepted. In essence, a response from the peripheral device
indicating that it is ready to accept data, (See Note 1).

PC4, PC5

MODE 1 (PORT B)
PB7-PB0

CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0

INTR - (Interrupt Request). A high on this output can be

used to interrupt the CPU when an output device has
accepted data transmitted by the CPU. INTR is set when
ACK is a one, OBF is a one and INTE is a one. It is reset
by the falling edge of WR.

PC1

OBFB

PC2

ACKB

PC0

INTRB

0
INTE
B

WR

FIGURE 8. MODE 1 OUTPUT

82C55A
tWOB
WR

tAOB
OBF

INTR

tWIT

ACK
tAK

tAIT

OUTPUT
tWB

FIGURE 9. MODE 1 (STROBED OUTPUT)

PA7-PA0
RD
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1

1/0

PC4

STBA

PC5

IIBFA

PC6, PC7
1 = INPUT
0 = OUTPUT

PC6, PC7
PB7, PB0

WR

WR
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0

INTRA

PC3

PA7-PA0

1/0

I/O

OBFB

PC2
PC0

PC7

OBFA

PC6

ACKA
INTRA

PC3

1
PC4, PC5
1 = INPUT
0 = OUTPUT

PC1

PC4, PC5
PB7, PB0

I/O

PC2

STBB

ACKB

PC1

IBFB

INTRB

PC0

INTRB

RD

PORT A - (STROBED INPUT)

PORT B - (STROBED OUTPUT)

PORT A - (STROBED OUTPUT)

PORT B - (STROBED INPUT)

Combinations of Mode 1: Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O
applications.
FIGURE 10. COMBINATIONS OF MODE 1

Operating Modes
Mode 2 (Strobed Bi-Directional Bus I/O)

Output Operations

The functional configuration provides a means for communicating with a peripheral device or structure on a single 8-bit
bus for both transmitting and receiving data (bi-directional
bus I/O). Hand shaking signals are provided to maintain
proper bus flow discipline similar to Mode 1. Interrupt generation and enable/disable functions are also available.

OBF - (Output Buffer Full). The OBF output will go low to

indicate that the CPU has written data out to port A.
ACK - (Acknowledge). A low on this input enables the
three-state output buffer of port A to send out the data. Otherwise, the output buffer will be in the high impedance state.
INTE 1 - (The INTE flip-flop associated with OBF). Controlled by bit set/reset of PC4.

Mode 2 Basic Functional Definitions:

Used in Group A only
One 8-bit, bi-directional bus Port (Port A) and a 5-bit
control Port (Port C)
Both inputs and outputs are latched
The 5-bit control port (Port C) is used for control and
status for the 8-bit, bi-directional bus port (Port A)

Input Operations
STB - (Strobe Input). A low on this input loads data into the
input latch.
IBF - (Input Buffer Full F/F). A high on this output indicates
that data has been loaded into the input latch.

Bi-Directional Bus I/O Control Signal Definition

INTE 2 - (The INTE flip-flop associated with IBF). Controlled

by bit set/reset of PC4.

(Figures 11, 12, 13, 14)

INTR - (Interrupt Request). A high on this output can be

used to interrupt the CPU for both input or output operations.

10

82C55A
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1

INTRA

PC3

1/0 1/0 1/0

PA7-PA0

PC2-PC0
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT

PC7

OBFA

INTE
1

PC6

ACKA

INTE
2

PC4

STBA

PC5

IBFA

WR
GROUP B MODE
0 = MODE 0
1 = MODE 1

PC2-PC0

RD

FIGURE 11. MODE CONTROL WORD

I/O

FIGURE 12. MODE 2

DATA FROM
CPU TO 82C55A

WR
tAOB
OBF
tWOB
INTR
tAK
ACK
tST
STB

tSIB
IBF
tAD
tPS

tKD

PERIPHERAL
BUS
tRIB

tPH
RD

DATA FROM
PERIPHERAL TO 82C55A

DATA FROM
82C55A TO PERIPHERAL
DATA FROM
82C55A TO CPU

NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF MASK STB RD OBF
MASK ACK WR)
FIGURE 13. MODE 2 (BI-DIRECTIONAL)

11

82C55A
MODE 2 AND MODE 0 (INPUT)

MODE 2 AND MODE 0 (OUTPUT)

PC3
PA7-PA0

1/0

PC2-PC0
1 = INPUT
0 = OUTPUT

PA7-PA0

8
OBFA

PC7
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0

PC6

ACKA

PC4

STBA

PC5

IBFA

PC2-PC0

PC3

INTRA

CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1

I/O

PB7-PB0

PC6

ACKA

PC4

STBA
IBFA

PC5
3

I/O

WR

MODE 2 AND MODE 1 (INPUT)

PA7-PA0

CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
0

PA7-PA0

8
OBFA

PC6

ACKA

PC4

STBA

PC5

IBFA

PC1

PC3

INTRA

PC7

PB7-PB0

WR

OBFA

PB7, PB0

PC3

RD

PC7

PC2-PC0

MODE 2 AND MODE 1 (OUTPUT)

RD

WR

1/0

PC2-PC0
1 = INPUT
0 = OUTPUT

RD

INTRA

CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1

OBFB

PC2

ACKB

PC0

INTRB

RD

WR

FIGURE 14. MODE 2 COMBINATIONS

12

PC7

OBFA

PC6

ACKA

PC4

STBA

PC5

IBFA

PB7-PB0

INTRA

PC2

STBB

PC1

IBFB

PC0

INTRB

82C55A
MODE DEFINITION SUMMARY
MODE 0

MODE 1

MODE 2

IN

OUT

IN

OUT

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

In
In
In
In
In
In
In
In

Out
Out
Out
Out
Out
Out
Out
Out

In
In
In
In
In
In
In
In

Out
Out
Out
Out
Out
Out
Out
Out

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

In
In
In
In
In
In
In
In

Out
Out
Out
Out
Out
Out
Out
Out

In
In
In
In
In
In
In
In

Out
Out
Out
Out
Out
Out
Out
Out

PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7

In
In
In
In
In
In
In
In

Out
Out
Out
Out
Out
Out
Out
Out

INTRB
IBFB
STBB
INTRA
STBA
IBFA
I/O
I/O

INTRB
OBFB
ACKB
INTRA
I/O
I/O
ACKA
OBFA

Special Mode Combination Considerations

GROUP A ONLY

Mode 0
or Mode 1
Only

I/O
I/O
I/O
INTRA
STBA
IBFA
ACKA
OBFA

INPUT CONFIGURATION

There are several combinations of modes possible. For any

combination, some or all of Port C lines are used for control
or status. The remaining bits are either inputs or outputs as
defined by a Set Mode command.

D7

D6

D5

I/O

I/O

IBFA

D4

D3

D2

INTEA INTRA INTEB

GROUP A

During a read of Port C, the state of all the Port C lines,

except the ACK and STB lines, will be placed on the data
bus. In place of the ACK and STB line states, flag status will
appear on the data bus in the PC2, PC4, and PC6 bit
positions as illustrated by Figure 17.

D1

D0

IBFB

INTRB

GROUP B

OUTPUT CONFIGURATION
D7

D6

OBFA INTEA

Through a Write Port C command, only the Port C pins

programmed as outputs in a Mode 0 group can be written.
No other pins can be affected by a Write Port C command,
nor can the interrupt enable flags be accessed. To write to
any Port C output programmed as an output in Mode 1
group or to change an interrupt enable flag, the Set/Reset
Port C Bit command must be used.

D5

D4

I/O

I/O

D3

D2

D1

D0

INTRA INTEB OBFB INTRB

GROUP A

GROUP B

FIGURE 15. MODE 1 STATUS WORD FORMAT

D7

D6

OBFA INTE1

D5
IBFA

D4

INTE2 INTRA

GROUP A

With a Set/Reset Port Cea Bit command, any Port C line

programmed as an output (including IBF and OBF) can be
written, or an interrupt enable flag can be either set or reset.
Port C lines programmed as inputs, including ACK and STB
lines, associated with Port C fare not affected by a
Set/Reset Port C Bit command. Writing to the corresponding Port C bit positions of the ACK and STB lines with the
Set Reset Port C Bit command will affect the Group A and
Group B interrupt enable flags, as illustrated in Figure 17.

D3

D2

D1

D0

GROUP B

(Defined by Mode 0 or Mode 1 Selection)

FIGURE 16. MODE 2 STATUS WORD FORMAT

Current Drive Capability

Any output on Port A, B or C can sink or source 2.5mA. This
feature allows the 82C55A to directly drive Darlington type
drivers and high-voltage displays that require such sink or
source current.

13

82C55A
Reading Port C Status (Figures 15 and 16)

Applications of the 82C55A

In Mode 0, Port C transfers data to or from the peripheral

device. When the 82C55A is programmed to function in
Modes 1 or 2, Port C generates or accepts hand shaking
signals with the peripheral device. Reading the contents of
Port C allows the programmer to test or verify the status of
each peripheral device and change the program flow
accordingly.

The 82C55A is a very powerful tool for interfacing peripheral

equipment to the microcomputer system. It represents the
optimum use of available pins and flexible enough to interface almost any I/O device without the need for additional
external logic.
Each peripheral device in a microcomputer system usually
has a service routine associated with it. The routine
manages the software interface between the device and the
CPU. The functional definition of the 82C55A is programmed
by the I/O service routine and becomes an extension of the
system software. By examining the I/O devices interface
characteristics for both data transfer and timing, and
matching this information to the examples and tables in the
detailed operational description, a control word can easily be
developed to initialize the 82C55A to exactly fit the
application. Figures 18 through 24 present a few examples
of typical applications of the 82C55A.

There is not special instruction to read the status information

from Port C. A normal read operation of Port C is executed
to perform this function.
INTERRUPT
ENABLE FLAG

POSITION

ALTERNATE PORT C
PIN SIGNAL (MODE)

INTE B

PC2

ACKB (Output Mode 1)

or STBB (Input Mode 1)

INTE A2

PC4

STBA (Input Mode 1 or

Mode 2)

INTE A1

PC6

ACKA (Output Mode 1 or

Mode 2)

FIGURE 17. INTERRUPT ENABLE FLAGS IN MODES 1 AND 2

INTERRUPT
REQUEST
PC3

MODE 1
(OUTPUT)

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC7
PC6
PC5
PC4

HIGH SPEED
PRINTER

HAMMER
RELAYS
DATA READY
ACK
PAPER FEED
FORWARD/REV.

82C55A
PB0
PB1
PB2
PB3
PB4
MODE 1 PB5
(OUTPUT) PB6
PB7
PC1
PC2

PAPER FEED
FORWARD/REV.
RIBBON
CARRIAGE SEN.
DATA READY
ACK

PC0
INTERRUPT
REQUEST

CONTROL LOGIC
AND DRIVERS

FIGURE 18. PRINTER INTERFACE

14

82C55A
INTERRUPT
REQUEST
PC3

MODE 1
(INPUT)

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

R0
R1
R2
FULLY
R3
DECODED
R4
KEYBOARD
R5
SHIFT
CONTROL

PC4
PC5

STROBE
ACK

INTERRUPT
REQUEST
PC3

MODE 1
(INPUT)
82C55A
PB0
PB1
PB2
PB3
PB4
MODE 1 PB5
(OUTPUT) PB6
PB7

B0
B1
B2
BURROUGHS
SELF-SCAN
B3
DISPLAY
B4
B5
BACKSPACE
CLEAR

82C55A

MODE 0
(INPUT)

DATA READY
ACK
BLANKING
CANCEL WORD

PC1
PC2
PC6
PC7

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

R0
R1
R2
FULLY
R3
DECODED
R4
KEYBOARD
R5
SHIFT
CONTROL

PC4
PC5
PC6
PC7

STROBE
ACK
BUST LT
TEST LT
TERMINAL
ADDRESS

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

INTERRUPT
REQUEST

FIGURE 20. KEYBOARD AND TERMINAL ADDRESS

INTERFACE

FIGURE 19. KEYBOARD AND DISPLAY INTERFACE

INTERRUPT
REQUEST
PA0
PA1
PA2
PA3
PA4
MODE 0 PA5
(OUTPUT) PA6
PA7
PC4
PC5
PC6
PC7
82C55A
PC0
PC1
BIT
SET/RESET PC2
PC3

LSB

PB0
PB1
PB2

LSB

MODE 0
(INPUT)

PB3
PC4
PC5
PC6
PC7

PC3

12-BIT
A/D
CONVERTER
(DAC)

MODE 1
(OUTPUT)

ANALOG
OUTPUT

R0
R1
R2
CRT CONTROLLER
R3
CHARACTER GEN.
R4
REFRESH BUFFER
CURSOR CONTROL
R5
SHIFT
CONTROL

PC7
PC6
PC5
PC4

DATA READY
ACK
BLANKED
BLACK/WHITE

PC2
PC1
PC0

ROW STB
COLUMN STB
CURSOR H/V STB

82C55A

STB DATA

SAMPLE EN
STB

8-BIT
D/A
CONVERTER
(ADC)

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

PB0
MODE 0 PB1
(OUTPUT) PB2
PB3
PB4
PB5
PB6
PB7

ANALOG
INPUT

MAB

FIGURE 21. DIGITAL TO ANALOG, ANALOG TO DIGITAL

CURSOR/ROW/COLUMN
ADDRESS
H&V

FIGURE 22. BASIC CRT CONTROLLER INTERFACE

15

82C55A

INTERRUPT
REQUEST

INTERRUPT
REQUEST
PC3

MODE 2

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

D0
D1
D2
D3
D4
D5
D6
D7

PC3

PC4
PC5
PC7
PC6

DATA STB
ACK (IN)
DATA READY
ACK (OUT)

FLOPPY DISK
CONTROLLER
AND DRIVE
MODE 1
(INPUT)

82C55A

PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7

R0
R1
R2
R3
R4
R5
R6
R7

PC4
PC5
PC6

STB
ACK
STOP/GO
MACHINE TOOL

82C55A
PC2
PC1
PC0

PB0
PB1
PB2
MODE 0 PB3
(OUTPUT) PB4
PB5
PB6
PB7

TRACK 0 SENSOR
SYNC READY
INDEX

MODE 0
(INPUT)

PC0
PC1
PC2

PB0
PB1
PB2
MODE 0 PB3
(OUTPUT) PB4
PB5
PB6
PB7

ENGAGE HEAD
FORWARD/REV.
READ ENABLE
WRITE ENABLE
DISC SELECT
ENABLE CRC
TEST
BUSY LT

FIGURE 23. BASIC FLOPPY DISC INTERFACE

B LEVEL
PAPER
TAPE
READER

START/STOP
LIMIT SENSOR (H/V)
OUT OF FLUID

CHANGE TOOL
LEFT/RIGHT
UP/DOWN
HOR. STEP STROBE
VERT. STEP STROBE
SLEW/STEP
FLUID ENABLE
EMERGENCY STOP

FIGURE 24. MACHINE TOOL CONTROLLER INTERFACE

16

82C55A
Absolute Maximum Ratings TA = 25oC

Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V

Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.5V to VCC+0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Thermal Resistance (Typical, Note 1)

JA

JC

CERDIP Package . . . . . . . . . . . . . . . .
50oC/W
10oC/W
CLCC Package . . . . . . . . . . . . . . . . . .
65oC/W
14oC/W
PDIP Package . . . . . . . . . . . . . . . . . . .
50oC/W
N/A
PLCC Package . . . . . . . . . . . . . . . . . .
46oC/W
N/A
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Junction Temperature
CDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(PLCC Lead Tips Only)

Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+4.5V to 5.5V
Operating Temperature Range
C82C55A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
I82C55A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
M82C55A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 Gates
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

VCC = 5.0V 10%; TA = 0oC to +70oC (C82C55A);

TA = -40oC to +85oC (I82C55A);
TA = -55oC to +125oC (M82C55A)
LIMITS

SYMBOL

PARAMETER

MIN

MAX

UNITS

VIH

Logical One Input Voltage

2.0
2.2

VIL

Logical Zero Input Voltage

0.8

TEST CONDITIONS
I82C55A, C82C55A,
M82C55A

V OH

Logical One Output Voltage

3.0
VCC -0.4

IOH = -2.5mA,
IOH = -100A

VOL

Logical Zero Output Voltage

0.4

IOL +2.5mA

II

Input Leakage Current

-1.0

+1.0

VIN = VCC or GND,

DIP Pins: 5, 6, 8, 9, 35, 36

IO

I/O Pin Leakage Current

-10

+10

VO = VCC or GND DIP Pins: 27 - 34

IBHH

Bus Hold High Current

-50

-400

VO = 3.0V. Ports A, B, C

IBHL

Bus Hold Low Current

50

400

VO = 1.0V. Port A ONLY

IDAR

Darlington Drive Current

-2.5

Note 2, 4

mA

Ports A, B, C. Test Condition 3

ICCSB

Standby Power Supply Current

10

VCC = 5.5V, VIN = VCC or GND. Output Open

ICCOP

Operating Power Supply Current

mA/MHz

TA = +25oC, VCC = 5.0V, Typical (See Note 3)

NOTES:
2. No internal current limiting exists on Port Outputs. A resistor must be added externally to limit the current.
3. ICCOP = 1mA/MHz of Peripheral Read/Write cycle time. (Example: 1.0s I/O Read/Write cycle time = 1mA).
4. Tested as VOH at -2.5mA.

Capacitance TA = 25oC
SYMBOL

PARAMETER

TYPICAL

UNITS

CIN

Input Capacitance

10

pF

CI/O

I/O Capacitance

20

pF

17

TEST CONDITIONS
FREQ = 1MHz, All Measurements are
referenced to device GND

82C55A
AC Electrical Specifications

VCC = +5V 10%, GND = 0V; TA = -55oC to +125oC (M82C55A) (M82C55A-5);

TA = -40oC to +85oC (I82C55A) (I82C55A-5);
TA = 0oC to +70oC (C82C55A) (C82C55A-5)
82C55A-5

SYMBOL

PARAMETER

82C55A

MIN

MAX

MIN

MAX

UNITS

TEST
CONDITIONS

READ TIMING
(1) tAR

Address Stable Before RD

ns

(2) tRA

Address Stable After RD

ns

(3) tRR

RD Pulse Width

250

150

ns

(4) tRD

Data Valid From RD

200

120

ns

(5) tDF

Data Float After RD

10

75

10

75

ns

(6) tRV

Time Between RDs and/or WRs

300

300

ns

WRITE TIMING
(7) tAW

Address Stable Before WR

ns

(8) tWA

Address Stable After WR

20

20

ns

(9) tWW

WR Pulse Width

100

100

ns

(10) tDW

Data Valid to WR High

100

100

ns

(11) tWD

Data Valid After WR High

30

30

ns

OTHER TIMING
(12) tWB

WR = 1 to Output

350

350

ns

(13) tIR

Peripheral Data Before RD

ns

(14) tHR

Peripheral Data After RD

ns

(15) tAK

ACK Pulse Width

200

200

ns

(16) tST

STB Pulse Width

100

100

ns

(17) tPS

Peripheral Data Before STB High

20

20

ns

(18) tPH

Peripheral Data After STB High

50

50

ns

(19) tAD

ACK = 0 to Output

175

175

ns

(20) tKD

ACK = 1 to Output Float

20

250

20

250

ns

(21) tWOB

WR = 1 to OBF = 0

150

150

ns

(22) tAOB

ACK = 0 to OBF = 1

150

150

ns

(23) tSIB

STB = 0 to IBF = 1

150

150

ns

(24) tRIB

RD = 1 to IBF = 0

150

150

ns

(25) tRIT

RD = 0 to INTR = 0

200

200

ns

(26) tSIT

STB = 1 to INTR = 1

150

150

ns

(27) tAIT

ACK = 1 to INTR = 1

150

150

ns

(28) tWIT

WR = 0 to INTR = 0

200

200

ns

(29) tRES

Reset Pulse Width

500

500

ns

1, (Note)

NOTE: Period of initial Reset pulse after power-on must be at least 50sec. Subsequent Reset pulses may be 500ns minimum.

18

82C55A
Timing Waveforms
tRR (3)

RD
tIR (13)

tHR (14)

INPUT
tAR (1)

tRA (2)

CS, A1, A0

D7-D0
tRD (4)

tDF (5)

FIGURE 25. MODE 0 (BASIC INPUT)

tWW (9)
WR
tDW
(10)

tWD (11)

D7-D0
tAW (7)

tWA (8)

CS, A1, A0

OUTPUT
tWS (12)

FIGURE 26. MODE 0 (BASIC OUTPUT)

tST (16)
STB

IBF

tSIB
(23)

tSIT
(26)

tRIB (24)
tRIT
(25)

INTR

RD

tPH
(18)

INPUT FROM
PERIPHERAL
tPS (17)

FIGURE 27. MODE 1 (STROBED INPUT)

19

82C55A
Timing Waveforms

(Continued)
tWOB (21)

WR

tAOB (22)
OBF

tWIT
(28)

INTR

ACK
tAK (15)

tAIT (27)

OUTPUT
tWB (12)

FIGURE 28. MODE 1 (STROBED OUTPUT)

DATA FROM
CPU TO 82C55A
WR
(NOTE)
tAOB
(22)

OBF
tWOB
(21)
INTR

tAK
(15)
ACK
tST
(16)
STB
(NOTE)
IBF

tSIB
(23)
tAD (19)
tPS (17)

tKD
(20)

PERIPHERAL
BUS
tRIB (24)

tPH (18)
RD

DATA FROM
PERIPHERAL TO 82C55A

DATA FROM
82C55A TO PERIPHERAL
DATA FROM
82C55A TO CPU

FIGURE 29. MODE 2 (BI-DIRECTIONAL)

NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF MASK STB RD OBF
MASK ACK WR)

20

82C55A
Timing Waveforms

(Continued)
A0-A1,
CS

A0-A1,
CS
tWA (8)

tAW (7)

tRA (2)

tAR (1)
tRR (3)

DATA
BUS

RD
tDW (10)

tWD (11)

(4) tRD

tDF (5)

DATA
BUS

WR

VALID
HIGH IMPEDANCE

tWW (9)

FIGURE 30. WRITE TIMING

FIGURE 31. READ TIMING

AC Test Circuit

AC Testing Input, Output Waveforms

V1

INPUT

OUTPUT

VIH + 0.4V

VOH
1.5V

R1
OUTPUT FROM
DEVICE UNDER
TEST

TEST
POINT
R2

1.5V

VIL - 0.4V

VOL

AC Testing: All AC Parameters tested as per test circuits. Input RISE and
FALL times are driven at 1ns/V.

C1
(SEE NOTE)

TEST CONDITION DEFINITION TABLE

NOTE: Includes STRAY and JIG Capacitance

TEST CONDITION

V1

R1

R2

C1

1.7V

523

Open

150pF

VCC

2k

1.7k

50pF

1.5V

750

Open

50pF

Burn-In Circuits

F14

F4

36

F2

F3

35

F5

GND
F0

7
8

34
33

GND

1 44 43 42 41 40

39

38

F5

F0

37

F15

F1

10

36

F11

F10

11

35

F12

F6

12

34

F13

F7

13

33

F14

F8

14

32

F15

F15
F11

F2

37

F14

F13

F13

F9

F12

38

F6

F7

F12

F8

F8

F11

39

F9

40

F4

F7

F3

F6

F11

MR82C55A CLCC

MD82C55A CERDIP

F1

32

F10

10

31

F13

F6

11

30

F14

F7

12

29

F15

F8

13

28

F11

F9

15

31

F11

F9

14

27

F12

F10

16

30

F12

F10

15

26

F6

17

29

F6

16

25

F13

F7

17

24

F14

F8

18

23

F15

F9

19

22

F11

F10

20

21

F12

NOTES:
1.
2.
3.
4.

VCC = 5.5V 0.5V

VIH = 4.5V 10%
VIL = -0.2V to 0.4V
GND = 0V

18 19 20 21 22 23 24 25 26 27 28

C1

NOTES:
1.
2.
3.
4.

21

C1 = 0.01F minimum
All resistors are 47k 5%
f0 = 100kHz 10%
f1 = f0 2; f2 = f1 2; . . . ; f15 = f14 2

VCC

F13

F14

F15

F11

F12

F10

F7

C1
F9

VCC

F8

F12

82C55A
Die Characteristics
DIE DIMENSIONS:
95 x 100 x 19 1mils

GLASSIVATION:
Type: SiO2
Thickness: 8k 1k

METALLIZATION:
Type: Silicon - Aluminum
Thickness: 11k 1k

WORST CASE CURRENT DENSITY:

0.78 x 10 5 A/cm2

Metallization Mask Layout

82C55A

RD

PA0

PA1 PA2

PA3 PA4 PA5 PA6 PA7

WR

RESET

CS
GND

D0

A1

D1

A0

D2

PC7

D3

PC6

D4

PC5

D5

PC4

D6

PC0

D7

PC1

VCC

PC2

PD3

PB0

PB1 PB2

22

PB3 PB4

PB5 PB6

PB7

82C55A
Dual-In-Line Plastic Packages (PDIP)
E40.6 (JEDEC MS-011-AC ISSUE B)

40 LEAD DUAL-IN-LINE PLASTIC PACKAGE

E1

INDEX
AREA

1 2 3

INCHES

N/2

SYMBOL
-B-

-C-

A2

SEATING
PLANE

B1
B

D1

A1

eC

0.010 (0.25) M C A B S

MAX

NOTES

0.250

6.35

0.015

0.39

A2

0.125

0.195

3.18

4.95

0.014

0.022

0.356

0.558

C
L

B1

0.030

0.070

0.77

1.77

eA

0.008

0.015

0.204

0.381

1.980

2.095

D1

0.005

A
L

D1

MIN

A
E

MAX

A1

-ABASE
PLANE

MILLIMETERS

MIN

eB

NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the MO Series Symbol List in Section 2.2
of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.

50.3

53.2

0.13

0.600

0.625

15.24

15.87

E1

0.485

0.580

12.32

14.73

0.100 BSC

2.54 BSC

eA

0.600 BSC

15.24 BSC

eB

0.700

0.115

0.200

2.93

40

40

17.78

5.08

4
9
Rev. 0 12/93

5. D, D1, and E1 dimensions do not include mold flash or protrusions.

Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

23

82C55A
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.048 (1.22)
PIN (1) IDENTIFIER

0.042 (1.07)
0.056 (1.42)

0.004 (0.10)

0.025 (0.64)
R
0.045 (1.14)

0.050 (1.27) TP

C
L

D2/E2
C
L
E1 E
D2/E2
VIEW A

0.020 (0.51)
MIN

A1
A

D1
D

0.026 (0.66)
0.032 (0.81)

MIN

0.013 (0.33)
0.021 (0.53)

0.025 (0.64)
MIN

0.045 (1.14)

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

MIN

MAX

NOTES

0.165

0.180

4.20

4.57

A1

0.090

0.120

2.29

3.04

0.685

0.695

17.40

17.65

D1

0.650

0.656

16.51

16.66

D2

0.291

0.319

7.40

8.10

4, 5

0.685

0.695

17.40

17.65

E1

0.650

0.656

16.51

16.66

E2

0.291

0.319

7.40

8.10

4, 5

44

44

6
Rev. 2 11/97

SEATING
-C- PLANE

0.020 (0.51) MAX

3 PLCS

N44.65 (JEDEC MS-018AC ISSUE A)

44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

VIEW A TYP.

NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions
are not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at
the extreme material condition at the body parting line.
4. To be measured at seating plane -C- contact point.
5. Centerline to be determined where center leads exit plastic body.
6. N is the number of terminal positions.

24

82C55A
Ceramic Leadless Chip Carrier Packages (CLCC)
J44.A

MIL-STD-1835 CQCC1-N44 (C-5)

44 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE

0.010 S E H S
D

INCHES

D3

SYMBOL

j x 45o

E3

0.010 S E F S
A1
PLANE 2

0.120

1.63

3.05

6, 7

0.088

1.37

2.24

0.033

0.039

0.84

0.99

B1

0.022

0.028

0.56

0.71

2, 4

-H-

L3

0.022

0.15

0.56

0.640

0.662

16.26

16.81

D1

0.500 BSC

12.70 BSC

D2

0.250 BSC

6.35 BSC

D3

0.662

0.640

0.662

16.26

16.81

16.81

E1

0.500 BSC

12.70 BSC

E2

0.250 BSC

6.35 BSC

0.662

0.050 BSC
0.015

0.040 REF
0.020 REF

16.81
1.27 BSC

0.38

2
-

1.02 REF

0.51 REF

0.045

0.055

1.14

1.40

L1

0.045

0.055

1.14

1.40

L2

0.075

0.095

1.90

2.41

L3

0.003

0.015

0.08

0.38

ND

11

11

NE

11

11

44

44

-F-

3
Rev. 0 5/18/94

NOTES:

B3

E1

E2

1.83 REF

0.006

0.072 REF

B3

NOTES

0.064

e1

B1

MAX

0.054

0.007 M E F S H S

MIN

E3

PLANE 1

-E-

MILLIMETERS

MAX

A1

B2

h x 45o

MIN

1. Metallized castellations shall be connected to plane 1 terminals

and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.

L2
B2

2. Unless otherwise specified, a minimum clearance of 0.015 inch

(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)

L1

3. Symbol N is the maximum number of terminals. Symbols ND

and NE are the number of terminals along the sides of length
D and E, respectively.

D2

e1
D1

4. The required plane 1 terminals and optional plane 2 terminals (if

used) shall be electrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturers option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
7. Dimension A controls the overall package thickness. The maximum A dimension is package height before being solder dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.

25

82C55A
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
F40.6 MIL-STD-1835 GDIP1-T40 (D-5, CONFIGURATION A)
40 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

LEAD FINISH

c1
-D-

-A-

BASE
METAL

SYMBOL

E
M
-Bbbb S

C A-B S

-C-

S1

0.225

5.72

0.026

0.36

0.66

b1

0.014

0.023

0.36

0.58

b2

0.045

0.065

1.14

1.65

b3

0.023

0.045

0.58

1.14

0.008

0.018

0.20

0.46

c1

0.008

0.015

0.20

0.38

2.096

53.24

0.510

0.620

15.75

eA

b2

b
ccc M C A - B S

eA/2

aaa M C A - B S D S

D S

NOTES

0.014

A A

MAX

A
L

MIN

SEATING
PLANE

MILLIMETERS

MAX

M
(b)

BASE
PLANE

MIN

b1

SECTION A-A

D S

INCHES

(c)

NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturers identification shall not be used
as a pin one identification mark.

12.95

0.100 BSC

2.54 BSC

eA

0.600 BSC

15.24 BSC

eA/2

0.300 BSC

7.62 BSC

0.125

0.200

3.18

5.08

0.015

0.070

0.38

1.78

S1

0.005

0.13

105o

90o

105o

2. The maximum limits of lead dimensions b and c or M shall be

measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.

90o

aaa

0.015

0.38

3. Dimensions b1 and c1 apply to lead base metal only. Dimension

M applies to lead plating and finish thickness.

bbb

0.030

0.76

ccc

0.010

0.25

0.0015

0.038

2, 3

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a

partial lead paddle. For this configuration dimension b3 replaces
dimension b2.

40

40

8
Rev. 0 4/94

5. This dimension allows for off-center lid, meniscus, and glass

overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporations quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

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NORTH AMERICA
Intersil Corporation
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TEL: (949) 341-7000
FAX: (949) 341-7123

Intersil Corporation
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TEL: (321) 724-7000
FAX: (321) 724-7946

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1006 Lausanne
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TEL: +41 21 6140560
FAX: +41 21 6140579

26

ASIA
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TEL: +852 2723 6339
FAX: +852 2730 1433