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FPGA Implementation of a Single-Input Fuzzy Logic

Controller for Boost Converter With the Absence
of an External Analog-to-Digital Converter
Fazel Taeed, Zainal Salam, Member, IEEE, and Shahrin M. Ayob, Member, IEEE

AbstractIn this paper, the single-input fuzzy logic controller

(FLC) (SIFLC) for boost converter output-voltage regulation is
proposed. The SIFLC utilizes the signed distance method that
reduces the multidimensional rule table to 1-D with only one
input variable, i.e., distance d. The simplification allows for the
control surface to be approximated by a piecewise linear. It is
shown that, despite the simplicity of SIFLC, its control performance is almost equivalent to that of the conventional FLC. As
a proof of concept, the SIFLC is implemented using the Altera
EP2C35F672C6N field-programmable gate array (FPGA) and
applied on a 50-W boost converter. The SIFLC is compared to
the proportionalintegral controller; the simulation and practical
results indicate that SIFLC exhibits excellent performance for
step load and input reference changes. Another feature of this
work is the absence of an external analog-to-digital converter
(ADC). Instead, a simple analog-to-digital conversion scheme is
implemented using the FPGA itself. Due to the simplicity of
the SIFLC algorithm and the absence of an external ADC, the
overall implementation requires only 408 logic elements and five
inputoutput pins of the FPGA.
Index TermsBoost converter, field-programmable gate array
(FPGA), fuzzy logic controller (FLC), single-input fuzzy logic
controller (SIFLC).

I. I NTRODUCTION

HE design of high-performance linear proportional

integral (PI) controller for boost converter presents a challenge due to several reasons. In addition to being a nonlinear
and time-varying system, a boost converter exhibits a righthalf-plane zero that is dependent on load resistance [1]. As
a result, the linear controller could not perform satisfactorily
when subjected to large load disturbance. In addition, the linear
controller may experience difficulty in handling rapid input
voltage reference change [2].
Furthermore, sensitivity to the changes in system parameters
such as temperature variation and component aging can be of a
major concern.

Manuscript received December 7, 2011; revised March 3, 2011 and April 22,
2011; accepted May 27, 2011. Date of publication July 5, 2011; date of current
version October 18, 2011. This work was supported by the Energy Research
Alliance, Research Management Center, Universiti Teknologi Malaysia, under
New Academic Staff (NAS) Fund (Vot. 77955).
F. Taeed and S. M. Ayob are with the Department of Energy Conversion,
Faculty of Electrical Engineering, Universiti Teknologi Malaysia, Skudai
81310, Malaysia (e-mail: fazel.taeed@gmail.com; shahrin@fke.utm.my).
Z. Salam is with the Inverter Quality Control Center, Universiti Teknologi
Malaysia, Skudai 81310, Malaysia (e-mail: zainals@fke.utm.my).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2011.2161250

Recently, several attempts have been made to use nonlinear

controller, particularly the fuzzy logic controller (FLC), to
control power electronic converters [3][10]. FLC is known to
be robust and has excellent immunity to external disturbances
[11]. However, the accuracy of FLC is determined by numerous
parameters; the most important ones are the number of inputs
and its corresponding rule table. A speed/accuracy tradeoff,
therefore, is inevitable. Additionally, other fuzzy processes
such as fuzzification, rule-based evaluation, and defuzzification
need to be considered. As a result, parameter tuning can be tedious, and hardware implementation often requires substantial
computing resources [12].
In this paper, the single-input FLC (SIFLC) for boost converter regulation is proposed. The motivation is to find a simpler
and faster method to implement FLC without compromising
the unique fuzzy capabilities. The SIFLC is expected to reduce
the computational burden because it has significantly fewer
rules to evaluate and does not require the fuzzy processes
mentioned earlier. Moreover, it is possible to translate the rules
to a piecewise linear (PWL) control surface which can be
constructed simply by using a lookup table (LUT) [13].
Naturally, the hardware realization of FLC/SIFLC will always be digital because its algorithm is primarily based on rule
inferences, i.e., using the if-then-else statements. Implementationwise, the use of digital processor such as microcontroller,
digital signal processor (DSP) and field-programmable gate
array (FPGA) is widespread [14], [15]. The main challenge,
however, is to compute the algorithm fast enough to achieve
good control bandwidth. Consequently, a powerful processor
may be required to expedite the task, but the cost may not
be justifiable in certain applications. Furthermore, since the
control variables are sensed in analog, the use of analogto-digital converter (ADC) is unavoidable. The conversion
time of the ADC (particularly, the lower cost ones) imposes
additional constraint to the processor. Considering these issues, this paper proposes a realization of SIFLC using FPGA
without the use of conventional (external) ADC. The analog
signal is converted to digital number by the FPGA itself,
using a simple schememade possible by virtue of SIFLCs
PWL control surface. The main advantages of this technique
are the following: 1) the absence of external ADC means
that fewer pins/gates of the FPGA are utilized and smaller
printed circuit board (PCB) footprint; 2) adjustable analogto-digital conversion time allows for more freedom to decide
the control bandwidth; and 3) no voltage reference sensitivity

0278-0046/$26.00 2011 IEEE

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TABLE I
FLC RULE TABLE W ITH T OEPLITZ S TRUCTURE

Fig. 1. Derivation of distance variable d.

TABLE II
SIFLC RULE TABLE U SING S IGNED D ISTANCE M ETHOD

issue because the technique does not require a reference

voltage.
Although specialized FPGA-based ADC is available in the
market [16], its conversion method is not adequately disclosed.
Its application is mainly dedicated to audio and low-frequency
sensors with 20-kHz maximum bandwidth. Furthermore, the
analog signal is capacitive coupling, implying that the dc signal
is blocked. On the other hand, the proposed ADC can be used
for both ac and dc signals. It could achieve bandwidth up
to 100 kHz which can be very useful for high-performance
control applications. Another attempt to design a controller
without an external ADC was reported in [17]. However, its
implementation was done at the semiconductor levelwhich is
not possible using the standard FPGA chip.
This paper is organized as follows. In the next section, an
overview of SIFLC is given. This includes the derivation of
the reduced rule table using the signed distance method and
the construction of the PWL control surface. Then, the equivalency of SIFLC and the conventional FLC (CFLC) is evaluated. The digital implementation of SIFLC using the Altera
EP2C35F672C6N FPGA without an external ADC is outlined.
This is followed by a design example using the SIFLC for a
boost converter. To validate the idea, a 50-W boost converter is
built. The SIFLC is implemented along with the PI controller
(as a comparison). In the result section, the performances
of both controllers are compared by simulation and practical
results.
II. SIFLC
A. Signed Distance Method
The rule table of a CFLC can be created by a 2-D array of
input error (e), change of error (e),
and outputs. A typical rule
table for CFLC with Teoplitz structure is shown in Table I [18].
The same output memberships (NM, PS, etc.) are diagonally
aligned with each point on a particular diagonal line which has
a magnitude proportional to the distance from its main diagonal
line LZ . The Toeplitz or near-Toeplitz property is true for all
FLC types which use the error and its derivative terms and is a
commonplace in power converters [18][23].
From Table I, it can be seen that it is possible to obtain the
corresponding output u o using a single variable input which

Fig. 2. SIFLC control structure.

Fig. 3. CFLC control structure.

represents the absolute distance (d) of the parallel diagonal

lines (LNL , LNM , LNS , LZ , LPS , LPM , and LPL ) from LZ .
To derive d, let Q(e0 , e 0 ) be an intersection point of the main
diagonal line and the line perpendicular to it from a known operating point P (e1 , e 1 ) (Fig. 1). Noting that the main diagonal
line can be represented as e + e = 0, the absolute distance d
from point P to point Q can be formulated as
e + e
d=
.
1 + 2

(1)

The aforementioned derivation reduces Table I to an SIFLC

with a 1-D rule table, as shown in Table II. The control action in
Table II is exclusively determined by a sole input, i.e., d. Figs. 2
and 3 compares the functional control structures of SIFLC and
the CFLC, respectively. The main advantage of SIFLC is the
significant reduction in the number of rules. For a typical twoinput CFLC with fuzzification level p, the number of rules to
be inferred is p2 . On the other hand, SIFLC requires only p rule
inferences.
B. SIFLC Control Surface
Using Table II, the SIFLC control surface can be approximated as a PWL function. This can be realized by various combinations of inputoutput (IO) membership function (MF) and

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Fig. 6.

MFs (a) for inputs (error and change of error) and (b) output.
TABLE III
RULE TABLE FOR CFLC

Fig. 4. PWL control surface with several PWL regions.

Fig. 5. SIFLC with PWL control surface.

fuzzification and defuzzification operators. Based on the procedures outlined in [24], an optimized PWL surface is achieved
by the following conditions: 1) the input MF is triangular shape
but not necessarily with a 50% overlap; 2) the output MF has
singleton shape; 3) fuzzification using center of gravity (CoG);
and 4) defuzzification using CoG. Fig. 4 shows an example of a
PWL control surface in which the triangular-shaped input MF
does not have a 50% overlap while the singleton output MFs are
arranged in unequal spacing. Note that such arrangement results
in a PWL function with multiple linear sections of different
slopes. It also introduces several breakpoints (BPs), which are
defined as the transition point between two PWL slopes.
The ability to reduce the 3-D control surface to a PWL
function simplifies the SIFLC to the block diagram shown in
Fig. 5. Clearly, the PWL function is much simpler to construct
compared to the CFLC control surface.
C. SIFLC/CFLC Performance Comparison
To demonstrate the equivalent control actions produced by
CFLC and SIFLC, MATLAB simulation of a boost converter
using the average model [25] is carried out. Note that the
purpose of this exercise is to show the similarity in response
for both controllers; therefore, the designs are not optimized.
The CFLC is of the Sugeno type. Its input MF for both the
error and change of error is shown in Fig. 6(a). The output MF
is an unequal spaced singleton, shown in Fig. 6(b). These MFs
are designed and heuristically tuned using the MATLAB Fuzzy
Toolbox.
The rules for CFLC are shown in Table III. The resulting control surface is shown in Fig. 7(a). For an equivalent SIFLC,

Fig. 7. (a) Control surface for CFLC. (b) Equivalent SIFLC PWL corresponding to MFs in Fig. 6.

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TABLE IV
RULE TABLE FOR SIFLC

Fig. 9. Output voltage of the boost converter for reference change test. The
reference is stepped from 15 to 20 V for 10- load. (a) CFLC. (b) SIFLC.
(c) Difference (error) between CFLC and SIFLC.

Fig. 8. Output voltage of boost converter in load step change from 10 to 5 .

(a) CFLC. (b) SIFLC. (c) Difference (error) between CFLC and SIFLC.

the reduced rule table is shown in Table IV. Its corresponding

PWL control surface is shown in Fig. 7(b). Note that the PWL is
designed to have a unity slope around the origin, i.e., for region
0 < d < 5. After the first BP (BP1 ), the slope increases rapidly
to nine. Then, after the second BP (BP2 ), the slope reduces to
0.5 until it reaches the saturation limit.
The CFLC and SIFLC were applied to the boost converter
model. Fig. 8(a) and (b) shows the output voltage of the
converter when the load is stepped from 10 to 5 (100% load
change). As can be observed, the response of CFLC and SIFLC
is very close to each other.
For clarity, the difference between the two is plotted in a
separate trace, i.e., Fig. 8(c). As can be seen, the difference
(error) is very small; the maximum error is less than 0.33%
of the output voltage. Similar results are observed for input
reference change shown in Fig. 9(a)(c). With a reference step
changed from 15 to 20 V, the maximum error is kept below
0.5%. From these results, it can be justified that the CFLC can

Fig. 10. Boost converter circuit and values.

be replaced by SIFLC without any significant degradation in

the control performance.
III. H ARDWARE
A. Controller Design Procedures
To validate the effectiveness of SIFLC in a practical circuit,
a 50-W boost converter, shown in Fig. 10, is designed and built.
The nominal output is 15 V, and the switching frequency of the
converter is 100 kHz.
The SIFLC is designed to cater for two different types of
disturbances, namely, the small-signal (for small d) and largesignal (large d) disturbances. For small-signal disturbance, previous researchers have demonstrated that FLC exhibits inferior

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Fig. 11. Block diagram of the discrete PI controller.

Fig. 13.

Fig. 12. Block diagram of discrete SIFLC.

performance; it was suggested that FLC is replaced by PI for

this region [26][28]. For large-signal disturbance, heuristic
tuning of the PWL control surface is carried out to determine
the optimum BPs and slope values. Since the controller is
digital, the design is done in discrete form.
Figs. 11 and 12 show the block diagrams of the discrete PI
and SIFLC, respectively. Note that structurewise, SIFLC is very
similar to PI controller if the control surface of the former is
set to unity value. To ensure that the SIFLC performs as a PI
(for small disturbance), the following conditions must be met.
In Fig. 11, m and n variables of the discrete PI controller are
given by [27]


Kp
Ts
+
(2)
m = Ki
Ki
2


Ts
Kp

(3)
n = Ki
2
Ki
where Ts is a sampling time of the controller. The output of the
discrete PI can be expressed in difference equation, i.e.,


(n)
e(k)

.
(4)
u(k)

= (m + n) e(k) +
(m + n)
Referring to Fig. 12, the output equation of SIFLC with unity
control surface can be written as


e(k)
e(k)

u(k)

= (r)
+
.
(5)
1 + 2
1 + 2
Comparing (4) and (5), the output voltage for the SIFLC and
PI will be similar if the following equalities for and r are
met, i.e.,
m+n
n
r = m + n.

(6)
(7)

For large-signal disturbance, the PWL control surface of the

SIFLC is adjusted to compensate for the change in d. This is

PWL controller surface for large-/small-signal disturbances.

done heuristically as shown in Fig. 13. Two parameters are

adjusted, namely, the BP (BP1 and BP2 ) and slope S1 . Note
that, for the small-signal region, i.e., small value of d, the slope
is maintained at unity as described earlier. For larger value of d,
the slope S1 is reduced below unity to reduce overshoot (largesignal region). Beyond BP2 , the controller enters saturation,
i.e., the region with zero slope.

B. FPGA Implementation Without External ADC

The SIFLC algorithm is implemented using the
EP2C35F672C6N FPGA from Altera. Like all digital controllers, the use of an ADC is inevitable as the analog feedback
signal has to be converted to digital for further computation.
However, embedded ADC is not a common feature of FPGA;
normally, an external ADC is required. There are several
disadvantages of external ADC. First, it requires IO pin that is
proportional to a number of digital bits of the converted data.
Furthermore, external connections increase the PCB footprint.
Second, ADC, typically the low cost one, has considerable
conversion time. For example, the conversion time for AD571
(10-b ADC) is 40 s. This limits the control bandwidth.
Although conversion speed increases for ADC with lower
number of bits, the accuracy decreases.
Due to these reasons, a simple analog voltage conversion
based on the pulsewidth control is designed. No external ADC
chip is required; the analog-to-digital conversion is done by a
combination of standard operational amplifier (op-amp) circuits
and pulsewidth control using the FPGA itself. The idea is depicted by the circuit in Fig. 14(a) and its corresponding timing
diagram in Fig. 14(b). First, a 100-kHz unipolar carrier signal
with 80% duty cycle is generated using the FPGA. The choice
of this particular duty cycle is to obtain a conversion time of less
than 8 s. The unipolar signal is converted to bipolar by adding
an offset voltage to the noninverting terminal of U1 (note that
U1 is an inverting amplifier). The bipolar waveform is then
integrated to form triangular waveform trains using an integrator (U2). Diodes D1 and D2 are required to generate different
integrator gains for positive and negative slopes, respectively.
The analog (feedback) signal from the output voltage of the
boost is compared with the triangular waveform (output of U2)
using comparator U3. The comparison generates a pulse (called
the PW-data) with a duty cycle proportional to the measured
analog signal.

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Fig. 16. Timing schedule of SIFLC algorithm.

TABLE V
EP2C35F672C6N FPGA R ESOURCE U TILIZATION U SING SIFLC

TABLE VI
L OGIC E LEMENT U SAGE BY N UMBER OF LUT I NPUTS

Fig. 14. (a) Circuit to generate PW-data. (b) Timing diagram for PW-data
generation.

Fig. 15. Timing diagram of PW-data conversion simulated in Quartus II.

To obtain the corresponding digital number, the PW-data is

fed to the input of the FPGA. A special high-speed counter
(based on clk1, running at 100 MHz) is designed to convert the
duty cycle of the PW-data to digital by incrementing the counter
value. Each count has a resolution of 10 ns. The conversion
process for PW-data to a digital number is simulated using the
Quartus II software, shown in Fig. 15. From the timing diagram,
it can be observed that, at every positive edge of the carrier
signal, the counter resets. Then, the counter increments itself
until it encounters the negative edge of PW-data waveform.
Upon the completion of the counting, the final counter value,
which is directly proportional to the analog signal, is stored.
In the example shown in Fig. 15, two PW-data (PW-data 1
and PW-data 2) which correspond to two different widths
(therefore, two different analog signal levels) are shown; the
final values of the counter are 697 and 495, respectively. These
are the digital data that will be used for further computation.
Since the maximum value for the counter is calibrated to be
800 for a full scale of 15 V, the corresponding analog voltage in
these two cases are 13.07 and 9.28 V, respectively.
C. FPGA RTL Block and Timing
Fig. 17 shows the overall block diagram of the controller
shown in the FPGAs Register Transfer Language (RTL) format. The SIFLC is a single feedback loop structure, i.e., voltage

control. In terms of functionality, the RTL can be divided

into two types, namely, sequential and combinational logics.
The former is composed of the analog-to-digital conversion,
differentiator, and integrator. They are time (clock) driven and
are initiated when an enable signal is activated. The remaining
logics are combinational type or nonclock dependent, which
means that they are timingwise and are always active. The
control pulsewidth modulation (PWM) pulse for the MOSFET
is generated using the PWM block. It is based on a 200 MHz
clock (clk3), which means that the PWM pulse has a 5-ns
resolution. Such very high resolution PWM is not achievable
in a standard microprocessor or DSP. The main advantage of
high-resolution PWM pulse is reduced steady-state error and
increased controller speed. The maximum frequency of the
PWM pulse is 100 kHz.
The timing schedule for the controller is designed as follows.
Typically, each analog-to-digital conversion using the proposed
method requires 8 s (maximum). Although two conversions
take place, the time remains the same because they run in
parallel. Once data conversions are completed, the differentiator
block is enabled by signal enb2. The data pass through the
divider, adder, and the PWL control surface. The differentiator
requires five clock cycles while the divider, adder, and control
surface require one clock each. Since the system clock (clk3)
is 50 MHz, it requires 0.16 s to accomplish all these tasks.
Thereafter, the data will be integrated by an integrator. It has
the same execution time as the differentiator (0.1 s). The
remaining blocks, i.e., the gain and subtractor, require only one
clock cycle each. The total time required for the execution of
the SIFLC algorithm is therefore less than 10 s, in which 8 s
is used for the analog conversion. Since the selected switching
frequency of the converter is 100 kHz, it is possible to update
the control pulse at every switching period. Fig. 16 shows the

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Fig. 17. RTL schematic of SIFLC.

scheduling and the time required to complete each task in the

SIFLC execution.
Table V shows the FPGA resource utilization using the proposed scheme. From the table, it can be observed that the SIFLC
code utilizes a very small portion of the FPGA resources; it
requires less than 1.3% of the total number of the available
logic gates. These logic gates are used mainly to build the LUT
as summarized in Table VI. For multipliers, LPM functions
are employed to generate the required 15-b multiplier block as
shown in Fig. 17. None of the on-chip embedded multipliers is
used because of the insufficient bit size (only 9-b multiplier is
provided). In addition to these, 36 logic array blocks are used.
Since the number of gates and pins used for SIFLC is very
few, the algorithm can be implemented on a much smaller and
cheaper complex programmable logic device (CPLD). Examples of low-cost CPLD are the EPM3032A and EPM3064A
(both from Altera). The former is composed of 600 logic gates
with 34 IO pins while the latter has 1250 and 64, respectively.
Both chips can operate at a maximum clock speed of 227 MHz.
IV. R ESULTS
A. Simulation
The SIFLC is designed as described in Section III-A. For
a more realistic comparison, instead of average model, the
MATLAB/Simulink simulation is performed using the actual
switch model of the boost converter. The component values and
converter parameters in Fig. 12 are used. To evaluate the performance of SIFLC, a comparison is made with PI controller.
The latter is designed using the procedures outlined in [26]. The
values of discrete PI parameters are as follows: n = 0.3 and
m = 1.3. Utilizing (6) and (7), the resulting SIFLC constants
and r are 3.33 and 1, respectively.
Fig. 18(a) shows the simulated response of the PI and
SIFLC for step load change; the load resistance is stepped
from 10 (nominal load) to 5 . The slope S1 for SILFC is
set to 0.5. As can be seen, the PI response is typical, similar
to that demonstrated by other researchers [11]. However, for
SIFLC, excellent response is observed. During transient, it
exhibits almost negligible overshoot and very short settling
time. Despite these facts, the output voltage has the same dip
and follows a recovery pattern similar to PI.

Fig. 18. Boost converter response for step change in load from 10 to 3 for
S1 = 0.5. (a) Output voltage. (b) Input of PWL control surface.

The superiority of SIFLC for step load change can be understood by observing the behavior of its control action. This can
be best investigated by looking on how the distance d varies
with time, as shown in Fig. 18(b). Prior to the disturbance,
the controller operates mostly within the unity slope region,
i.e., S1 = 1. When disturbance occurs at t = 0.25 s, a sudden
increase in d causes it to exceed BP BP1 , forcing the controller
to migrate to the large-signal region. Since, in this region,
S1 = 0.5, the overshoot is reduced by rapid compensation of
the control pulses. In this case, because the load change is
severe, d exceeds the second BP BP2 and enters the saturation
region. The overshoot is reduced further because, in the saturation region, the slope is zero. Meanwhile, as the pulses are
compensated, d is reduced, and the controller falls back into the
large-signal region and finally settles in the steady-state region
(unity slope).

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Fig. 19. Boost converter response to change in reference voltage from 12.5 to
15 V in R = 10 .

Clearly, the locations of BPs (BP1 and BP2 ) and the slope
value S1 influence the transient response directly. If the selections of these parameters are not appropriate, the response
may not be optimum. Since there is no documented procedure
on how these values can be systematically tuned, heuristic
approach is sought, as explained in Section III-A. Nevertheless,
adjusting the values of BPs and the slope of SIFLC is considerably easier compared to the parameters and rule table tuning in
a CFLC.
Fig. 19 shows the simulated reference change test; the reference voltage is stepped from 12.5 to 15 V with the load
maintained at 10 . For SIFLC, two cases for the slopes are
presented: low value of S1 = 0.5 and high value of S1 = 1.1.
As can be seen, the performance of the SIFLC with S1 = 0.5
appears to be inferior to PI. However, when S1 is increased to
1.1, the voltage tracking of the SIFLC improves significantly,
i.e., comparable to PI. The faster rise of output voltage using
higher S1 value is attributed to the fact that the compensation
rate for duty cycles is greater.
Although there seems to be a contradiction for S1 for load
change, it can be solved by interchanging its value; whenever
a reference change is demanded, S1 is switched to a higher
value. Otherwise, S1 remains at a lower value to cater for
unpredictable load change. This scheme is appropriate because,
typically, a reference change is a planned disturbance, i.e., its
occurrence is known beforehand. A simple flag/check statement
can be inserted in the software to notify the controller that a
reference change is demanded, and consequently, the correct
value of S1 is set.

Fig. 20. PWM-data generation for two different output voltages. (a) V o =
12.5 V. (b) V o = 15 V. Legend: (CH1) Carrier signal (2 V/div), (CH2)
triangular signal (5 V/div), (CH3) output voltage (diminished) (200 mV/div),
and (CH4) PW-data (10 V/div). Horizontal time scale: 5 s/div.

B. Hardware
Fig. 20 shows the operation of the analog-to-digital conversion scheme described in Section III-B. Two cases are
considered; in CH3 of Fig. 20(a), the measured analog signal
is 12.5 V, while in Fig. 20(b), it is 15 V. The resulting PWdata for each case is shown by its corresponding CH4. As can
be seen, the PW-data varies according to variation of the output
voltage of the boost converter. With the horizontal time scale set
at 2 s/div, the digital number that corresponds to the analog
voltage can be obtained. These waveforms are similar to the
ones shown in Fig. 14 except that, in the latter figure, two cases
are shown in one plot.

Fig. 21. Boost converter response to change in the load from 10 to 5 ,

in V o = 15. (a) Using PI controller. (b) Using SIFLC (S1 = 0.5).

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For the reference change, two sets of results are shown for
SIFLC, i.e., using S1 = 1.1 and S1 = 0.5. These are shown in
Fig. 22(a) and (b), respectively. From the oscillogram, it can be
seen that the SIFLC with S1 = 0.5 has a slower response to the
step change; the rise time for the output voltage is measured
to be 2 ms. On the other hand, the rise time for SIFLC with
S1 = 1.1 is about 1.2 ms. Furthermore, the settling time for
S1 = 1.1 (within a 5% error band) is 0.8 ms, while for the
S1 = 0.5 case, this value is 1.6 ms. The sluggishness of the
latter is due to the slower compensation rate of the duty cycle.
Moreover, it can be observed in Fig. 22(a) that the performance
for PI is approximately equal to SIFLC with S1 = 1.1. These
observations are in close agreement with the simulation results
shown in Fig. 19.
V. C ONCLUSION
This paper has described the FPGA implementation of the
SIFLC to control a boost converter without the use of an
external ADC. It was shown that the SIFLC with PWL control
surface has identical performance to the CFLC; therefore, the
latter can be replaced without significant degradation in the control performance. Due to the simplicity of the SIFLC algorithm,
its implementation requires only 460 logic gates and four IO
pins of the FPGA. The analog-to-digital conversion is achieved
by a combination of standard op-amp circuits and pulsewidth
control using the FPGA itself. Both the simulation and experiment indicate promising results. Compared to PI, the SIFLC
has superior performance for load and reference changes with
very small overshoot and fast settling time. For future work,
it would be interesting to investigate the possibility of using
different types of PWL slopes, in particular, the hysteresis-type
PWL function. Furthermore, since most power converters do
exhibit Teoplitz structure, the application of SIFLC method can
be extended to other converter topologies.
R EFERENCES

Fig. 22. Boost converter response for periodic change in the reference voltage
from 12.5 to 15 V, with 10- load. (a) PI controller. (b) SIFLC with S1 = 1.1.
(c) SIFLC with S1 = 0.5.

Fig. 21(a) and (b) shows the controller response for PI and
SILC, respectively, when subjected to a step load change. The
load was stepped from 10 to 5 at an output voltage of 15 V.
The specifications for the boost converter and the parameter
settings of the controller are the same as in simulation. For
SIFLC, the slope S1 is set to 0.5. As can be clearly seen in
Fig. 21(a) and (b), the transient response of SIFLC is superior to
PI. Although the fist voltage dip (immediately after the applied
step) is about the same for both, i.e., 4 V, the SIFLC does not
exhibit any overshoot. This observation is consistent with the
simulation shown in Fig. 18(a).

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Fazel Taeed was born in Mahabad, Kurdistan, Iran,

in 1981. He received the B.Sc. degree in biomedical
engineering from Sahand University of Technology,
Tabriz, Iran, in 2004 and the M.S. degree in electrical power engineering from Universiti Teknologi
Malaysia, Skudai, Malaysia, in 2010.
From 2004 to 2008, he was with the R&D Department, Pardis Engineering Company, Tehran, Iran,
as a Power Electronic Designer. His main research
interests include power electronic converters, control
techniques, and digital electronic applications in
power electronic.

Zainal Salam (M95) was born in Seremban,

Malaysia, in 1963. He received the B.Sc. degree
from the University of California, Los Angeles, in
1985, the M.E.E. degree from Universiti Teknologi
Malaysia (UTM), Kuala Lumpur, Malaysia, in
1989, and the Ph.D. degree from the University of
Birmingham, Birmingham, U.K., in 1997.
He has been a Lecturer with UTM for over 20
years. He is currently the Director of Inverter Quality
Control Center, UTM. His research interests include
all areas of power electronics, renewable energy, and
machine control.

Shahrin M. Ayob (M03) was born in Kuala

Lumpur, Malaysia, in 1979. He received the B.E.E.,
M.E.E., and Ph.D. degrees from the Universiti
Teknologi Malaysia (UTM), Kuala Lumpur, in 2000,
2003 and 2009, respectively.
He is currently with the Department of Energy
Conversion, Faculty of Electrical Engineering,
UTM, Skudai, Malaysia. His current interest of research is on the application of artificial intelligence
on power converters.