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A Triac needs a single fuse protection, which also simplifies the construction.
A Triac needs a single heat sink of slightly larger size whereas antiparallel thyristor pair
needs two heat sinks.
The Power MOSFET technology has mostly reached maturity and is the most popular device
for SMPS, lighting ballast type of application where high switching frequencies are desired
but operating voltages are low. Being a voltage fed, majority carrier device (resistive
behaviour) with a typically rectangular Safe Operating Area, it can be conveniently utilized.
Utilising shared manufacturing processes, comparative costs of MOSFETs are attractive. For
low frequency applications, where the currents drawn by the equivalent capacitances across
its terminals are small, it can also be driven directly by integrated circuits. These capacitances
are the main hindrance to operating the MOSFETS at speeds of several MHz. The resistive
characteristics of its main terminals permit easy paralleling externally also. At high current
low voltage applications the MOSFET offers best conduction voltage specifications as the
R
specification is current rating dependent. However, the inferior features of the
DS(ON)
inherent anti-parallel diode and its higher conduction losses at power frequencies and voltage
levels restrict its wider application.
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Part B
1. Explain the Construction & Working Principle of Power MOSFET
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shown in Fig 6.2 (b)) to form a complete device. The two n end layers labeled Source and
Drain are heavily doped to approximately the same level. The p type middle layer is termed
the body (or substrate) and has moderate doping level (2 to 3 orders of magnitude lower than
+
n regions on both sides). The n drain drift region has the lowest doping density. Thickness
of this region determines the breakdown voltage of the device. The gate terminal is placed
-
over the n and p type regions of the cell structure and is insulated from the semiconductor
body be a thin layer of silicon dioxide (also called the gate oxide). The source and the drain
region of all cells on a wafer are connected to the same metallic contacts to form the Source
and the Drain terminals of the complete device. Similarly all gate terminals are also
connected together. The source is constructed of many (thousands) small polygon shaped
areas that are surrounded by the gate regions. The geometric shape of the source regions, to
same extent, influences the ON state resistance of the MOSFET.
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As mentioned in the introduction section, Power MOSFET is a device that evolved from
MOS integrated circuit technology. The first attempts to develop high voltage MOSFETs
were by redesigning lateral MOSFET to increase their voltage blocking capacity. The
resulting technology was called lateral double deffused MOS (DMOS). However it was soon
realized that much larger breakdown voltage and current ratings could be achieved by
resorting to a vertically oriented structure. Since then, vertical DMOS (VDMOS) structure
has been adapted by virtually all manufacturers of Power MOSFET. A power MOSFET
using VDMOS technology has vertically oriented three layer structure of alternating p type
and n type semiconductors as shown in Fig 6.2 (a) which is the schematic representation of a
single MOSFET cell structure. A large number of such cells are connected in parallel (as
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The positive charge induced on the gate metallization repels the majority hole carriers from the
interface region between the gate oxide and the p type body. This exposes the negatively
charged acceptors and a depletion region is created.
Further increase in V causes the depletion layer to grow in thickness. At the same time the electric
GS
field at the oxide-silicon interface gets larger and begins to attract free electrons as shown in
Fig 6.4 (b). The immediate source of electron is electron-hole generation by thermal ionization.
The holes are repelled into the semiconductor bulk ahead of the depletion region. The extra
holes are neutralized by electrons from the source.
As V increases further the density of free electrons at the interface becomes equal to the free hole
GS
density in the bulk of the body region beyond the depletion layer. The layer of free electrons at
the interface is called the inversion layer and is shown in Fig 6.4 (c). The inversion layer has all
the properties of an n type semiconductor and is a conductive path or channel between the
drain and the source which permits flow of current between the drain and the source. Since
current conduction in this device takes place through an n- type channel created by the
electric field due to gate source voltage it is called Enhancement type n-channel MOSFET.
The value of V at which the inversion layer is considered to have formed is called the Gate
GS
GS
(th). As V
GS
gets some what thicker and more conductive, since the density of free electrons increases
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further with increase in V . The inversion layer screens the depletion layer adjacent to it
GS
2. Explain the Construction & Working Principle of Power TRIAC. Discuss its four
modes of operations
Fig. 4.12 (a) and (b) show the circuit symbol and schematic cross section of a triac
respective. As the Triac can conduct in both the directions the terms anode and cathode
are not used for Triacs. The three terminals are marked as MT (Main Terminal 1), MT
Since a Triac is a bidirectional device and can have its terminals at various combinations of positive
and negative voltages, there are four possible electrode potential combinations as given below
1. MT positive with respect to MT , G positive with respect to MT
2
The triggering sensitivity is highest with the combinations 1 and 3 and are generally used. However,
for bidirectional control and uniforms gate trigger mode sometimes trigger modes 2 and 3 are used.
Trigger mode 4 is usually averded. Fig 4.13 (a) and (b) explain the conduction mechanism of a triac
in trigger modes 1 & 3 respectively.
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(Main Terminal 2) and the gate by G. As shown in Fig 4.12 (b) the gate terminal is near MT
In trigger mode-1 the gate current flows mainly through the P N junction like an ordinary thyristor.
2
When the gate current has injected sufficient charge into P layer the triac starts conducting through
2
In the trigger mode-3 the gate current I forward biases the P P junction and a large number of
g
electrons are introduced in the P region by N . Finally the structure P N P N turns on completely.
2
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From a functional point of view a triac is similar to two thyristors connected in anti parallel.
st
rd
Therefore, it is expected that the V-I characteristics of Triac in the 1 and 3 quadrant of the V-I
plane will be similar to the forward characteristics of a thyristors. As shown in Fig. 4.14, with no
signal to the gate the triac will block both half cycle of the applied ac voltage provided its peak value
is lower than the break over voltage (V ) of the device. However, the turning on of the triac can be
BO
controlled by applying the gate trigger pulse at the desired instance. Mode-1 triggering is used in the
first quadrant where as Mode-3 triggering is used in the third quadrant. As such, most of the thyristor
characteristics apply to the triac (ie, latching and holding current). However, in a triac the two
conducting paths (from MT to MT or from MT to MT ) interact with each other in the structure of
2
The introduction of Power MOSFET was originally regarded as a major threat to the power
bipolar transistor. However, initial claims of infinite current gain for the power MOSFETs were
diluted by the need to design the gate drive circuit capable of supplying the charging and
discharging current of the device input capacitance. This is especially true in high frequency
circuits where the power MOSFET is particularly valuable due to its inherently high switching
speed. On the other hand, MOSFETs have a higher on state resistance per unit area and
consequently higher on state loss. This is particularly true for higher voltage devices (greater than
about 500 volts) which restricted the use of MOSFETs to low voltage high frequency circuits (eg.
SMPS).
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the triac. Therefore, the voltage, current and frequency ratings of triacs are considerably lower than
thyristors. At present triacs with voltage and current ratings of 1200V and 300A (rms) are available.
Triacs also have a larger on state voltage drop compared to a thyristor. Manufacturers usually specify
characteristics curves relating rms device current and maximum allowable case temperature as shown
in Fig 4.15. Curves relating the device dissipation and RMS on state current are also provided for
different conduction angles.
The i-v characteristics of an n channel IGBT is shown in Fig 7.4 (a). They appear qualitatively
similar to those of a logic level BJT except that the controlling parameter is not a base current but
the gate-emitter voltage.
When the gate emitter voltage is below the threshold voltage only a very small leakage current
flows though the device while the collector emitter voltage almost equals the supply voltage
(point C in Fig 7.4(a)). The device, under this condition is said to be operating in the cut off
region. The maximum forward voltage the device can withstand in this mode (marked V in Fig
CES
7.4 (a)) is determined by the avalanche break down voltage of the body drain p-n junction.
Unlike a BJT, however, this break down voltage is independent of the collector current as shown
in Fig 7.4(a). IGBTs of Non-punch through design can block a maximum reverse voltage (V )
RM
equal to V
CES
RM
is negligible (only a
few tens of volts) due the presence of the heavily doped n+ drain buffer layer.
As the gate emitter voltage increases beyond the threshold voltage the IGBT enters into the active
region of operation. In this mode, the collector current i is determined by the transfer
c
characteristics of the device as shown in Fig 7.4(b). This characteristic is qualitatively similar to
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that of a power MOSFET and is reasonably linear over most of the collector current range. The
ratio of i to (V v
) is called the forward transconductance (g ) of the device and is an
gE
gE(th)
fs
important parameter in the gate drive circuit design. The collector emitter voltage, on the other
hand, is determined by the external load line ABC as shown in Fig 7.4(a).
The switching waveforms of an IGBT is, in many respects, similar to that of a Power MOSFET.
This is expected, since the input stage of an IGBT is a MOSFET as shown in Fig 7.5(b). Also in
a modern IGBT a major portion of the total device current flows through the MOSFET.
Therefore, the switching voltage and current waveforms exhibit a strong similarity with those of
a MOSFET. However, the output p-n-p transistor does have a significant effect on the switching
characteristics of the device, particularly during turn off. Another important difference is in the
gate drive requirement. To avoid dynamic latch up, (to be discussed later) the gate emitter
voltage of an IGBT is maintained at a negative value when the device is off.
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As shown in Fig 4.1 (b) the primary crystal is of lightly doped n type on either side of which two p
type layers with doping levels higher by two orders of magnitude are grown. As in the case of power
-
diodes and transistors depletion layer spreads mainly into the lightly doped n region. The thickness
of this layer is therefore determined by the required blocking voltage of the device. However, due to
conductivity modulation by carriers from the heavily doped p regions on both side during ON
+
condition the ON state voltage drop is less. The outer n layers are formed with doping levels
+
higher then both the p type layers. The top p layer acls as the Anode terminal while the bottom n
layers acts as the Cathode. The Gate terminal connections are made to the bottom p layer.
As it will be shown later, that for better switching performance it is required to maximize the
peripheral contact area of the gate and the cathode regions. Therefore, the cathode regions are finely
distributed between gate contacts of the p type layer. An Involute structure for both the gate and
the cathode regions is a preferred design structure.
The circuit symbol in the left hand side inset defines the polarity conventions of the variables used in
this figure.
With ig = 0, V has to increase up to forward break over voltage V
before significant anode
AK
BRF
BRF
forward break over takes place and the voltage across the
thyristor drops to V (holding voltage). Beyond this point voltage across the thyristor (V ) remains
H
AK
almost constant at V (1-1.5v) while the anode current is determined by the external load.
H
The magnitude of gate current has a very strong effect on the value of the break over voltage as
shown in the figure. The right hand side figure in the inset shows a typical plot of the forward break
over voltage (V ) as a function of the gate current (I )
BRF
After Turn ON the thyristor is no more affected by the gate current. Hence, any current pulse (of
required magnitude) which is longer than the minimum needed for Turn ON is sufficient to effect
control. The minimum gate pulse width is decided by the external circuit and should be long enough
to allow the anode current to rise above the latching current (I ) level.
L
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The left hand side of Fig 4.3 shows the reverse i-v characteristics of the thyristor. Once the thyristor
is ON the only way to turn it OFF is by bringing the thyristor current below holding current (I ). The
H
gate terminal has no control over the turn OFF process. In ac circuits with resistive load this happens
automatically during negative zero crossing of the supply voltage. This is called natural
commutation or line commutation. However, in dc circuits some arrangement has to be made to
ensure this condition. This process is called forced commutation.
During reverse blocking if i = 0 then only reverse saturation current (I ) flows until the reverse
g
BRR
reverse voltage and current generates excessive heat and destroys the device. If i > 0 during reverse
g
bias condition the reverse saturation current rises as explained in the previous section. This can be
avoided by removing the gate current while the thyristor is reverse biased.
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Fig 4.10 shows the waveforms of the gate current (i ), anode current (i ) and anode cathode voltage
g
(V ) in an expanded time scale during Turn on. The reference circuit and the associated waveforms
AK
are shown in the inset. The total switching period being much smaller compared to the cycle time, i
and V
AK
As shown in Fig 4.10 there is a transition time t from forward off state to forward on state. This
ON
transition time is called the thyristor turn of time and can be divided into three separate intervals
namely, (i) delay time (t ) (ii) rise time (t ) and (iii) spread time (t ). These times are shown in Fig
d
instant the thyristor regains forward blocking capability. If forward voltage is applied across the
device during this period the thyristor turns on again.
During turn off time, excess minority carriers from all the four layers of the thyristor must be
removed. Accordingly t is divided in to two intervals, the reverse recovery time (t ) and the gate
q
rr
recovery time (t ). Fig 4.11 shows the variation of anode current and anode cathode voltage with
qr
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To arrive at the structure shown in Fig 2.3 (c) a lightly doped n epitaxial layer of specified
width (depending on the required break down voltage) and donor atom density (N ) is
dD
-3
dK
Finally the p-n junction is formed by defusing a heavily doped (N acceptor atoms.Cm ) p
aA
region into the epitaxial layer. This p type region acts as the anode.
-3
-3
Impurity atom densities in the heavily doped cathode (N .Cm ) and anode (N .Cm ) are
19
dk
-3
aA
dD
10
14
-3
Cm ). In a
low power diode this drift region is absent. The Implication of introducing this drift region in
a power diode is explained next.
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In the previous section it was shown how the introduction of a lightly doped drift region in the p-n
structure of a diode boosts its blocking voltage capacity. It may appear that this lightly doped drift
region will offer high resistance during forward conduction. However, the effective resistance of this
region in the ON state is much less than the apparent ohmic resistance calculated on the basis of the
geometric size and the thermal equilibrium carrier densities. This is due to substantial injection of
+
excess carriers from both the p and the n regions in the drift region as explained next.
+
As the metallurgical p n junction becomes forward biased there will be injection of excess p type
-
carrier into the n side. At low level of injections (i.e << n ) all excess p type carriers recombine
p
no
with n type carriers in the n drift region. However at high level of injection (i.e large forward current
-
density) the excess p type carrier density distribution reaches the n n junction and attracts electron
+
from the n cathode. This leads to electron injection into the drift region across the n n junction with
carrier densities = . This mechanism is called double injection
n
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Power Diodes take finite time to make transition from reverse bias to forward bias condition (switch
ON) and vice versa (switch OFF).
Behavior of the diode current and voltage during these switching periods are important due to the
following reasons.
Severe over voltage / over current may be caused by a diode switching at different points in the
circuit using the diode.
Voltage and current exist simultaneously during switching operation of a diode. Therefore,
every switching of the diode is associated with some energy loss. At high switching
frequency this may contribute significantly to the overall power loss in the diode.
It is observed that the forward diode voltage during turn ON may transiently reach a significantly
higher value V compared to the steady slate voltage drop at the steady current I .
fr
In some power converter circuits (e.g voltage source inverter) where a free wheeling diode is used
across an asymmetrical blocking power switch (i.e GTO) this transient over voltage may be high
enough to destroy the main power switch.
V (called forward recovery voltage) is given as a function of the forward di/dt in the
fr
manufacturers data sheet. Typical values lie within the range of 10-30V. Forward recovery
time (t ) is typically within 10 us.
fr
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voltage (V ) in an expanded time scale during Turn on. The reference circuit and the
AK
associated waveforms are shown in the inset. The total switching period being much smaller
compared to the cycle time, i and V before and after switching will appear flat.
A
AK
As shown in Fig 4.10 there is a transition time t from forward off state to forward on state.
ON
This transition time is called the thyristor turn of time and can be divided into three separate
intervals namely, (i) delay time (t ) (ii) rise time (t ) and (iii) spread time (t ). These times are
d
portion of the cathode which is closest to the gate. This conducting area starts spreading at a finite
speed until the entire cathode region becomes conductive. Time taken by this process constitute the
turn on delay time of a thyristor. It is measured from the instant of application of the gate current to
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the instant when the anode current rises to 10% of its final value (or V
value). Typical value of t is a few micro seconds.
AK
Rise time (tr): For a resistive load, rise time is the time taken by the anode current to rise from
10% of its final value to 90% of its final value. At the same time the voltage V falls from 90% of
AK
its initial value to 10% of its initial value. However, current rise and voltage fall characteristics are
strongly influenced by the type of the load. For inductive load the voltage falls faster than the current.
While for a capacitive load V falls rapidly in the beginning. However, as the current increases, rate
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Industrial Electronics Question Bank with Answers
Unit 2 Converters
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For any current to flow in the load at least one device from the top group (T , T , T ) and one from
1
the bottom group (T , T , T ) must conduct. It can be argued as in the case of an uncontrolled
2
converter only one device from these two groups will conduct.
Then from symmetry consideration it can be argued that each thyristor conducts for 120 of the input
cycle. Now the thyristors are fired in the sequence T T T T T T T with 60
1
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interval between each firing. Therefore thyristors on the same phase leg are fired at an interval of
180 and hence can not conduct simultaneously. This leaves only six possible conduction mode for
the converter in the continuous conduction mode of operation. These are T T , T T , T T T T ,
1 2
2 3
3 4,
4 5
T T , T T . Each conduction mode is of 60 duration and appears in the sequence mentioned. The
5 6
6 1
conduction table of Fig. 13.1 (b) shows voltage across different devices and the dc output voltage for
each conduction interval. The phasor diagram of the line voltages appear in Fig. 13.1 (c). Each of
these line voltages can be associated with the firing of a thyristor with the help of the conduction
table-1. For example the thyristor T is fired at the end of T T conduction interval. During this period
5 6
ac
v . Similar observation can be made about other thyristors. The phasor diagram of Fig. 13.1 (c) also
ac
confirms that all the thyristors are fired in the correct sequence with 60 interval between each firing.
Fig. 13.2 shows the waveforms of different variables (shown in Fig. 13.1 (a)). To arrive at the
waveforms it is necessary to draw the conduction diagram which shows the interval of conduction for
each thyristor and can be drawn with the help of the phasor diagram of fig. 13.1 (c). If the converter
firing angle is each thyristor is fired angle after the positive going zero crossing of the line
voltage with which its firing is associated. Once the conduction diagram is drawn all other voltage
waveforms can be drawn from the line voltage waveforms and from the conduction table of fig. 13.1
(b). Similarly line currents can be drawn from the output current and the conduction diagram. It is
clear from the waveforms that output voltage and current waveforms are periodic over one sixth of
the input cycle. Therefore this converter is also called the six pulse converter. The input current on
rd
th
the other hand contains only odds harmonics of the input frequency other than the triplex (3 , 9 etc.)
harmonics. The next section will analyze the operation of this converter in more details.
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the voltage across T was v . Therefore T is fired angle after the positive going zero crossing of
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Write the sequence and draw the output in graph sheet - refer class notes
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Fig 10.3 (a) shows the circuit diagram of a single phase fully controlled bridge converter. It is one of
the most popular converter circuits and is widely used in the speed control of separately excited dc
machines. Indeed, the RLE load shown in this figure may represent the electrical equivalent circuit
of a separately excited dc motor.
The single phase fully controlled bridge converter is obtained by replacing all the diode of the
corresponding uncontrolled converter by thyristors. Thyristors T and T are fired together while T
1
and T are fired 180 after T and T . From the circuit diagram of Fig 10.3(a) it is clear that for any
4
load current to flow at least one thyristor from the top group (T , T ) and one thyristor from the
1
bottom group (T , T ) must conduct. It can also be argued that neither T T nor T T can conduct
2
1 3
2 4
simultaneously. For example whenever T and T are in the forward blocking state and a gate pulse is
3
applied to them, they turn ON and at the same time a negative voltage is applied across T and T
1
For the same reason T T or T T can not conduct simultaneously. Therefore, the only
1 4
2 3
possible conduction modes when the current i can flow are T T and T T . Of coarse it is possible
0
1 2
3 4
that at a given moment none of the thyristors conduct. This situation will typically occur when the
load current becomes zero in between the firings of T T and T T . Once the load current becomes
1 2
3 4
zero all thyristors remain off. In this mode the load current remains zero. Consequently the converter
is said to be operating in the discontinuous conduction mode.
Fig 10.3(b) shows the voltage across different devices and the dc output voltage during each
of these conduction modes. It is to be noted that whenever T and T conducts, the voltage across T
1
and T becomes v . Therefore T and T can be fired only when v is negative i.e, over the negative
4
half cycle of the input supply voltage. Similarly T and T can be fired only over the positive half
1
cycle of the input supply. The voltage across the devices when none of the thyristors conduct
depends on the off state impedance of each device. The values listed in Fig 10.3 (b) assume identical
devices.
Under normal operating condition of the converter the load current may or may not remain zero over
some interval of the input voltage cycle. If i is always greater than zero then the converter is said to
0
be operating in the continuous conduction mode. In this mode of operation of the converter T T and
1 2
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Although Equations 13.30 ensures that the dc voltages produced by these converters are
equal the output voltages do not match on an instantaneous basis. Therefore to avoid a direct
short circuit between two different supply lines the two converters must never be gated
simultaneously. Converter-I receives gate pulses when the load current is positive. Gate
pulses to converter-II are blocked at that time. For negative load current converter-II
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thyristors are fired while converter-I gate pulses are blocked. Thus there is no circulating
current flowing through the converters and therefore it is called the non-circulating current
type dual converter. It requires precise sensing of the zero crossing of the output current
which may pose a problem particularly at light load due to possible discontinuous
conduction. To overcome this problem an interphase reactor may be incorporated between
the two converters. With the interphase reactor in place both the converters can be gated
simultaneously with = . The resulting converter is called the circulating current type
2
4. Explain the operation of 3 phase bridge converter and derive the output voltage.
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dual converter.
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operates in its inverting region, and under this condition, the load is regenerating power back into the
cyclo-converter output terminals, and hence, into the ac system at the input side. These two are
illustrative cases only. Any other case, say capacitive load, with the displacement angle as leading,
the operation changes with inverting region in the first period of the half-cycle as per displacement
angle, and the latter period operating in rectifying region. This is not shown in Fig. 29.2, which can
be studied from a standard text book.
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of the load (current) is (Fig. 29.2a). In this case, each converter carries the load current only,
when it operates in its rectifying region, and it remains idle throughout the whole period in which
its terminal voltage is in the inverting region of operation. In Fig. 29.2b, the displacement angle
of the load is lagging. During the first period of each half-cycle of load current, the associated
converter operates in its rectifying region, and delivers power to the load. During the latter
period in the half-cycle, the associated converter
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The regulators in Fig 26.1 (a), (b) and (c) perform quite similarly. They are called Phase Angle
Controlled (PAC) AC-AC converters or AC-AC choppers. The TRIAC based converter may be
considered as the basic topology. Being bi-directionally conducting devices, they act on both
polarities of the applied voltage. However, reapplieddvdt their ratings being poor, they tend to turn-on in
the opposite direction just subsequent to their turn-off with an inductive load. The 'Alternistor' was
developed with improved features but was not popular. The TRIAC is common only at the low
power ranges. The (a) and (b) options are improvements on (c) mostly regarding current handling
and turn-off-able current rating.
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A transistorised AC-AC regulator is a PWM regulator similar to the DC-DC converters. It also
requires a freewheeling path across the inductive load, which has also got to be bi-directional.
Consequently, only controlled freewheeling devices can be used.
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Unit Test 3 Industrial Electronics Question Bank
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2 Marks
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Part B
1. Explain the working of 3 phase full bridge inverter for 180 conduction and draw the
relevant output waveforms in the graph sheet.
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3. Explain the working of step up and step down DC chopper with TRC and CLC control.
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5.
a.
b.
c.
d.
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Multiple-Pulse-Width Modulation
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Sinusoidal Pulse-Width
Modulation
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Vo Vs (
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Modified Sinusoidal Pulse-Width
Modulation
This utilizes a different method of modulation.
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6. Explain the working of 3 phase full bridge inverter for 120 conduction and draw the
relevant output waveforms in the graph sheet.
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Mention the advantages of a converter fed indication motor over a line fed motor.
A converter fed induction motor has the following advantages over line fed motor.
a. Smooth start up is guaranteed by variable frequency starting from a low value.
b. Soft starting and acceleration at constant current and torque are possible.
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c. The network is no longer subjected to a high switching surge current as with the
direct switch On of cage induction motor, and as such, special starting equipment can
be omitted even at high ratings.
d. High moments of inertia can be accelerated without need to over dimension the
motor.
e. The converter acts as a decoupling device. Therefore feedback from the motor to the
point of short circuit does not take place, when line short circuits occur. The short
circuit rating on the basis of which the switchgear has to be over dimensioned is
therefore low, permitting a saving to be made.
9. How is the speed control by variation of slip frequency obtained?
Speed control by variation of slip frequency is obtained by the following ways.
a. Stator voltage control using a three-phase voltage controller.
b. Rotor resistance control using a chopper controlled resistance in the rotor circuit.
c. Using a converter cascade in the rotor circuit to recover slip energy.
d. Using a cycloconverter in the rotor circuit.
10. What is meant by V/f control?
When the frequency is reduced, the input voltage must be reduced proportionally so as to
maintain constant flux. Otherwise the core will get saturated resulting in excessive iron loss
and magnetizing current. This type of induction motor behavior is similar to the working
of dc series motors.
11. What is slip controlled drive?
When the slip is used as a controlled quantity to maintain the flux constant in the motor
the drive is called slip conrolled drive. By making the slip negative (i.e., decreasing the
output frequency of the inverter) The machine may be made to operate as a generator and the
energy of the rotating parts fed back to the mains by an additional line side converter or
dissipated in a resistance for dynamic barking. By keeping the slip frequency constant,
braking at constant torque and current can be achieved. Thus braking is also fast.
12. How is the D.C. dynamic braking is obtained?
D.C. dynamic barking is obtained when the stator of an induction motor running at a
speed is connected to a D.C. supply. D.C. current flowing though the stator produces a
stationary magnetic field. Motion of rotor in this field induces voltage in the rotor winding.
Machine, therefore, works as a generator. Generated energy is dissipated in the rotor circuit
resistance, thus giving dynamic barking.
13. What is meant by regenerative braking?
Regenerative braking occurs when the motor speed exceeds the synchronous
speed.
In this case,the induction motor would run as the induction generator is converting the
mechanical power into electrical power, which is delivered back to the electrical system. This
method of braking is known as regenerative braking.
14. Why the drive motor must be slightly over dimensioned in slip energy recovery
scheme?
The losses in the circuits cause a slight reduction in efficiency. This affiance is further
affected by additional losses due to the non-sinusoidal nature of the rotor current. Therefore
the drive motor must be slightly over dimensioned. The motor used must have a rating 20%
higher than the required power.
15. How is super synchronous speed achieved?
Super synchronous speed can be achieved if the power is fed to the rotor from A.C.
mains. This can be made possible by replacing the converter cascade by a cycloconverter. A
cycloconverter allows power flow in either direction making the static sherbiuss drive
operate at both sub and super synchronous speeds.
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Part B
1. Explain the operation of a single phase fully controlled converter fed separately excited DC
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motor with neat waveforms and derive the speed torque characteristics.
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2. Deduce an expression relating speed and torque of a single phase full converter fed
separately excited DC motor drive operating in the continuous current mode and
discontinuous modes
.same answer of the previous question
3. Explain the motoring and braking operation of three phase fully controlled rectifier control of
DC separately excited motor with aid of diagrams and waveforms. Also obtain the expression
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4. Explain in detail the working of a multi quadrant control of chopper fed DC series motor
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5. With necessary diagram, explain the theoretical principles of stator voltage control
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6. Derive an expression for the torque of an inverter fed three phase induction motor when it is
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operated with V/F control. Show that the maximum torque remains unaltered in this scheme.
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Low speed.
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Unit V Applications of Inverters.
2. Define Redundancy.
It means the use of more power conditioners that it is required for the critical loads. In
that case, it one of the conditioners fails it can be isolated and the remaining conditioners
can serve the critical loads without any disturbance.
3. What are the applications of UPS ?
Communication systems, Medical Equipments, Process Industires continuous Monitoring
of processes, Personal Computers.
4. What are the functions of a power supply?
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Part A
1. What are the advantages of / Protection available in On-line UPS ?
It can protect the critical load against surges, line noise, spikes line noise, frequency and
voltage variation, brownout outages. All these protections are not available in the off-line
UPS System.
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What do you mean by SMPS?
7.
8.
10.
Asynchronous (ripple) counter changing state bits are used as clocks to subsequent
state flip-flops
Synchronous counter all state bits change under control of a single clock
Decade counter counts through ten states per stage
Up/down counter counts both up and down, under command of a control input
Ring counter formed by a shift register with feedback connection in a ring
Johnson counter a twisted ring counter
Cascaded counter
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6.
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Part B
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2. Explain the working of a linear voltage regulator with its basic block diagram.
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