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1. Introduction
A switching overvoltage due to a circuit breaker
operation has been one of dominant factors to determine the
insulation level of a substation equipment. Thus, reduction
of the overvoltage is a significant subject to reduce the
insulation level and to optimize insulation co-ordination of
the substation and a transmission line. A circuit breaker
with a closing and opening resistor is widely adopted to
reduce the switching overvoltage. The reduction is, in
general, expected to be 2.0pu or less, although it can be
farther reduced in theory by adopting a resistance same as
the surge impedance of the transmission line. The limit
comes from the thermal capacity of the resistor during fault
current interruption.
The paper proposes a circuit breaker with multiple
resistors. As is clear from a parallel resistance circuit, each
resistance of the parallel ones is greater than the total
resistance of the parallel circuit. Thus, an optimum
resistance to reduce the switching overvoltage is easily
achieved by a parallel combination of the resistors, and at
the same time a thermal requirement of the resistors is
reduced because of the greater resistance and less insertion
time to a circuit. The principle of the multiple resistor
circuit breaker follows an ideal circuit breaker of which the
resistance starts from infinite and ends up zero, similar to a
semiconductor circuit breaker.
The paper caries out switching surge simulations on
transmission lines from 77kV to 1100kV with various line
length both for closing and fault clearing surges by using
EMTP simulations[1]. Based on the simulation results,
various conditions of multiple resistors and switching
instance are investigated to reduce the switching
overvoltages to a desired level, and the effectiveness of the
proposed circuit breaker is discussed.
881
RCB
S1
line
S2
source
RCB
V1
Z0
1
RCB
V2
Z0
clearing
1.5
1
closing
0.5
0
4
6
RCB /Z0
Fig. 3 Switching overvoltage-RCB characteristic
0
1
surge voltage[pu]
1
0
0
time[ms]
CB
cct. 1
phase a
cct. 2
x
eb
CB
cct. 1
phase b
cct. 2
ec
CB
cct. 1
phase c
cct. 2
Fig. 6 A model system
GW1
GW2
22.4m
PWa
13.5m
11.8m
11.8m
PWb
PWc
15.9m
16.7m
17.5m
50cm
PWc
PWb
PWa
55.0m
(a) 500kV
GW1
GW2
20.8m
PWa
10.2m
R2
12.7m
line
12.7m
PWb
PWc
19.0m
19.9m
20.8m
50cm
PWc
PWb
PWa
27.2m
Rn
S0
(b) 1100kV
882
F
XF
R1
ea
S2
time[ms]
( 6)
S1
Sn
(a) NO resistor
= 1 Z0
source
time[ms]
( 5)
R2 = 5Z 0 4
(4)
1 R
n
t = tn : Sn closed, RCB = 1 Ri
i =1
3
surge voltage[pu]
t = t2 : S2 closed, RCB = (1 R1 + 1 R2 )1
3
surge voltage[pu]
77kV
500kV, Fig. 7(a)
1100kV, Fig. 7(b)
30, 60, 100, 150
0 : infinite bus
50, 100
simultaneous
a =b=c
sequential
a =0, c =/3, b=2/3
sequential
a =0, b=2/3, c =4/3,
10k, 5k, 2k, 750, 500
2, 5, 10
2.5
2.5
overvoltage[pu]
overvoltage[pu]
1.5
1
0.5
0
2
1.5
1
0.5
3
4
case No.
3
4
case No.
phase a
phase b
phase c
(a) 500kV line with x=100km
(b) 1100kV line with x=150km
Fig. 8 Maximum closing overvoltage at the receiving vs CB condition
883
2
voltage[pu]
case
no resistor
SCB
MCB
-1
20
40
60
time[ms]
node F
2.168
1.138
-1.123
80
100
80
100
80
100
voltage[pu]
2
1
0
-1
-2
0
20
40
60
time[ms]
(b) SCB
voltage[pu]
2
1
0
-1
-2
0
20
40
60
time[ms]
(C) MCB
Fig. 9 Simulation results of fault clearing and reclosing surges at the fault
position on phase a of cct. 2
5. References
[1] W. Scott-Meyer : ATP Rule Book, B.P.A., Portland, April 1982.
[2] A. Ametani : Distributed-Parameter Line Theory, Corona Pub. Co.,
Tokyo, Feb. 1990.
[3] CIGRE WG13-05 : The calculation of switching surges, Electra,
No.32, 1974 and No.62, 1979.
[4] Electrical Engineering Handbook, IEE of Japan, Tokyo.
[5] JEC-102-1994 : High voltage testing method, IEE of Japan, 1994.
phase a [pu]
case
no resistor
SCB
MCB
-2
884
thermal
[MJ]
?
12.7
8.4
phase c [pu]
node F
-1.655
1.057
-1.029
node R
1.432
-1.050
1.033