IDT74ALVCH16345

3.3V CMOS REGISTERED ADDRESS LINE DRIVER WITH 3-STATE OUTPUTS

INDUSTRIAL TEMPERATURE RANGE

3.3V CMOS REGISTERED

ADDRESS LINE DRIVER
WITH 3-STATE OUTPUTS
AND BUS-HOLD
FEATURES:

DESCRIPTION:

0.5 MICRON CMOS Technology

Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V 0.2V
W typ. static)
CMOS power levels (0.4
Rail-to-Rail output swing for increased noise margin
Available in SSOP, TSSOP, and TVSOP packages

This registered address line driver is built using advanced dual metal CMOS
technology. The ALVCH16345 is configured with banks of four drivers, each
to be used in high speed synchronous memory applications.
The ALVCH16345 is ideal for driving memory modules in systems where
multiple memory modules are used. One each of the four output banks drives
a different module; modules can be added or removed without affecting the signal
integrity of the other modules in the system. Dual clock enables (CEx) allow use
of the device in high speed memory interleaving applications where the clock
can be alternately enabled and disabled, allowing the address to be held for
additional cycles during memory access.
The ALVCH16345 has been designed with a 24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16345 has bus-hold which retains the inputs last state
whenever the input goes to a high impedance. This prevents floating inputs and
eliminates the need for pull-up/down resistors.

DRIVE FEATURES:
High Output Drivers: 24mA
Suitable for heavy loads

APPLICATIONS:

IDT74ALVCH16345

3.3V high speed systems

3.3V and lower voltage computing systems
High speed synchronous DRAM modules
PC motherboards

FUNCTIONAL BLOCK DIAGRAM

CE 1
OE

CE 2

1Q 1

CE
D1

56

29

1Q 5

CE
D5

36

4Q 1

1Q 2

CE
D2

14

4Q 5

1Q 6

CE

D6

42

4Q 2

1Q 3

CE
D3

15

4Q 6

1Q 7

CE

D7

43

4Q 3

1Q 4

CE
D4

21

4Q 7

D8

D
4Q 4

CLK

1Q 8

CE
49

D
4Q 8

28

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE

APRIL 1999
1

1999 Integrated Device Technology, Inc.

DSC-4734/1

IDT74ALVCH16345
3.3V CMOS REGISTERED ADDRESS LINE DRIVER WITH 3-STATE OUTPUTS

INDUSTRIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS(1)

PIN CONFIGURATION

CE1

56

CE2

1Q1

55

1Q8

2Q1

54

2Q8

GND

53

GND

3Q1

52

3Q8

Symbol

Description

VTERM(2)

Max

Unit

Terminal Voltage with Respect to GND

0.5 to +4.6

VTERM(3)

Terminal Voltage with Respect to GND

0.5 to VCC+0.5

TSTG

Storage Temperature

65 to +150

50 to +50

mA

50

mA

IOUT

DC Output Current

IIK

Continuous Clamp Current,

VI < 0 or VI > VCC

IOK

Continuous Clamp Current, VO < 0

50

mA

ICC
ISS

Continuous Current through each

VCC or GND

100

mA

4Q1

51

4Q8

VCC

50

VCC

D1

49

D8

1Q2

48

1Q7

2Q2

10

47

2Q7

GND

11

46

GND

3Q2

12

45

3Q7

4Q2

13

44

4Q7

D2

14

43

D7

D3

15

42

D6

1Q3

16

41

1Q6

Symbol

Conditions

Typ.

Max.

2Q3

17

40

2Q6

CIN

Input Capacitance

VIN = 0V

pF

COUT

Output Capacitance

VOUT = 0V

pF

CI/O

I/O Port Capacitance

VIN = 0V

pF

GND

18

39

GND

3Q3

19

38

3Q6

4Q3

20

37

4Q6

D4

21

36

D5

VCC

22

35

VCC

1Q4

23

34

1Q5

2Q4

24

33

2Q5

GND

25

32

GND

3Q4

26

31

3Q5

4Q4

27

30

CLK

28

29

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.

CAPACITANCE (TA = +25C, F = 1.0MHz)

Unit

NOTE:
1. As applicable to the device type.

FUNCTION TABLE(1)
Inputs

Output

CEx

CLK

OE

Dx

xQx

4Q5

B2

OE

B2

SSOP/ TSSOP/ TVSOP

TOP VIEW

NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Dont Care
Z = High-Impedance
= LOW-to-HIGH Transition
2. Output level before the indicated steady-state input conditions were established.

PIN DESCRIPTION
Pin Names

Parameter(1)

Description

OE

3-State Output Enable Inputs (Active LOW)

Dx

Data Inputs(1)

xQx

3-State Data Outputs

CLK

Clock Input

CEx

Clock Enable Inputs (Active LOW)

NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.

IDT74ALVCH16345
3.3V CMOS REGISTERED ADDRESS LINE DRIVER WITH 3-STATE OUTPUTS

INDUSTRIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 40C to +85C
Symbol
VIH
VIL

Min.

Typ.(1)

Max.

Unit

VCC = 2.3V to 2.7V

1.7

VCC = 2.7V to 3.6V

VCC = 2.3V to 2.7V

0.7

VCC = 2.7V to 3.6V

0.8

Parameter
Input HIGH Voltage Level
Input LOW Voltage Level

Test Conditions

IIH

Input HIGH Current

VCC = 3.6V

VI = VCC

IIL

Input LOW Current

VCC = 3.6V

VI = GND

IOZH

High Impedance Output Current

VCC = 3.6V

VO = VCC

10

IOZL

(3-State Output pins)

VO = GND

10

VIK

Clamp Diode Voltage

VCC = 2.3V, IIN = 18mA

0.7

1.2

VH
ICCL
ICCH
ICCZ
ICC

Input Hysteresis
Quiescent Power Supply Current

VCC = 3.3V
VCC = 3.6V
VIN = GND or VCC

100
0.1

40

mV
A

Quiescent Power Supply Current

Variation

One input at VCC - 0.6V, other inputs at VCC or GND

750

Min.

Typ.(2)

Max.

Unit

75

VI = 0.8V

75

VI = 1.7V

45

45

500

NOTE:
1. Typical values are at VCC = 3.3V, +25C ambient.

BUS-HOLD CHARACTERISTICS
Symbol
IBHH

Parameter(1)

Test Conditions

Bus-Hold Input Sustain Current

VCC = 3V

Bus-Hold Input Sustain Current

VCC = 2.3V

Bus-Hold Input Overdrive Current

VCC = 3.6V

VI = 2V

IBHL
IBHH
IBHL
IBHHO

VI = 0.7V
VI = 0 to 3.6V

IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25C ambient.

A
A

IDT74ALVCH16345
3.3V CMOS REGISTERED ADDRESS LINE DRIVER WITH 3-STATE OUTPUTS

INDUSTRIAL TEMPERATURE RANGE

OUTPUT DRIVE CHARACTERISTICS

Symbol
VOH

Test Conditions(1)

Parameter
Output HIGH Voltage

Min.

Max.

Unit

VCC 0.2

IOH = 6mA

IOH = 12mA

1.7

2.2

VCC = 2.3V to 3.6V

IOH = 0.1mA

VCC = 2.3V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
VOL

Output LOW Voltage

2.4

VCC = 3V

IOH = 24mA

VCC = 2.3V to 3.6V

IOL = 0.1mA

0.2

VCC = 2.3V

IOL = 6mA

0.4

IOL = 12mA

0.7

VCC = 2.7V

IOL = 12mA

0.4

VCC = 3V

IOL = 24mA

0.55

NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = 40C to + 85C.

OPERATING CHARACTERISTICS, TA = 25C

Symbol

Parameter

CPD

Power Dissipation Capacitance Outputs enabled

CPD

Power Dissipation Capacitance Outputs disabled

Test Conditions

VCC = 2.5V 0.2V

VCC = 3.3V 0.3V

Typical

Typical

Unit

CL = 0pF, f = 10Mhz

pF

SWITCHING CHARACTERISTICS(1)
VCC = 2.5V 0.2V
Symbol

Parameter

fMAX

VCC = 2.7V

VCC = 3.3V 0.3V

Min.

Max.

Min.

Max.

Min.

Max.

Unit

150

150

150

ns

1.5

5.4

1.5

4.4

1.5

ns

1.5

5.2

1.5

5.1

1.5

4.5

ns

1.5

5.5

1.5

4.5

1.5

5.2

ns

tPLH

Propagation Delay

tPHL

CLK to xQx

tPZH

Output Enable Time

tPZL

OE to xQx

tPHZ

Output Disable Time

tPLZ

OE to xQx

tSU

Set-up Time, CEx to CLK, HIGH or LOW

1.5

1.5

1.5

ns

tSU

Set-up Time, Dx to CLK, HIGH or LOW

1.5

1.5

1.5

ns

tH

Hold Time, CEx to CLK, HIGH or LOW

0.5

0.5

0.5

ns

tH

Hold Time, Dx to CLK, HIGH or LOW

0.5

0.5

0.5

ns

tW

Pulse Width, CLK HIGH or LOW

ns

tSK(o)

Output Skew(2)

500

ps

tSK(b)

Output Skew(2)

350

ps

NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = 40C to + 85C.
2 Skew between any two outputs of the same package and switching in the same direction. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. For tSK(b) OUTPUT1
and OUTPUT2 are in the same bank.

IDT74ALVCH16345
3.3V CMOS REGISTERED ADDRESS LINE DRIVER WITH 3-STATE OUTPUTS

INDUSTRIAL TEMPERATURE RANGE

TEST CIRCUITS AND WAVEFORMS

TEST CONDITIONS
VCC(1)= 3.3V0.3V VCC(1)= 2.7V

Symbol

VCC(2)= 2.5V0.2V

Unit

VLOAD

2 x Vcc

VIH

2.7

2.7

Vcc

VT

1.5

1.5

Vcc / 2

VLZ

300

300

150

mV

VHZ

300

300

150

mV

CL

50

50

30

pF

(1, 2)

tPHL

V IH
VT
0V
ALVC Link

DISABLE

ENABLE
CONTROL
INPUT

GND

tPZL

D.U.T.

OUTPUT
SWITCH
NORMALLY
CLOSED
LOW
tPZH
OUTPUT
SWITCH
NORMALLY
OPEN
HIGH

500

RT

t PLH

CL
ALVC Link

Test Circuit for All Outputs

V OH
VT
V OL

Propagation Delay

V OUT

Pulse
Generator

t PHL

OPPOSITE PHASE
INPUT TRANSITION

Open
500

tPLH
OUTPUT

V LOAD

V CC

V IN

V IH
VT
0V

SAME PHASE
INPUT TRANSITION

tPLZ

V IH
VT
0V

V LOAD/2

V LOAD/2

VT

V LZ
V OL

tPHZ
VT

V OH
V HZ

0V

0V
ALVC Link

DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Enable and Disable Times

NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
V IH
DATA
VT
INPUT
0V
tSU
tH
V IH
TIMING
VT
INPUT
0V
tREM
V IH
ASYNCHRONOUS
VT
CONTROL
0V
V IH
SYNCHRONOUS
VT
CONTROL
tSU
0V
tH

NOTES:
1. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.
2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2ns; tR 2ns.

SWITCH POSITION
Test

Switch

Open Drain
Disable Low
Enable Low

VLOAD

Disable High
Enable High

GND

All Other Tests

Open

ALVC Link

Set-up, Hold, and Release Times

V IH
INPUT

VT
0V

tPHL1

tPLH1

V OH
OUTPUT 1

tSK (x)

LOW-HIGH-LOW
PULSE

VT
V OL

tSK (x)

tW

V OH
VT
V OL

OUTPUT 2

VT

HIGH-LOW-HIGH
PULSE

VT
ALVC Link

tPLH2

tPHL2

Pulse Width

tSK (x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

Output Skew - tSK(X)

ALVC Link

NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74ALVCH16345
3.3V CMOS REGISTERED ADDRESS LINE DRIVER WITH 3-STATE OUTPUTS

INDUSTRIAL TEMPERATURE RANGE

ORDERING INFORMATION
IDT
ALVC X
XX
Bus-Hold
Temp. Range

XXX
Family

XX
XXX
Device Type Package

CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054

PV
PA
PF

Shrink Small Outline Package

Thin Shrink Small Outline Package
Thin Very Small Outline Package

345

Registered Address Line Driver with 3-State Outputs

16

Double-Density, 24mA

Bus-Hold

74

40C to +85C

for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com

for Tech Support:

logichelp@idt.com
(408) 654-6459