KLU/ECE/2014-15/ODD/Teaching-Learning/FORM-2D(P.G.

- P)
ECE5183 HDL PROGRAMMING AND EDA TOOLS LABORATORY (2 Credits)

KALASALINGAM UNIVERSITY
(Kalasalingam Academy of Research and Education)
Krishnankoil

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

COURSE INFORMATION SHEET

ECE5183 HDL PROGRAMMING AND EDA TOOLS LABORATORY (2 Credits)
1. COURSE DETAILS
REVISION DATE:

REVISION: 2014-15 / Odd Semester

BRANCH/YEAR/ M.Tech. E.C.E./ I / I / A

SEMESTER/SECTION(S) :
REQUIRED/ELECTIVE :
COURSE SCHEDULE :

COURSE DESCRIPTION :

REQUIRED
Practical 1 Laboratory session per week, 150 minutes each
To familiarise the student with basics of VLSI in the form of
understanding the Verilog HDL language for the programming
point of view and SPICE tool for the synthesis of different
electronic circuits.
To familiarise the students with
1. Describing, designing, and verifying digital hardware
using the VERILOG language.
2. Understanding and applying HDL and FPGA technologies
and tools.
3. The use of SPICE, a Simulation Program with Integrated
Circuit Emphasis, since that it is the major Electronic
circuit designers computer aided design tool.
4. Writing of technical reports

COURSE OBJECTIVES :

At the end of the course, the students will be able to

COURSE OUTCOMES :

1. Write Verilog code that is synthesizable, i.e., code that can

be translated into hardware.
2. Implement Verilog code into FPGA circuits.
3. Use SPICE tools to design circuits and systems and
analyze their performance.
4. Check timing and understanding how proper design can
improve performance (speed, power, area).
5. Document experiments using an industry recognized
report format.

ECE Department, Kalasalingam University

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KLU/ECE/2014-15/ODD/Teaching-Learning/FORM-2D(P.G. - P)
ECE5183 HDL PROGRAMMING AND EDA TOOLS LABORATORY (2 Credits)
2. GRADING POLICY(As per University Regulations)
Model Exam and Laboratory Sessions (Internal) 50%
50%
End Semester Practical Session

3. COURSE PLAN
SL.
NO.
1. .
2.
3.
4.
5.
6.
7.
8.

9.
10.

EXPERIMENT NAME
Study of FPGA and tools
Design of Combinational and Sequential
Circuits using HDL
Synthesis of designed circuits on FPGA
Study of SPICE,
Diode and MOS transistor circuits
Basic Logic Gates using SPICE
Current Source/Mirrors, Differential
Amplifier using SPICE
Op-Amp/RC Coupled CE Amplifier design
using SPICE
Model Lab
CMOS Full Adder Design and Simulation
using SPICE
(Additional Experiment Beyond Syllabus)
Mini Project (Analog or Digital Design)

# OF HOURS
3

CUMULATIVE HOURS
3

15

18

21

27

30

33

36

4. COURSE INSTRUCTOR(S):
Prepared By

(Course Coordinator)

Approved By

(Head of the Department)

ECE Department, Kalasalingam University

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