Escolar Documentos
Profissional Documentos
Cultura Documentos
Synplicity, Inc.
935 Stewart Drive
Sunnyvale, CA 94085
408.215.6000 direct
408.990.0290 fax
www.synplicity.com
Preface
Preface
Disclaimer of Warranty
Synplicity, Inc. makes no representations or warranties, either expressed
or implied, by or with respect to anything in this manual, and shall not be
liable for any implied warranties of merchantability or fitness for a particular purpose of for any indirect, special or consequential damages.
Copyright Notice
Copyright 1994-2001 Synplicity, Inc. All Rights Reserved.
Synplicity software products contain certain confidential information of
Synplicity, Inc. Use of this copyright notice is precautionary and does not
imply publication or disclosure. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form by any means without the prior
written permission of Synplicity, Inc. While every precaution has been
taken in the preparation of this book, Synplicity, Inc. assumes no responsibility for errors or omissions. This publication and the features
described herein are subject to change without notice.
Trademarks
Synplicity, the Synplicity S logo, Behavior Extracting Synthesis
Technology, Embedded Synthesis, HDL Analyst, SCOPE, Simply Better
Results, Simply Better Synthesis, Synplify, and Synthesis Constraint
Optimization Environment are registered trademarks of Synplicity, Inc.
Amplify, B.E.S.T., Certify, DST, Direct Synthesis Technology, PartitionDriven Synthesis, and Physical Optimizer are trademarks of
Synplicity, Inc.
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Verilog is a registered trademark of Cadence Design Systems, Inc. IBM
and PC are registered trademarks of International Business Machines
Corporation. Microsoft is a registered trademark of Microsoft Corporation.
Sun, SPARC, Solaris, and SunOS are trademarks of Sun Microsystems,
Inc. UNIX is a registered trademark of UNIX Systems Laboratories, Inc. All
other product names mentioned herein are the trademarks or registered
trademarks of their respective owners.
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Preface
This is a legal agreement between you, the user (Licensee) and Synplicity, Inc.
(Synplicity) regarding the software program that is attached to or enclosed with
this software license agreement, or that is the subject of this documentation (the
SOFTWARE). The term SOFTWARE also includes related documentation
(whether in print or electronic form) and, if Licensee is obtaining an update, any
pre-existing software and data provided within earlier software releases (to the
extent such earlier software and data is retained by, embodied in or in any way
used or accessed by the upgraded SOFTWARE provided with this Agreement). If
Licensee is a participant in the University Program or has been granted an
Evaluation License, then some of the following terms and conditions may not
apply (refer to the sections entitled, respectively, Evaluation License and
University Program, below).
By opening the packaging of the SOFTWARE, or by installing or using the
SOFTWARE, Licensee agrees to be bound by the terms of this Software License
Agreement (the Agreement). If Licensee does not agree to the terms of this
Agreement, then do not install the SOFTWARE and return the copy of the
SOFTWARE to the place from which you obtained it.
Evaluation License. The following applies, in addition to the other terms and
conditions and as a limit on the license, if Licensee has obtained an Evaluation
License. If Licensee has obtained the SOFTWARE pursuant to an evaluation
license, then the following additional terms, conditions, and restrictions apply:
(a) The license to the SOFTWARE terminates after 20 days (unless otherwise
agreed to in writing by Synplicity); and (b) Licensee may use the SOFTWARE only
for the sole purpose of tests and other evaluation to determine whether Licensee
wishes to license the SOFTWARE on a commercial basis. Licensee shall not use
the SOFTWARE to design any integrated circuits for production or preproduction purposes or any other commercial use including, but not limited to,
for the benefit of Licensees customers. If Licensee breaches any of the foregoing
restrictions, then Licensee shall pay to Synplicity a license fee equal to
Synplicitys standard license fee for the commercial version of the SOFTWARE.
License. Synplicity grants to Licensee, a non-exclusive right to install the
SOFTWARE and to use or authorize use of the SOFTWARE by up to the number
of nodes for which Licensee has a license and for which Licensee has the security
key(s) or authorization code(s) provided by Synplicity or its agents. All
SOFTWARE must be used within the country for which the systems were
licensed and at Licensee's site (contained within a one kilometer radius);
however, remote use is permitted by employees who work at the site but are
temporarily telecommuting to that same site from less than 50 miles away (for
example, an employee who works
LO at a home office on occasion). In addition,
Synplicity grants to Licensee a non-exclusive license to copy and distribute
internally the documentation portion of the SOFTWARE in support of its license
to use the program portion of the SOFTWARE.
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Preface
Copy Restrictions. This SOFTWARE is protected by United States copyright laws
and international treaty provisions and copying not in accordance with this
Agreement is forbidden. Licensee may copy the SOFTWARE only as follows: (i) to
directly support authorized use under the license and (ii) in order to make a copy
of the SOFTWARE for backup purposes. Copies must include all copyright and
trademark notices.
Use Restrictions. This SOFTWARE is licensed to Licensee for internal use only.
Licensee shall not (and shall not allow any third party to): (i) decompile,
disassemble, reverse engineer or attempt to reconstruct, identify or discover any
source code, underlying ideas, underlying user interface techniques or
algorithms of the SOFTWARE by any means whatever, or disclose any of the
foregoing; (ii) provide, lease, lend, or use the SOFTWARE for timesharing or
service bureau purposes, on an application service provider basis, or otherwise
circumvent the internal use restrictions; (iii) modify, incorporate into or with
other software, or create a derivative work of any part of the SOFTWARE; (iv)
disclose the results of any benchmarking of the SOFTWARE, or use such results
for its own competing software development activities, without the prior written
permission of Synplicity; or (v) attempt to circumvent any user limits, maximum
gate count limits or other license, timing or use restrictions that are built into the
SOFTWARE.
Transfer Restrictions. Licensee shall not sublicense, transfer or assign this
Agreement or any of the rights or licenses granted under this Agreement, except
in the case of a merger or sale of all or substantially all of Licensees assets.
Ownership of the SOFTWARE. Synplicity retains all right, title, and interest in
the SOFTWARE (including all copies), and reserves all rights not expressly
granted to Licensee. This License is not a sale of the original SOFTWARE or of
any copy.
Ownership of Design Techniques. Design means the representation of an
electronic circuit or device(s), derived or created by Licensee through the use of
the SOFTWARE in its various formats, including, but not limited to, equations,
truth tables, schematic diagrams, textual descriptions, hardware description
languages, and netlists. Design Techniques means the Synplicity-supplied data,
circuit and logic elements, libraries, algorithms, search strategies, rule bases,
and technical information incorporated in the SOFTWARE and employed in the
process of creating Designs. Synplicity retains all right, title and interest in and to
Design Techniques incorporated into the SOFTWARE, including all intellectual
property rights embodied therein. Licensee acknowledges that Synplicity is in the
business of licensing SOFTWARE which incorporates Design Techniques.
Licensee agrees that in the event Licensee voluntarily discloses any design
techniques to Synplicity without designating such as Licensees Confidential
Information, Synplicity has an unrestricted, royalty-free right to incorporate
those Design Techniques into its software, documentation and other products,
and to sublicense third parties to use those incorporated design techniques.
Protection of Confidential Information. Confidential Information means (i)
the source code of the SOFTWARE, and any included trade secrets (including any
technology, idea, algorithm or information contained in the SOFTWARE, and
specifically including Design Techniques); (ii) either partys product plans,
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designs, costs, prices and names; non-published financial information;
marketing plans; business opportunities; personnel; research; development or
know-how; (iii) any information designated by the disclosing party as confidential
in writing or, if disclosed orally, designated as confidential at the time of
disclosure and reduced to writing and given to the receiving party and designated
as confidential in writing within 30 days; and (iv) the terms and conditions of this
Agreement; provided, however that Confidential Information will not include
information that: (a) is or becomes generally known or available by publication,
commercial use or otherwise through no fault of the receiving party; (b) is known
and has been reduced to tangible form by the receiving party at the time of
disclosure and is not subject to restriction; (c) is independently developed by the
receiving party without use of the disclosing partys Confidential Information; (d)
is lawfully obtained from a third party who has the right to make such
disclosure; or (e) is released for publication by the disclosing party in writing.
Each party will protect the others Confidential Information from unauthorized
dissemination and use with the same degree of care that each such party uses to
protect its own like information. Neither party will use the others Confidential
Information for purposes other than those necessary to directly further the
purposes of this Agreement. Neither party will disclose to third parties the others
Confidential Information without the prior written consent of the other party.
Termination. Synplicity may terminate this Agreement in the event of breach or
default by Licensee. Upon termination Licensee will relinquish all rights under
this Agreement, and must cease using the SOFTWARE and return or destroy all
copies (and partial copies) of the SOFTWARE and documentation.
Export. Licensee shall not allow the Synplicity SOFTWARE to be sent or used in
any country except in compliance with applicable U. S. laws and regulations.
Limited Warranty and Disclaimer. Synplicity warrants that the program
portion of the SOFTWARE will perform substantially in accordance with the
accompanying documentation for a period of 90 days from the date of receipt.
Synplicitys entire liability and Licensees exclusive remedy for a breach of the
preceding limited warranties shall be, at Synplicitys option, either (a) return of
the license fee, or (b) providing a fix, patch, work-around, or replacement of the
SOFTWARE that does not meet such limited warranty. In either case, Licensee
must return the SOFTWARE to Synplicity with a copy of the purchase receipt or
similar document. Replacements are warranted for the remainder of the original
warranty period or 30 days, whichever is longer. Some states/jurisdictions do
not allow limitations on duration of an implied warranty, so the above limitation
may not apply. EXCEPT AS EXPRESSLY SET FORTH ABOVE, NO OTHER
WARRANTIES OR CONDITIONS, EITHER EXPRESS OR IMPLIED, ARE MADE BY
SYNPLICITY WITH RESPECT TO THE SOFTWARE AND THE ACCOMPANYING
DOCUMENTATION (STATUTORY OR OTHERWISE), AND SYNPLICITY
EXPRESSLY DISCLAIMS ALL WARRANTIES AND CONDITIONS NOT EXPRESSLY
STATED HEREIN, INCLUDING BUT NOT LIMITED TO THE IMPLIED
WARRANTIES OR CONDITIONS OF MERCHANTABILITY, NONINFRINGEMENT,
AND FITNESS FOR A PARTICULAR
PURPOSE. SYNPLICITY DOES NOT
LO
WARRANT THAT THE FUNCTIONS CONTAINED IN THE SOFTWARE WILL MEET
LICENSEES REQUIREMENTS, BE UNINTERRUPTED OR ERROR FREE, OR
THAT ALL DEFECTS IN THE PROGRAM WILL BE CORRECTED. Licensee
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assumes the entire risk as to the results and performance of the SOFTWARE.
Some states/jurisdictions do not allow the exclusion of implied warranties, so the
above exclusion may not apply.
Limitation of Liability. IN NO EVENT SHALL SYNPLICITY OR ITS AGENTS BE
LIABLE FOR ANY INDIRECT, SPECIAL, CONSEQUENTIAL OR INCIDENTAL
DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR
LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTIONS, LOSS OF
BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING OUT OF
THE USE OF OR INABILITY TO USE THESE SYNPLICITY PRODUCTS, EVEN IF
SYNPLICITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. In
no event will Synplicity be liable to Licensee for damages in an amount greater
than the fees paid for the use of the SOFTWARE. Some states/jurisdictions do
not allow the limitation or exclusion of incidental or consequential damages, so
the above limitations or exclusions may not apply.
Intellectual Property Right Infringement. If a claim alleging infringement of an
intellectual property right arises concerning the SOFTWARE (including but not
limited to patent, trade secret, copyright or trademark rights), Synplicity in its
sole discretion may elect to defend or settle such claim. Synplicity in the event of
such a claim may also in its sole discretion elect to terminate this Agreement and
all rights to use the SOFTWARE, and require the return or destruction of the
SOFTWARE, with a refund of the fees paid for use of the SOFTWARE less a
reasonable allowance for use and shipping.
Miscellaneous. If Licensee is a corporation, partnership or similar entity, then
the license to the Software that is granted under this Agreement is expressly
conditioned upon acceptance by a person who is authorized to sign for and bind
the entity. This Agreement is the entire agreement between Licensee and
Synplicity with respect to the license to the SOFTWARE, and supersedes any
previous oral or written communications or documents (including, if you are
obtaining an update, any agreement that may have been included with the initial
version of the Software). This Agreement is governed by the laws of the State of
California, USA. This Agreement will not be governed by the U. N. Convention on
Contracts for the International Sale of Goods and will not be governed by any
statute based on or derived from the Uniform Computer Information
Transactions Act (UCITA). If any provision of this Agreement is found to be invalid
or unenforceable, it will be enforced to the extent permissible and the remainder
of this Agreement will remain in full force and effect. Failure to prosecute a
partys rights with respect to a default hereunder will not constitute a waiver of
the right to enforce rights with respect to the same or any other breach.
Government Users. The Software contains commercial computer software and
commercial computer software documentation. In accordance with FAR 12.212
and DFARS 227.7202, use, duplication or disclosure is subject to restrictions
under paragraph (c)(1)(ii) of the Rights in Technical Data and Computer Software
clause at 252.227-7013, and further restricted by this Agreement. Synplicity,
Inc., 935 Stewart Drive, Sunnyvale, CA 94085, U. S. A.
University Program. The following section applies only if Licensee is a participant
in Synplicitys University Program; it does not replace the remainder of the
Agreement and supersedes only those terms that directly conflict.
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Preface
University Program: License. Subject to the terms and conditions of this
Agreement, Synplicity hereby grants to Licensee (a University) for the License
Term (defined below), a non-exclusive license, only for purposes of course work or
teaching in connection with a university-sponsored class, or for academic
research either sponsored by or conducted under the auspices of Licensee, to (a)
install and use the SOFTWARE, and (b) reproduce and distribute copies of the
documentation included in the SOFTWARE subject only to payment for those
copies (which may be based on the number of users, the number and type of
copies, or both). If the SOFTWARE is licensed pursuant to a node-locked license,
then the Licensee may install and use the SOFTWARE on the authorized
workstations. If the SOFTWARE is licensed pursuant to a floating license, then
the Licensee may install the SOFTWARE on the authorized server and use the
SOFTWARE on up to the number of nodes for which Licensee has paid license
fees and Synplicity has granted authorization.
University Program: License Term and Termination. For purposes of the
University Program, License Term means one year unless otherwise agreed to in
writing. This Agreement will terminate at the end of the License Term, unless
earlier terminated in accordance with this Agreement.
University Program: License Restrictions. As Licensee, University may not (i)
allow access to the SOFTWARE by any user not registered for a course or
participating in an academic research project for which use of the SOFTWARE
has been authorized; (ii) use the SOFTWARE to design any commercial products;
or (iii) disclose the results of any benchmarking of the SOFTWARE, or use such
results for its own competing software development activities, without the prior
written permission of Synplicity.
University Program: Technical Liaison. Licensee shall appoint a Technical
Liaison who will serve as the single point of contact between Synplicity and
Licensee with respect to the subject matter of this Agreement. The Technical
Liaison will coordinate installation and maintenance of the SOFTWARE,
communicate with Synplicity regarding license procedures, administer Licensees
obligations under this Agreement and respond to inquiries by Synplicity related
to the subject matter of this Agreement.
University Program: Technical Support in North America. Unless otherwise
agreed in writing, Synplicity will accept calls only from the appointed Technical
Liaison. No technical support will be provided other than calls from the Technical
Liaison relating to installation of the SOFTWARE. SOFTWARE upgrades may be
obtained from the Synplicity Web Site.
University Program: International Technical Support. Technical support is
provided through Synplicitys authorized distributors in accordance with their
applicable policies.
revised 02/01
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Synplify Pro User Guide, February 2001
Contents
Chapter 1: Introduction
Synplify Pro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
About the Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synplicity Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-2
1-2
1-3
1-3
1-4
1-4
1-5
1-5
1-6
1-6
1-6
1-6
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Scope of the Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Starting the Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Setting Up Your License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Getting Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
User Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
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Contents
Set up Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Create a Project File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Check the Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Resolve Source File Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Examine the RTL View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Altera Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Set Altera Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Set Altera Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Run Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Analyze the Synthesis Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Examine the Technology View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Check Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analyze Critical Paths in the Technology View . . . . . . . . . . . . . . . . . . . . . . .
2-22
2-22
2-24
2-25
2-35
2-35
2-37
2-39
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3-13
3-13
3-15
3-16
3-17
3-20
3-21
3-22
3-22
3-25
3-26
3-27
3-28
3-29
3-30
3-33
3-35
3-38
3-39
3-40
3-41
3-42
3-42
3-43
3-44
3-49
3-50
3-51
3-53
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Contents
Crossprobing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crossprobing within an RTL/Technology View . . . . . . . . . . . . . . . . . . . . . . . .
Crossprobing from the RTL/Technology View . . . . . . . . . . . . . . . . . . . . . . . .
Crossprobing from the Text Editor Window . . . . . . . . . . . . . . . . . . . . . . . . . .
Crossprobing from the Tcl Script Window . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crossprobing from the FSM Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-54
3-54
3-55
3-56
3-57
3-60
3-60
3-61
3-62
3-64
3-65
3-67
3-68
3-70
3-72
3-72
3-74
3-74
3-76
3-76
3-82
3-82
3-83
3-85
3-87
3-95
3-95
3-96
3-97
3-99
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Contents
Preventing Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102
Preserving Objects from Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102
Preserving Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-103
Working with Multiple Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-104
Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Optimization Tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Area Optimization Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Optimization Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-106
3-106
3-107
3-107
4-4
4-4
4-4
4-5
4-5
4-6
4-7
4-15
4-15
4-17
4-19
4-21
4-22
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Contents
Using FSM Explorer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
Deciding When to Use the FSM Explorer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
Running the FSM Explorer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Prerequisites for Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pipelining the Entire Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adding Pipelining Attributes in the Source Code . . . . . . . . . . . . . . . . . . . . . .
Adding Pipelining Attributes Interactively . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-29
4-30
4-30
4-31
4-32
Retiming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Retiming During Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Retiming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Retiming Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-34
4-35
4-37
4-38
4-41
4-42
4-42
4-46
4-49
4-51
4-54
4-54
4-55
4-55
4-56
4-57
4-58
4-59
4-59
4-60
4-60
4-62
4-64
4-66
4-67
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Synplify Pro User Guide, February 2001
Contents
Using the Xilinx Modular Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction to the Modular Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initial Design Budgeting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Active Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Final Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design Files and Area Floorplanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synplify Pro and Amplify Modular Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents
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Synplify Pro User Guide, February 2001
Chapter 1
Introduction
This chapter contains an introduction to Synplify Pro, and describes the
following:
Synplify Pro on page 1-2
The Generic FPGA Design Flow on page 1-4
Audience on page 1-7
Scope of the Document on page 1-7
Starting the Software on page 1-8
User Interface Overview on page 1-12
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Synplify Pro
Chapter 1: Introduction
Synplify Pro
This section briefly discusses the following topics:
About the Software
Supported Platforms
Supported Standards
Synplicity Product Family
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Synplify Pro
Chapter 1: Introduction
Supported Platforms
Synplify Pro runs on these platforms:
PC (Windows98/Windows 2000/NT 4.0/Windows ME)
Sun (Sun OS 5.6 and 5.7/Solaris 2.6 and 2.7)
HP-UX 10.20
Supported Standards
Verilog
Synplify Pro supports a synthesizable subset of Verilog95 (IEEE
1364).
VHDL
Synplify Pro supports a synthesizable subset of VHDL93 (IEEE
1076), and the following IEEE library packages:
std_logic_1164
numeric_std
numeric_bit
std_logic_unsigned
std_logic_signed
std_logic_arith
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Chapter 1: Introduction
Synplify
Certify
Physical Optimization
Amplify
Synplify Pro
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Chapter 1: Introduction
Synplify Pro
Technology Mapping
Placement
Routing
FPGA Configuration
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Chapter 1: Introduction
Technology Mapping
Technology mapping is the second phase of optimization, in which the
logic is optimized to a specific technology. During this phase, the
compiled design is transformed into a circuit of optimized FPGA logic
blocks. Depending on your design priorities, you might want to focus on
area optimization (minimizing the total number of blocks), delay optimization (minimizing the number of logic block stages in time-critical paths),
or both.
Synplify Pro uses architecture-specific mapping techniques to map the
logic design. It has built-in tools to analyze critical paths, crossprobe, and
check the RTL view. Synplify Pro outputs netlists in formats appropriate
for the place and route tools that follow.
Placement
Placement is the first step of the physical design process. During placement, the logic blocks are placed in an FPGA array. At this point, considerations like the total interconnect length become important.
This is the point at which Synplify Pro gives control of the design to
another tool. However if you have the Amplify Physical Optimizer, you
can use the results from an initial placement pass to further optimize
your logic design.
Routing
Routing is the final step of the physical design process. At this stage, use
the place-and-route tool to connect the placed logic blocks by assigning
wire segments and choosing programmable switches.
FPGA Configuration
In this design phase, you configure the final FPGA chip and implement it.
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Audience
Chapter 1: Introduction
Audience
Synplify Pro is targeted towards the FPGA system developer. It is assumed
that you are knowledgeable about the following:
Design synthesis
RTL
FPGAs
Verilog/VHDL
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Chapter 1: Introduction
Getting Started
1. If you have not already done so, install Synplify Pro according to the
installation instructions.
2. Start the software.
If you are working on a PC, select Programs->Synplicity->Synplify Pro
from the Start button.
If you are working on a UNIX workstation, type this at the
command line:
synplify_pro
The command starts the Synplify Pro synthesis tool, and opens the
Project window. If you have run the software before, the window
displays the previous project. For more information about the interface, see the Synplify Pro Reference Manual.
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Chapter 1: Introduction
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Chapter 1: Introduction
To automatically start the selected license the next time you start
Synplify Pro select Save as default license type at the bottom of the
window.
Click Save and restart the software.
3. For Windows 98, Windows ME, Windows NT, and Windows 2000,
install the sentinel driver.
Double click on the setupx86.exe file in the <install
drive>\Synplicity\sentinel directory.
In the installation window that opens, click Functions (located in the
upper left hand corner) to select Install Sentinel driver. A dialog box
specifying the path for I386 pops up.
Confirm that the path is correct.
After the drive has been installed, restart the computer. You can
now start Synplify Pro.
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Chapter 1: Introduction
Getting Help
Before you call Synplicity Support, look through the documented information. You can access the information online from the Help menu, or refer to
the printed manual. The following table shows you how the information is
organized.
For help with...
Refer to the...
Licensing
Installation Guide
Synthesis features
Tcl
Using tool-specific
features and attributes
How to...
Flow information
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Chapter 1: Introduction
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Chapter 1: Introduction
Toolbars
Menu
Status Bar
Button
Panel
View Tab
Project View
The other choice is shown below. In this interface, some features are only
available from the menus. For information about using this interface, see
Classic Interface on page 4-52.
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Chapter 1: Introduction
Menus
Toolbars
Project View
UI Buttons
and Options
View Tab
Status
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Synplify Pro User Guide, February 2001
Chapter 2
Synplify Pro Tutorial
The tutorial shows you how to use Synplify Pro in the design process.
Information is organized into these topics:
Introduction to the Tutorial on page 2-2
The Tutorial Design Flow on page 2-3
Start the Software on page 2-4
Set up Source Files on page 2-6
Altera Flow on page 2-17
Set Altera Constraints on page 2-17
Run Synthesis on page 2-22
Analyze the Synthesis Results on page 2-22
Rerun Synthesis on page 2-27
Xilinx Flow on page 2-29
Set Constraints on page 2-30
Set Xilinx Device Options on page 2-32
Run Synthesis on page 2-35
Analyze the Synthesis Results on page 2-35
Rerun Synthesis on page 2-40
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See...
Installation information
Advanced techniques
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Technology parameters
Set Options
Run
Analyze
Rerun
Implement FPGA
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tutorial
verilog
vhdl
<technology>
Source Files
<technology>
Source Files
Source Files
Source Files
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The command starts the synthesis tool and opens the Project
Window. This figure shows the window the first time you start the
software. If you have run the software before, the window displays
the previous project. For more information about the interface, see
the Synplify Pro Reference Manual.
Toolbars
Menu
Project Window
TCL Window
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Even though you do not use the Tcl window in this tutorial, you can
leave it open to view status and other informational messages.
You can access common commands in different ways: through the
menu, popup menus, keyboard shortcuts, and icons. Throughout
this tutorial, the alternate methods are listed first and the menu
command is listed at the end.
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The next step is to add the source files to your project file.
3. Add the source files, by doing the following in the dialog box:
Set the Look In field at the top to the <technology> folder. This
tutorial uses VHDL source files. However, when you run the
software on your own design, you also have the option of using
Verilog source files or mixed input files.
Set Files of Type to VHDL files (*.vhd). If you are using Verilog files, you
must set this to Verilog files (*.v).
Add the package file first. Select the const_pkg.vhd file and click
the Add button on the right side of the form. The file appears in the
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text box at the bottom of the form. You do not need to add the
package file first in Verilog.
Add the other files. Click the Add All button on the right side of the
form to add all the files in the directory. The text box now displays
all the .vhd files.
Click OK.
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5. Make sure the package file is the first file and the top-level file is the
last in the list of files in the Project window. Click the top-level file
(eight_bit_uc.vhd) in the text box and drag it to the end of the list of
files. The order of the rest of the files does not matter.
6. Save and rename the project. Select File->Save, type tutorial as the name
of the project, and click Save. The Project window reflects your
changes.
If your files are not in a folder under the tutorial directory, you can
set this preference by selecting the Options->Project View Options
command and checking the View project files in folders box. This separates
one kind of file from another in the Project view by putting them in
separate folders.
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2. Review the warning. To see the warning, click the Warnings tab in
the Tcl window. Double-click the ins_decode.vhd file in the Project view.
This opens the Text Editor window, with the error highlighted in red.
@W: ins_decode.vhd(21): Map for port tris_we of component
ins_decode not found
@W: eight_bit_uc.vhd(171): tris_we is not assigned a value
(floating)
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Type TRIS in the Find What field of the form and click Find Next. The
software finds this line:
TRIS_XWE : out std_logic;
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left pane lists the nets and ports in the design and the right pane
contains the schematic. At the top, it lists the number of sheets in
the schematic.
Zoom into
this area
marked by
the red
rectangle
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Incrementor
symbol
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Click the Push/Pop Hierarchy icon and then click in a blank area of
the view (you see an arrow pointing upwards) to return to the top
level.
5. To crossprobe from the source code to the schematic, double-click
the alu.vhd file in the Project view. This opens the source file.
Select the Push/Pop Hierarchy icon and click the ALU block in the RTL
view. You see a schematic of the ALU function.
Select the entire bitdecoder definition in the source file. You can
use Ctrl-f to find the definition, which begins with this code:
BITDECODER <= 00000001.
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6. Close the source code window and return to the top-level schematic
view. You can iconize the RTL view, but do not close it.
The rest of the tutorial varies slightly, depending on the technology
you use. So, if you are working with Altera technology, go to Altera
Flow on page 2-17 for the next step. If you are working with Xilinx
technology, go to Xilinx Flow on page 2-29 for the next step. If you do
not use either of these vendors, you can follow the methodology used
in either of these flows and substitute device options specific to your
vendor.
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Altera Flow
Altera Flow
The Altera design flow in this tutorial uses APEX technology. The following
sections show you how to
Set Altera Constraints
Set Altera Device Options
Run Synthesis
Analyze the Synthesis Results
Rerun Synthesis
To work through the tutorial with the Xilinx design flow, see Xilinx Flow
on page 2-29. If you do not use Altera or Xilinx, you can still follow along
with the tutorial, using device options specific to your vendor.
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2-17
2. Click Initialize.
The SCOPE window opens, with the most common constraints, clock
frequency and input/output delays, initialized.
3. Do the following to set a clock frequency constraint:
Select the Clocks tab at the bottom, if it is not already selected.
Click the box in the Enabled column to enable the clock constraint.
Enter 65 in the Value column to set the global frequency value.
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6. Select Yes in the dialog box that asks you if you want to add the file to
the project.
You should now have the following files in the project:
A vhdl folder that contains the source files
A constraint folder with the constraint file (tutorial.sdc)
An implementation folder (rev_1)
Now that you have your files set up, you can set the device options and
run synthesis.
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3. Click the Options/Constraints tab at the top, and set the following:
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Leave the default optimization switches (Symbolic FSM Compiler and
Resource Sharing).
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4. Click the Implementation Results tab, and check the Write Vendor Constraint
File option is checked. Leave the other defaults.
5. Do not make any changes on the VHDL tab. Click OK.
You have already specified the top-level module in the project window
by putting it last in the list. If you had not done that, you would
specify the top-level module in the VHDL tab.
You have now set all the device options and can run synthesis.
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Run Synthesis
Run Synthesis
1. Make sure you have the prerequisites for synthesis:
Source files
Target technology (device options)
An optional constraint file
2. Click the Run button to start synthesis.
The software goes through two synthesis phases, compilation and
mapping. It reflects these stages in the Status box in the upper right of
the project window. Compilation is the creation of a technologyindependent boolean structure, and mapping is the technologyspecific optimization of the boolean structure. You can see the
results of compilation in the RTL view and the results after mapping
in the Technology view.
You can now go on to analyze your results and check timing.
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(probably Sheet 1), and click OK. Click in an empty area of the
schematic to deselect the component.
Alternatively, click F12 or click the right mouse button and select
Filter Schematic from the menu. You see another Technology view,
with just the component you selected. Close this view.
Check Timing
You can check timing results in the log file and in the log watch window.
The latter is a quick way to view just the essentials.
1. Check the essential timing parameters in the log watch window.
Select View -> Log Watch Window to open a window where you can
quickly see the essential information, presented in a spreadsheet
format.
Position the cursor in the first cell in the Log Parameter column, and
hold down the left mouse button.
Select Estimated Frequency from the popup list. The software displays
the corresponding value.
Repeat the previous two steps in to set the Requested Frequency, Slack
and I/O ATOMs. You can see that the design does not meet timing
because it has a negative slack time. Positive or 0 slack times
indicate that you have met or are under the timing constraint.
Close the log watch window.
The following figure shows the values in the log watch window. The
values you get when you run the tutorial might vary slightly, because
of the ongoing optimization of the synthesis tool.
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4. Leave the filtered critical path view open, and close any other open
Technology views.
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Rerun Synthesis
Rerun Synthesis
This section walks you through the post-analysis phase, where you set
constraints, rerun synthesis, and check your results.
Rerun Synthesis
The critical path fails timing because it was not set up as a two-cycle path.
You now add that constraint and resynthesize the design.
1. Make sure you have the filtered view of the critical path open. Click
the clock icon, to deselect the objects in the filtered view.
2. Open the constraints file.
Double-click on the constraint file (tutorial.sdc) in the Project
view to open the file. The SCOPE window opens.
Select the Multi-cycle Paths tab in SCOPE.
3. Add a constraint to the end point of the critical path. In this example,
the end point is Dmux.ALUA. You can use one of these ways to add the
end point.
To drag and drop:
Select one of the end points of the critical path in the filtered
Technology view. You can select it directly or use Ctrl-f to find and
select the object you want. If you use Ctrl-f, double-click the object
you want on the Instances tab. This moves the object from the
Unhighlighted to the Highlighted column, and it is selected in all open
views.
Drag and drop it into the Object column of the SCOPE window.
To select in the SCOPE table:
Pull down the menu in the Object column in SCOPE, and select the
object you need. To do this, you must have a compiled design.
4. Set the constraints.
For each component, set Type to to.
Type 2 in the Value column for each of the components.
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Rerun Synthesis
Save the constraint file. If you save it as a new constraint file, you
must add it to the project file. Iconify or close the SCOPE window.
eight_bit_uc.vm [VERILOG]
eight_bit_uc.vhm [VHDL]
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eight_bit_uc_cons.tcl [Constraints]
eight_bit_uc.vqm [VERILOG/VHDL]
Result file
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Description
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Xilinx Flow
Xilinx Flow
The Xilinx flow uses Virtex technology. The following sections show you
how to
Set Constraints
Set Xilinx Device Options
Run Synthesis
Analyze the Synthesis Results
Rerun Synthesis
To work through the tutorial with the Altera design flow, see Altera Flow
on page 2-17. If you do not use Altera or Xilinx, you can follow along with
the tutorial using device options specific to your vendor.
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Set Constraints
Set Constraints
Design constraints are optional, but most designers use them to define
the frequency goals and describe the environment around the design. For
designs without aggressive timing goals, you can just set the clock period.
You can set constraints in a text file that you can create with any text
editor, but it is easier to use SCOPE (Synthesis Constraint Optimization
Environment). SCOPE provides an easy-to-use spreadsheet interface for
entering constraints.
The tutorial design uses basic constraints, which you enter as follows:
1. Start SCOPE in the open project window by doing one of the
following:
Clicking the Constraint file (SCOPE) icon in the toolbar.
Selecting File - >New Constraint file (SCOPE).
The Initialize New Constraints dialog box opens.
2. Click Initialize.
The SCOPE window opens, with the most common constraints, clock
frequency and input/output delays, initialized.
3. Do the following to set a clock frequency constraint:
Select the Clocks tab at the bottom, if it is not already selected.
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Click the box in the Enabled column to enable the clock constraint.
Enter 82 in the Value column to set the global frequency.
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Set Constraints
6. Select Yes in the dialog box that asks you if you want to add the file to
the project.
You should now have the following files in the project:
A vhdl folder that contains the source files
A constraint folder with the constraint file (tutorial.sdc)
An implementation folder (rev_1)
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You can now set the device options and run synthesis.
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Leave the other defaults. The dialog box should look like this:
3. Click the Options/Constraints tab at the top, and set the following:
Leave the default optimization switches (Symbolic FSM Compiler and
Resource Sharing).
Make sure the constraint file is checked.
Leave the defaults on the Implementation Results tab.
Click OK.
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4. Click the Implementation Results tab, and make sure the Write Vendor
Constraint File option is checked. Leave the other defaults.
5. Do not make any changes on the VHDL tab. Click OK.
You have already specified the top-level module in the project
window by putting it last in the list. If you had not done that, you
would specify the top-level module in the VHDL tab. You have now set
all the device options and can run synthesis.
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Run Synthesis
Run Synthesis
1. Make sure you have the prerequisites for synthesis:
Source files
Target technology (device options)
An optional constraint file
2. Click the Run button to start synthesis.
The software goes through two synthesis phases, compilation and
mapping, and it reflects these stages in the Status box in the upper
right of the project window. Compilation is the creation of a
technology-independent boolean structure, and mapping is the
technology-specific optimization of the boolean structure. You can
see the results of compilation in the RTL view and the results after
mapping in the Technology view.
You might get warning messages after mapping. You can ignore these
warnings.
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Check Timing
You can check timing results in the log file and in the Log Watch window.
The latter is a quick way to view just the essentials.
1. Check the essential timing parameters in the log watch window.
Select View -> Log Watch Window to open a window where you can
quickly see the essential information, presented in a spreadsheet
format.
Position the cursor in the first cell in the Log Parameter column, and
hold down the left mouse button.
Select Estimated Frequency from the popup list. The software displays
the corresponding value.
Repeat the previous two steps in subsequent cells to set the
Requested Frequency, and Slack. You can see that the design does not
meet timing because it has a negative slack time. Positive or 0
slack times indicate that you have met or gone under the timing
constraint. Close the Log Watch window.
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The following figure shows the values in the log watch window. The
values you get when you run the tutorial might vary slightly, because
of the ongoing optimization of the synthesis tool.
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Rerun Synthesis
Zoom in and examine the critical path. You can handle the critical
path by adding a multicycle path constraint and resynthesizing
the design. The start point of the path is Dmux.ALUA and the end
points are UC_ALU.ALUZ and Dmux.ALUB. If you have a different
critical path, you can follow the method shown here to add a
different constraint.
5. Leave the filtered critical path view open, and close any other open
Technology views.
Rerun Synthesis
To meet timing, you set multicycle constraints on the start and end points
of the critical path. You add the constraints and resynthesize the design.
1. Make sure you have the filtered view of the critical path open. Click
the clock icon, to deselect the objects in the view.
2. Open the constraints file.
Double-click on the constraint file (tutorial.sdc) in the Project
view to open the file. The SCOPE window opens.
Select the Multi-cycle Paths tab in SCOPE.
3. Add the start point of the critical path to SCOPE. You can use one of
these ways to add the start point.
To drag and drop:
Select the start point of the critical path (Dmux.ALUA) in the filtered
Technology view. You can select it directly or use Ctrl-f to find and
select the object you want. If you use Ctrl-f, double-click the object
you want on the Instances tab. This moves the object from the
Unhighlighted to the Highlighted column, and it is selected in all open
views.
Drag and drop it into the Object column of the SCOPE window.
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Rerun Synthesis
To select in SCOPE:
Pull down the menu in the Object column in SCOPE, and select the
object you need. To do this, you must have a compiled design.
To enter directly, type Dmux.ALUA[7:0] in the Object column in
SCOPE.
4. Repeat the previous step to add the end points of the critical path to
SCOPE.
5. Set the constraints.
For the start point (Dmux.ALUA), set Type to from.
For the end points (UC_ALU.ALUZ and Dmux.ALUB), set Type to to.
Type 2 in the Value column for each of the components.
Save the constraint file and add it to the project file. Iconify the
SCOPE window.
6. Click the Run button to rerun synthesis. You can now check the
results to see if the constraints eliminated the negative slack on the
path.
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Rerun Synthesis
Description
eight_bit_uc.edf [EDIF]
eight_bit_uc.vhm [VHDL]
eight_bit_uc.vm [VERILOG]
eight_bit_uc_ncf [Constraints]
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Chapter 3
Tasks and Tips
This chapter describes typical synthesis tasks, some of which are also in
the tutorial. It covers the following:
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Set up Files
Set Constraints
Set Options
Vendor-specific options
Analyze Results
Implement FPGA
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A blank editing window opens with line numbers on the left. You can
name it now by pressing Ctrl-s and naming the file, or after you have
entered some text. Go to step 3.
2. To create a new file using the menu command, do the following:
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In the form that opens, select the kind of source file you want to
create, Verilog or VHDL.
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To check all the source files in a project, make sure that none of
the files are active, do not select any files in the list, and go to the
next step. If you have an active source file, the software only
checks the active file.
For details of setting up the project file, see Setting Up Project Files on
page 3-13.
2. To check the syntax, select Run->Syntax Check or press Shift+F7.
The software detects syntax errors like incorrect keywords and
punctuation. It puts an exclamation mark next to files in the project
list that have errors, and lists the number of warnings or notes
found. If there are no errors, the Tcl Script window at the bottom of
the project window displays this message:
Syntax check successful!
3. To run a synthesis check, select Run->Synthesis Check or press Shift+F8.
If there are hardware-related errors like incorrectly-coded flip-flops,
the software displays an exclamation mark next to the file name in
the project list and lists the number of warnings or errors it found in
the file.
4. Review the errors by doing one of the following:
Check the log file for information about the error by selecting View
-> Log File.
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Click the Error, Warning, or Note tab in the Tcl window and doubleclick the error.
The Editing window opens the relevant source file, and highlights the
code that caused the error message. Messages can be categorized as
errors, warnings or notes. Review all of them and resolve all errors.
Warnings are less serious, but you must read through and understand them even if you do not resolve all of them. Notes are less
serious, and generally contain information. For information on fixing
errors, see Viewing and Editing Source Files on page 3-6.
To automatically open the first file in the list with errors, press
Ctrl-F5.
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Do...
Select the command from the popup (hold down the right
mouse button to get the popup) or from the Edit menu
Go to a specific line
Find text
Press Ctrl-f or select Edit ->Find. Type the text you want to
find, and click OK.
Replace text
Press Ctrl-h or select Edit -> Replace. Type the text you
want to find, and the text you want to replace it with. Click
OK.
Complete a keyword
Edit columns
Press Alt, and use the left mouse button to select the
column.
3. To create and work with bookmarks in your file, see the following
table.
Bookmarks are a convenient way to navigate long files or to jump to
points in the code that you refer to often. You can use the icons in
the Edit toolbar for these operations. If you cannot see the Edit toolbar
on the far right of your window, resize some of the other toolbars.
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To...
Do...
Insert a bookmark
Delete a
bookmark
Delete all
bookmarks
Navigate a file
using bookmarks
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5. Use the following commands to navigate from one error to the next.
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Open the RTL and Technology views. You must have both views
open to see the object highlighted in the Technology view when
you crossprobe.
Select the HDL code you want to crossprobe, and the object is
highlighted in the RTL and Technology views. If necessary you can
right-click in the Text Editor window, and select a sheet number
from the popup menu. If you select invalid text, the popup menu
tells you crossprobing is not available.
3. To crossprobe to an FSM Viewer window:
Do this....
Click Syntax coloring.
On the Syntax Coloring form, check Use Syntax coloring.
Set the colors you want for keywords, comments, quotes,
and default text by clicking Foreground and Background
and selecting colors from the palette.
Click OK.
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To...
Do this....
Define comment
characters
Set fonts
Click Fonts.
On the Font form, set the font and the size,.
Click OK.
Set tabs
Useful Shortcuts
The following table summarizes command shortcuts to use when editing
text or checking source files:
Keyboard
Action
Alt-c
Inserts the appropriate comment character in the text file. Same as Edit>Advanced->Comment Code.
Ctrl-c
Ctrl-f
Ctrl-F2
Toggles bookmarks on and off in a text editing window. Same as Edit>Toggle Bookmarks.
Ctrl-F4
Closes the current view. Same as File->Close, or the View symbol in the
far left of the menu bar->Close.
Ctrl-F6
Displays the next view. If you are working in Workbook Mode, you see
tabs for the open views. Same as the View symbol in the far left of the
menu bar->Next.
Ctrl-g
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Keyboard
Action
Ctrl-h
In a text editing window, it lets you replace text. Same as Edit-> Replace.
In an RTL or Technology view, it enables crossprobing to Visual HDL.
Same as HDL Analyst->Visual HDL Crossprobing-> Connect.
Ctrl-n
Ctrl-o
Ctrl-p
Ctrl-ShiftF2
Ctrl-Shift-u
Ctrl-u
Ctrl-v
Ctrl-x
Ctrl-y
Ctrl-z
F3
Finds the next occurrence of the text you previously specified with Find.
Same as clicking the Find Again button on the Edit->Find form.
F5
Displays the next error in the source files. Same as Run->Next Error.
Shift-F5
Shift-F7
Shift-F8
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3. Click Add Files in the next dialog box. The Select Files to Add to Project
dialog box opens.
4. Add the source files to the project.
Make sure the Look in field at the top of the form points to the right
directory. The files are listed in the box. If you do not see the files,
check that the Files of Type field is set to display the correct file type.
For Verilog files, set it to Verilog (*.v), and for VHDL files set it to
VHDL (*.vhd). If you have mixed input files, follow the procedure
described in Using Mixed Language Source Files on page 3-17.
To add all the files in the directory at once, click the Add All button
on the right side of the form. To add files individually, click on the
file in the list and then click the Add button. Delete files from the
list to be added with the Remove and Remove All buttons.
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If you are using VHDL files, check file order. Package files must be
first on the list because they are compiled before they are used. If
you have design blocks spread over many files, make sure you
have the following file order: the file containing the entity must be
first, followed by the architecture file, and finally the file with the
configuration. File order is not important for Verilog files.
Click Next.
5. Type a name for the project. At this point, you can click Finish,
because you have finished setting up the project file.
If you want to set the technology-specific options with the wizard, you
can continue by clicking Next. For details about setting device
options, see Setting Implementation Options on page 3-22.
6. To close a project file, select the Close Project button or File->Close Project.
Click the P icon, or press the Open Project button on the left side of
the Project window. In the form that opens, double-click the
project you want from the list of recent projects.
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Select the Add Files button or Project->Add Source File to open the Select
Files to Add to Project dialog box.
Set the Look In: field at the top of the form to point to the right
directory.
If you need all or most of the files in the directory, click the Add All
button on the right side of the form and add all the files in the
directory. Delete the files you do not want with the Remove
buttons.
Click OK.
2. To delete a file from a project,
click the file in the Project window, and
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press the Delete key.
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In the Source File dialog box, set Look In to the directory where the
new file is located. The new file must be of the same type as the file
you want to replace.
If you do not see your file listed, select the type of file you need
from the Files of Type field.
Double-click the file. The new file replaces the old one in the
project list.
4. To determine how project files are saved in the project, right click on
a file in the Project view and select File Options. Set the Save File option
to either Relative to Project or Absolute Path.
5. To check the time stamp on a file, right click on a file in the Project
view and select File Options. Check the time that the file was last
modified, and then click OK.
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Select the Verilog and VHDL files you want and add them to your
project. For details about adding files to a project, see Making
Changes to a Project on page 3-16.
The files you added are displayed in the Project view. The following
figure shows the files arranged in separate folders.
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3. When you set device options (Impl Options button), specify the top-level
module. For more information about setting device options, see
Setting Implementation Options on page 3-22.
If the top-level module is Verilog, click the Verilog tab and type the
name of the module.
If the top-level module is VHDL, click the VHDL tab and type the
name of the module.
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View Project Files in Folders checked
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3. To automatically display all the files, check Show Project Library. If this is
unchecked, the Project view does not display the names of the files
until you click on the plus symbol and expand the files below.
4. To open more than one implementation in the same Project view,
check Allow Multiple Projects to be Opened.
Project 1
Project 2
5. To determine how file names are displayed, check one of the boxes in
the Project File Name Display section of the form. You can choose to
display the file name only, the relative path, or the absolute path.
Useful Shortcuts
The following table lists handy shortcuts to common project-level operations:
Keyboard
Action
Ctrl-F4
Ctrl-F6
Displays the next view. If you are working in Workbook Mode, you
see tabs for the open views. Same as the View symbol in the far left
of the menu bar->Next.
Ctrl-n
Ctrl-o
Ctrl-p
Ctrl-s
Ctrl-t
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Keyboard
Action
Ctrl-y
Ctrl-z
Delete
F1
F4
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1. Open the Options for Implementation form by clicking the Impl Options
button or selecting Project->Implementation Options, and click the Device
tab at the top if it is not already selected.
2. Select the technology, part, package, and speed. Available options
vary, depending on the technology you choose.
3. Set the device mapping options. The options vary, depending on the
technology you choose.
To set an option, type in the value or check the box to enable it.
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To set device options with a script, use the set_option Tcl command. The
following table is an alphabetical list of the device options on the form
mapped to the equivalent Tcl commands. Because the options are
technology-based, all the options will not apply to your design. All
commands begin with set_option, followed by the syntax in the column as
shown. Check the Synplify Pro Reference Manual for the most comprehensive list of options for your vendor.
Form Option
-area_delay_percent net_percentage
Cliquing (Altera)
-cliquing {true/false}
-disable_io_insertion {true/false}
-fanin_limit max_fanin
-fanout_guide fanout_value
Fanout limit
-fanout_limit limit
-maxfan_hard {true/false}
-force_gsr {true/false}
-map_logic {true/false}
Maximum terms/macrocell
(Lattice, Xilinx)
-max_terms_per_macrocell max_terms
Package
-package pkg_name
Part
-part part_name
-soft_buffers {true/false}
Speed
-speed_grade speed_grade
Technology
-technology keyword
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The equivalent Tcl set_option command options are -resource_sharing, use_fsm_explorer, -pipe, -retiming and -symbolic_fsm_compiler.
3. Specify the constraints you want to use.
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2. Specify the output files you want to generate.
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Opening SCOPE
To work with SCOPE, you must have a compiled design so that SCOPE
can access the design structure. You can still use SCOPE with an uncompiled design, but you have to type in entries manually because SCOPE
has no knowledge of the design.
1. To create a new constraint file,
Compile the design. If you do not compile the design, you can still
use SCOPE, but you can not automatically initialize the clocks
and I/O ports.
, pressing
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You can now enter constraints directly or with the wizard. Refer to
Entering and Editing Constraints Directly in SCOPE on page 3-30 or
Entering Default Constraints with the Wizard on page 3-33.
2. To open an existing file, do one of the following:
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To define...
Click...
Clock
Clock to Clock
Inputs/Outputs
Registers
Multi-cycle paths
False Paths
Attributes
Other
For object or attribute cells in the spreadsheet, click in the cell and
select from the pull-down list of available choices.
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Click the check box in the Enabled column to enable the constraint.
Make sure you have entered all the essential information for that
constraint. Scroll horizontally to check. For example, to set a clock
constraint in the Clocks tab, you must fill out Enabled, Clock, Value,
and Units. The other columns are optional.
This table summarizes the essential steps for different SCOPE
constraints:
Constraint (Tab)
Clock
Clock to Clock
Select the first clock (Clock1) and the edge (Rise or Fall).
Select the second clock (Clock2) and the edge (Rise/Fall).
Type the shortest time between the first edge condition and
the next occurrence of the other edge (Value).
Check the Enabled box.
Inputs/Outputs
Registers
Multi-cycle paths
False Paths
Attributes
Other
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Do...
Select the command from the popup (hold down the right
mouse button to get the popup) or from the Edit menu.
Find text
Select Find from the Edit or popup menus. Type the text
you want to find, and click OK.
4. Save the file by clicking the Save icon and naming the file.
The software creates a TCL constraint file (*.sdc). See Working with
Constraint Files on page 4-9 for information about the commands in
this file.
5. To apply the constraints to your design, you must add the file to the
project now or later.
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Click on one of the tabs, and select Edit->Insert Quick. The software
lists all the objects and their types.
Type values in the Value column. If you need the same value in a
number of cells, select the column of cells with the same value,
type the value in the topmost cell, and press Ctrl-d. The rest of the
selected cells (in the same column) get the same value.
2. Select a tab in SCOPE and then select Edit->Insert Wizard or press Ctrl-w
to start the wizard.
The wizard walks you through two dialog boxes, which vary slightly
depending on the kind of constraints you want to set.
3. In the first dialog box, select the design objects to which you want to
attach the constraints.
Click Next.
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4. In the second dialog box, set defaults for the selected objects.
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When you are done, the constraints appear in the SCOPE window. To
modify or add to them, do so directly in the SCOPE window (refer to
Entering and Editing Constraints Directly in SCOPE on page 3-30).
5. To apply the constraints to your design, add the file to the project
according to the procedure described in Making Changes to a Project
on page 3-16. The constraints file has a .sdc extension. See Working
with Constraint Files on page 4-9 for more information about
constraint files.
Defining Clocks
Clock frequency is the most important timing constraint, and must be set
accurately.
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1. If you have limited clock resources, define clocks that do not need a
clock buffer with the syn_noclockbuf attribute attached to an individual
port or to the entire module or architecture.
2. Define frequency by attaching a define_clock constraint to the clock.
Specify the duty cycle for asymmetrical clocks with either the duty_ns or duty_pct options.
The software infers all clocks, whether declared or undeclared, by
tracing the clock pins of the flip-flops. However, it is recommended
that you specify frequencies for all the clocks in your design. The
defined frequency overrides the global frequency. Any undefined
clocks default to the global frequency. The global frequency also
applies to any purely combinatorial paths.
3. Define frequencies for signals other than the clocks with the
syn_reference_clock attribute.
You might need to do this if your design uses an enable signal as a
clocking signal because of limited clocking resources. If the enable is
slower than the clock, defining the enable frequency separately
instead slowing down the clock frequency ensures more accuracy. If
you slow down the clock frequency, it affects all other registers
driven by the clock, and can result in longer run times as the tool
tries to optimize a non-critical path. To use this attribute,
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The software only considers the edges you specified, and ignores
any undefined edges. To avoid timing misconceptions, declare all
four possibilities (rise to rise, fall to fall, rise to fall, and fall to rise).
Register
Register
Combinatorial logic
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Do this...
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To...
Do this...
Hide/show cells
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RTL View
Technology View
Both the RTL and the Technology views have the schematic on the right
and a pane on the left that contains a hierarchical list of the objects in the
design. This pane is called the Hierarchy Browser. The bar at the top of
the window contains the name of the view, hierarchical level, and the
number of sheets in the schematic.
1. To open the RTL view do one of the following after the design has
been compiled:
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(the NAND
gate icon).
See...
Crossprobing
Flattening
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If the object you select is on another sheet of the schematic, the view
tracks to the appropriate sheet. If you have other windows open, the
selected object is highlighted in the other windows as well
(crossprobing) but the other views do not track to the correct sheet.
Selected nets that span different hierarchical levels are highlighted
on all the levels. See Crossprobing on page 3-54 for more information
about crossprobing.
2. To select more than one object, either
Finding Objects
You can always zoom in to find an object in the schematic. This procedure
shows you how to use the Hierarchy Browser in the left pane of the view
and the Find command to find objects in the RTL and Technology views.
1. To find an object using your knowledge of the design hierarchy, do
this in the left pane of the view: click the name of the net, port, or
instance you want to select.
If the object is on a lower level of hierarchy, expand the object by
clicking the plus symbol next to the higher-level object, and then
click on the object you want. The selected object is highlighted in the
schematic.
2. To find an object by name, select HDL Analyst->Find or press Control-f,
and do the following on the form:
Select the tab (at the top of the form) for the kind of object. You see
a list of all the objects of that type in the box on the left. You can
now do either of the following
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Select the objects you want from the box on the left and click the
right arrow to move the objects into the box on the right. Click OK.
Traversing Hierarchy
Schematics generally have a certain amount of design hierarchy. The
software has two methods for traversing design hierarchy: the Hierarchy
Browser in the left pane of the view, and Push/Pop mode. For additional
information, see Working with HDL Analyst on page 3-61.
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The hierarchy browser allows you to traverse and select the following:
Ports
Internal nets
Components and submodules
The browser lists the names of the objects and a symbol. A plus sign in a
square icon indicates that there is hierarchy under that object. A minus
sign indicates that the design hierarchy has been expanded. To descend
the hierarchy, click on the objects plus sign. To ascend the hierarchy,
click on the minus sign.
(two arrows
Press F2.
The cursor changes to an arrow. The arrow points in a different direction, depending on the hierarchy. The status bar at the bottom of the
window reports information about the objects over which you move
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The status bar at the bottom of the Synplify Pro window reports
information about the object currently under the cursor, including
whether the object is a primitive.
2. To push (descend) into an object, click on the hierarchical object.
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When you descend into a ROM, you can push into it one more time to
see the ROM data table. The information is in a view-only text file
called rom.info. Here is an example of the file:
Note: This data is for viewing only
ROM work.INS_ROM(first)-data[11:0]
address width: 11
data width: 12
inputs:
0: Addr[0]
1: Addr[1]
2: Addr[2]
...
outputs:
0: data[0]
1: data[1]
2: data[2]
data:
00000000000 -> 101000000001
00000000001 -> 000001100011
00000000010 -> 000001100101
...
default -> 000000000000
Similarly, you can push into a state machine. If you push into a state
machine from the RTL view, the FSM viewer opens, where you can
graphically view the transitions. For more information, see Using the
FSM Viewer on page 3-89. If you push into a state machine from the
Technology view, you see the underlying logic.
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3. To pop (ascend) a level, move your cursor to a blank area and click.
4. To exit Push/Pop mode, do one of the following:
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Next sheet
Previous sheet
A specific sheet
number
Selected items
only
A net across
sheets
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Set...
Some of these options do not take effect in the current view, but are
visible in the next view you open.
3. To control the display of labels, click any of the Label Options. You
must enable the Show Text option to access the other label options.
The following figure illustrates the label that each option controls.
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Show
Conn
Name
Show Text
4. To change the label font, click Change (on the lower right), select the
font type, size, and style on the Font form, and click OK.
5. Click OK on the Schematic Options form.
The software writes the preferences you set to the .ini file, and they
remain in effect until you change them.
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2. Adjust the RGB (red, green, blue) values in the [Schematics] section.
To Change...
Adjust...
SSC_DEFAULT_LINE
SSC_HILIT
SSC_NOSELECTED
SSC_BACKGROUND
0 =
255
0 0
200
black
255 = white
= red
200 = gray
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Managing Views
As you work on a project, you move between many views of the design.
The following guidelines help you manage the different views you have
open.
1. Toggle on View->Workbook Mode.
Below the Project view, you see tabs like the following for each open
view. The tab for the current view is on top. The symbols in front of
the view name on the tab help identify the kind of view.
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Crossprobing
Crossprobing
This section describes how to crossprobe from different views. It includes
the following:
Overview
Crossprobing within an RTL/Technology View
Crossprobing from the RTL/Technology View
Crossprobing from the Text Editor Window
Overview
Crossprobing is the process of selecting an object in one view and having
the object or the corresponding logic automatically highlighted in other
views. Highlighting a line of text, for example, highlights the corresponding logic in the schematic views. Crossprobing helps you visualize
where coding changes or timing constraints might help to reduce area or
increase performance.
You can crossprobe between the RTL view, Technology view, the FSM
Viewer, the log file, the source files, and some external text files from
place-and-route tools. However, not all objects or source code crossprobe
to other views, because some source code and RTL view logic is optimized
away during the compilation or mapping processes.
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Crossprobing
Item Highlighted/Displayed
Net in schematic
Port in schematic
Instance in schematic
Net in schematic
Port in schematic
In this example, when you select the DECODE module in the Hierarchy
Browser, the DECODE module automatically is selected in the RTL view.
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Crossprobing
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Crossprobing
To...
Conditions
RTL
Source
code
RTL
Technology
RTL
FSM
Viewer
Technology
Source
code
Technology
RTL
Open the RTL and Technology views. You must have both views
open to see the object highlighted in the Technology view when
you crossprobe.
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Crossprobing
Select a part of the HDL code in the source code window, rightclick, and select from the popup menu.
You can use this method to crossprobe from any text file with objects
that have the same instance names as in Synplify Pro. For example,
you can crossprobe from place-and-route files. See Example of
Crossprobing a Path from a Text File on page 3-58 for a practical
example of how to use crossprobing.
3. To turn off text crossprobing from the RTL and Technology views,
select Options->Schematic Options and deselect the Allow Text Crossprobing
box.
Select the column by pressing Alt and dragging the cursor to the
end of the column.
To select all the objects in the path, right-click and choose Select All
from the popup menu. Alternatively, you can select certain objects
only, as described next.
The software selects the objects in the column, and highlights the
path in the open RTL and Technology views.
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Crossprobing
Technology view
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Crossprobing
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Result
An entire RTL or
Technology view
schematic
Flatten Current
Schematic
An entire Technology
view schematic down
to Boolean logic
Flatten Current
Schematic to Gates
Selected instances in
a flattened Technology
view down to the
Boolean logic
Dissolve Selected
instances
If you use the filtering and flattening commands together, you can easily
isolate parts of your design for detailed debugging. The following figure
shows the results of using one sequence of commands.
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Selected Instances
Filter Schematic
Dissolve Selected
Instances
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Filtering Schematics
In HDL Analyst, you can isolate selected objects in their own schematic
sheet. This is very useful for analyzing portions of your design. To do this,
you use the Filter Schematic command, which takes all selected objects and
groups them together in one schematic, filtering or removing all other
objects.
This procedure shows you how to filter your schematic:
1. Select one or more objects that you want to filter. For example, you
can select the objects on a critical path.
2. Select the Filter Schematic command, using one of these methods:
Press F12.
You see just the objects you selected displayed. You can crossprobe
from this view.
LO
3. To return to the previous schematic view, select the Filter Schematic
command again.
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Do this...
Result
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Expanding Paths
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6. View instances in the critical path that have less than the worst-case
slack time:
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1. Isolate the critical path with Filter Schematic, and check the end points
of the paths that are displayed. Look at the instances. Use the
commands described in Flattening Schematic Hierarchy on
page 3-62, Filtering Schematics on page 3-64, and Extending Selected
Logic on page 3-65.
The start point can be a primary input or a flip-flop. The end point
can be a primary output or a flip-flop.
2. Determine whether there is a timing exception, like a false or
multicycle path. If this is the cause of the negative slack, set the
appropriate timing constraint.
If there are fewer start points, pick a start point to add the constraint.
If there are fewer end points, add the attribute to an end point.
3. If there are no timing exceptions and timing is within about 20% of
the goal, you can use the -improve constraints to speed up the design
and meet timing:
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4. If your design does not meet timing by 20% or more, you might need
to make structural changes. You could do this by
Useful Shortcuts
The following table lists handy shortcuts to common commands you use
in HDL Analyst:
Keyboard
Action
Ctrl-1
Displays a scaled view of the design in the RTL or Technology views. Same
as View->Normal View.
Ctrl-a
Ctrl-f
Ctrl-F4
Closes the current view. Same as File->Close, or the View symbol in the far
left of the menu bar->Close.
Ctrl-F6
Displays the next view. If you are working in Workbook Mode, you see tabs
for the open views. Same as the View symbol in the far left of the menu bar>Next.
Ctrl-l
Toggles the Zoom function off and on. Same as View->Zoom Lock.
Ctrl-k
Enables crossprobing to windows in other tools. Same as HDL Analyst >External Crossprobing Engaged.
Ctrl-r
Expands the path to show the net driver. Same as View->Go To Net Driver.
Ctrl-g
Lets you select the sheet number in a multipage schematic. Same as View>View Sheets.
Ctrl-Shift-i
Ctrl-Shift-p
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Keyboard
Action
Ctrl-Shift-n
Ctrl-y
Ctrl-z
Selects the driver for the selected net. Same as Select Net Driver from the
popup menu in the RTL or Technology views.
Expands the path to include instances connected to the selected pin. Same
as HDL Analyst->Expand in the RTL or Technology views.
Expands the path from the selected pin in the selected direction to up to the
next register or port. Same as HDL Analyst->Expand to Register/Port in the
RTL or Technology views.
F2
Changes the RTL or Technology view to show the next hierarchical level
below or above. Same as View->Push/Pop Hierarchy.
F4
Fits the entire schematic in the window. Same as View ->Full View.
F10
Pans the view in the direction you drag the cursor. Same as
View->Pan.
F11
F12
Filters the schematic to show only the selected objects and their
connectivity. Same as HDL Analyst->Filter Schematic.
Shows all the logic between the selected instances. Same as HDL Analyst>Expand Paths.
Shift-F11
Shift-F5
Shift-left
arrow
Shift-right
arrow
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The log files lists the compiled files, details of the synthesis run, a list
of errors, warnings and notes, and a number of reports. For information about the reports, see Analyzing Results Using the Log File
Reports on page 3-74.
For general information
LOabout working in an Editing window,
including adding bookmarks, see Viewing and Editing Source Files on
page 3-6.
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2. To find information in the log file, select Edit -> Find or press Ctrl-f. Fill
out the criteria in the form and click OK.
The following table lists places in the log file you can use when
searching for information.
To find...
Search for...
Notes
@N
@W and @E
Performance summary
Performance Summary
Interface Information
Resource usage
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Check the report by going to the Net Buffering Report section of the log
file.
Go to the Resource Usage Report section at the end of the log file.
Check the number and types of components used to determine if
you have used too much of your resources.
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The software automatically fills in the appropriate value from the last
synthesis run. You can check the clock requested and estimated
frequencies, the clock requested and estimated periods, the slack,
and some resource usage criteria.
3. To compare the results of two or more synthesis runs, do the
following:
If needed, resize the Tcl Script window to get a bigger log window.
Click the right mouse button in the window and select Configure
Watch from the popup.
In the log watch window, set the parameters you want to compare.
The software shows the values for the selected implementations side
by side. For more information about multiple implementations, see
Working with Multiple Implementations on page 3-104.
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Click the Errors or Warnings tab to display the errors and warnings,
respectively.
Scroll through the errors and warnings or use the Next Error and
Previous Error commands from the Run menu.
Double-click the error to open the source code file with the error.
Handling Warnings
The following cases describe some warning messages you might see in
your log file and discusses how you can deal with them.
Asynchronous Loads
Register <name> with async load is being synthesized in compatibility mode. A
synthesis/simulation mismatch is possible.
This message is generated when the software creates objects that are not
explicitly defined in the RTL code. For example, if you have a register with
an asynchronous load, the software generates a set/reset register even if
this is not defined in the code. To avoid simulation mismatches, rewrite
the code with explicit assignments.
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Verilog Example
Original Code
Revised Code
VHDL Example
Original Code
Revised Code
begin
tmp_set <= load and d0;
tmp_rst <= load and not (d0);
process (clk, tmp_rst, tmp_set)
if (tmp_rst = 1) then )
q <= 0;
elsif (tmp_set = 1) then
q <= 1;
elsif (rising_edge(clk)) then
q <=d;
end if;
end
Latch Inference
Latch generated from always block for signal <name>, probably caused by a missing
assignment in IF or CASE statement.
You see a message like this when you have not declared all the cases in a
CASE or IF statement describing purely combinatorial logic. This may be
permissible in your design, but you must check to make sure. If you do
not want a latch generated, make sure that you use a default clause or a
Verilog full_case directive for CASE statements. Make sure you always use
the else clause in IF-THEN-ELSE statements. If you require a latch, use assign
statements.
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The software generates a latch for the following example, because there is
no assignment for the case when sel2 = 11. You can fix it by adding a statement, as shown.
Latch generated because there is no
assignment for case 11:
case sel2 i
when "00" => mux41_out <= inp1;
when "01" => mux41_out <= inp2;
when "10" => mux41_out <= inp3;
when others => null;
end case;
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Revised Code
module nand2(A,B,Y1);
input A, B;
output Y1;
always @(A or B)
begin
Y1 = !(A & B);
end
endmodule
module nand2(A,B,Y1);
input A, B;
output Y1;
always @(A)
begin
Y1 = !(A & B);
end
endmodule
VHDL Example
Original Code
Revised Code
process (A)
begin
Y1 <= A nand B;
end process;
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process (A, B)
begin
Y1 <= A nand B;
end process;
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Unused Inputs
<design>|Input <input name> is unused.
You see this kind of message when an input is unused. You must check
these warnings because the software removes any logic that does not
ultimately feed a primary output.
Redundant Logic
Removing sequential element <element_name>.
During optimization, the software reduces duplicate instances, and issues
a warning message like the one above. For example, if you have one
instance driving four other instances, the software uses just one driver
instead of four copies. Check your design and ensure that the optimization is appropriate. If you want to keep four copies of the driver, you must
specify this explicitly in the code with the syn_preserve directive.
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Verilog Example
Original Code
VHDL Example
Original Code
entity dff is
port (data1, clk : in bit;
q1, q2, q3, q4 : out bit);
end dff;
architecture rtl of dff is
begin
process (clk) begin
if (clk event and clk = 1) then
q1 <= data1; q2 <=data1; q3 <= data1;
q4 <= data1;
end if;
end process;
end rtl;
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entity dff is
port (data1, clk : in bit;
q1, q2, q3, q4 : out bit);
attribute syn_preserve : boolean;
attribute syn_preserve of q1, q2, q3,
q4 : signal is true;
end dff;
architecture rtl of dff is
begin
process (clk) begin
if (clk event and clk = 1) then
q1 <= data1; q2 <=data1; q3 <= data1;
q4 <= data1;
end if;
end process;
end rtl;
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Encoding Style
Up to 4
Sequential
5-24
Onehot
> 24
Gray
The FSM Compiler also writes a log file that contains a description of
each state machine extracted and the set of reachable states for each
state machine.
4. Select View->View Log File and check the log file for descriptions of the
state machines and the set of reachable states for each one. You see
text like the following:
Extracted state machine for register cur_state
State machine has 7 reachable states with original encodings of:
0000001
0000010
0000100
0001000
0010000
0100000
1000000
....
original code -> new code
0000001 -> 0000001
0000010 -> 0000010
0000100 -> 0000100
0001000 -> 0001000
0010000 -> 0010000
0100000 -> 0100000
1000000 -> 1000000
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In the RTL view you see the FSM primitive with one output for
each state.
In the fsm.info text file, you see the state transition information.
Enable the FSM Compiler by checking the box in the button panel
of the Project window.
VHDL
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Run synthesis.
The software automatically recognizes and extracts all the state
machines, except the ones you marked. It optimizes the FSMs it
extracted from the design, honoring the syn_encoding attribute. It
writes out a log file that contains a description of each state machine
extracted, and the set of reachable states for each FSM.
2. If you have many state machines you do not want optimized, do this:
VHDL
For state machines with specific encoding styles, set the encoding
style with the syn_encoding attribute, as described in Specifying
FSMs with Attributes and Directives on page 3-87. When
synthesized, these registers have the specified encoding style.
Run synthesis.
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Attribute
HDL
SCOPE
syn_encoding
Yes
Yes
syn_state_machine=1
Yes
No
syn_state_machine=0
Yes
No
syn_preserve=1
Yes
No
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The syn_encoding attribute defines an encoding style for the state machine.
Both the FSM Compiler and the FSM Explorer honor this setting. The
different values for this attribute are briefly described here:
sequential
Use this value if area is important, because it is one of the smallest
encoding styles. The software uses this style by default if there are
less than five states. In this style, more than one bit of the state
register can change at a time, so the value must be decoded to determine the state. This style could be faster than a onehot style if you
have a large output decoder following an FSM.
onehot
This style is usually the fastest, and is well-suited to most FPGA
architectures because it requires the least state decode logic. Speed
could be an issue as FPGAs usually have a large number of flip-flops.
In this style, each state variable has one bit set, and only one bit of
the state register changes at a time.
gray
With this style, only one bit of the state register changes at a time,
but because more than one bit can be hot, the value must be
decoded to determine the state. This style could be faster than a
onehot style if you have a large output decoder following an FSM.
safe
If recovery from an invalid state is important, use this value in
conjunction with onehot, sequential, or gray, to force the state machine
to reset. For example, an alpha particle hit in a hostile operating
environment could cause a register to change spontaneously. When
you specify safe, the state machine can be reset from an unknown
state to its reset state. You specify safe before the other value.
Verilog
VHDL
Tcl Constraint
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Select the FSM instance, click the right mouse button and select
View FSM from the popup menu.
Push down into the FSM instance using the Push/Pop icon or the
command from the popup menu.
The FSM viewer opens. The viewer consists of a transition bubble
diagram and a table for the encodings and transitions. If you used
Verilog to define the FSMs, the viewer displays binary values for the
state machines if you defined them with the define keyword, and
actual names if you used the parameter keyword.
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Do...
This figure shows you the mapping information for a state machine.
The Transitions tab shows you simple equations for conditions for each
state. The RTL Encodings tab has a State column that shows the state
names in the source code, and a Registers column for the corresponding RTL encoding. The Mapped Encoding tab shows the state
names in the code mapped to actual values.
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Mapped Encoding
RTL Encoding
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Similarly, you can check the relationship between two or more states
by selecting the states, filtering them, and checking their properties.
4. To view the properties for a state,
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5. To view the FSM description in text format, select the state machine
in the RTL view and View FSM Info File from the right mouse popup.
This is an example of the FSM Info File, statemachine.info.
State Machine: work.Control(verilog)-cur_state[6:0]
No selected encoding - Synplify Pro will choose
Number of states: 7
Number of inputs: 4
Inputs:
0: Laplevel
1: Lap
2: Start
3: Reset
Clock: Clk
Transitions: (input, start state, destination state)
-100 S0 S6
--10 S0 S2
---1 S0 S0
-00- S0 S0
--10 S1 S3
-100 S1 S2
-000 S1 S1
---1 S1 S0
--10 S2 S5
-000 S2 S2
-100 S2 S1
---1 S2 S0
-100 S3 S5
-000 S3 S3
--10 S3 S1
---1 S3 S0
-000 S4 S4
--1- S4 S0
-1-- S4 S0
---1 S4 S0
-000 S5 S5
-100 S5 S4
--10 S5 S2
---1 S5 S0
1--0 S6 S6
---1 S6 S0
0--- S6 S0
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Useful Shortcuts
The following table lists handy shortcuts to use in the FSM Viewer:
Keyboard
Action
Ctrl-++
Shows only the output transitions for the selected states in an FSM
bubble diagram. Same as View->Filter->Selected in the FSM viewer.
Ctrl-+-
Shows only the input transitions for the selected states in an FSM
bubble diagram. Same as View->Filter->Selected in the FSM viewer.
Ctrl-+*
Ctrl-1
Ctrl-Enter
Ctrl-F4
Ctrl-F6
Displays the next view. If you are working in Workbook Mode, you see
tabs for the open views. Same as the View symbol in the far left of the
menu bar->Next.
Ctrl-l
Toggles the Zoom function off and on. Same as View->Zoom Lock.
Ctrl-u
Ctrl-y
Ctrl-z
F4
Fits the entire diagram in the window. Same as View ->Full View.
F10
Pans the view in the direction you drag the cursor. Same as
View->Pan.
F11
Shift-F11
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For example:
entity simpledff is
port(q: out bit_vector(7 downto 0);
d : in bit_vector(7 downto 0);
clk : in bit);
attribute syn_noclockbuf of clk :signal is true;
For information about the syntax of attributes and directives, see the
Synplify Pro Reference Manual.
3. If you do not use the predefined attributes package, define attributes
after design unit declarations as follows:
<design_unit_declaration>;
attribute <att_name> : <data_type>;
attribute <att_name> of <object_name>:<object_kind> is <value>;
If you do not use the attributes package, you must redefine the
attributes each time you include them in source code. For example:
entity simpledff is
port(q: out bit_vector(7 downto 0);
d : in bit_vector(7 downto 0);
clk : in bit);
attribute syn_noclockbuf : boolean;
attribute syn_noclockbuf of clk :signal is true;
4. Add the source file to the project.
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Drag the object to which you want to attach the attribute from the
RTL or Technology views to the Object column in SCOPE.
Select the type of object in the Object Filter column, and then select
an object from the list of choices in the Object column.
Type the name of the object in the Object column. If you do not
know the name, use the Find command or the Object Filter column.
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If you specified the object first, you can now specify the attribute.
The list shows only the valid attributes for the type of object you
selected.
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4. Specify the attribute and the value in the box. The bottom left of the
form shows a short description of the selected attribute and lists the
type of value required.
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Optimizing Results
Optimizing Results
You can optimize your results with attributes and directives, some of
which are specific to the technology you are using. For a complete list of
all the directives and attributes, see the Reference Manual. This section
describes the following:
Controlling Flattening
Optimization flattens hierarchy. To control the flattening, use the syn_hier
attribute as described here. You can also use the attribute to prevent
flattening, as described in Preserving Hierarchy on page 3-103.
1. Attach the syn_hier attribute to the module or architecture you want
to preserve. You can also add the attribute in SCOPE. If you use
SCOPE to enter the attribute, make sure to use the v: syntax.
2. Set the attribute value:
To...
Value...
flatten
remove
flatten, remove
soft
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Optimizing Results
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Preventing Optimization
Preventing Optimization
You can use attributes and directives to specify objects or hierarchy that
you want to preserve during synthesis.
Attach...
Result
Nets
Shared registers
Sequential
components
syn_preserve on reg or
module (Verilog), signal or
architecture (VHDL)
FSMs
syn_preserve on reg or
module (Verilog), signal
(VHDL)
Instantiated
components
syn_noprune on module or
component (Verilog),
architecture or instance
(VHDL)
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Preventing Optimization
Preserving Hierarchy
The synthesis process includes cross-boundary optimizations that can
flatten hierarchy. To override these optimizations, use the syn_hier
attribute as described here. You can also use this attribute to direct the
flattening process as described in Controlling Flattening on page 3-100.
1. Attach the syn_hier attribute to the module or architecture you want to
preserve. You can also add the attribute in SCOPE. If you use SCOPE
to enter the attribute, make sure to use the v: syntax.
2. Set the attribute value:
To...
Value...
Preserve the interface but allow cell packing across the boundary
firm
hard
macro
flatten, firm
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The new implementation uses the same source code and constraint
files. It copies some files from the previous implementation: the .tlg
log file, the .srs RTL netlist file, and the <design>_fsm.sdc file generated by FSM Explorer. It also keeps a repeatable history of the
synthesis runs.
3. To open more than one implementation in the same Project view,
check Allow Multiple Projects to be Opened.
Project 1
Project 2
4. Run synthesis again with different settings. For example, you might
want to try a different part or experiment with a different frequency.
LO current implementation in the project view.
A green arrow marks the
The Log Watch Window monitors the current implementation. If you
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Use the Log watch window to compare selected criteria. Make sure
to set the implementations you want to compare with the Configure
Watch command. See Using the Log Watch Window on page 3-74 for
details.
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Design Guidelines
Design Guidelines
The software automatically makes efficient tradeoffs to achieve the best
results. However, you can optimize your results by using the appropriate
control parameters. This section describes general design guidelines for
optimization. The topics have been categorized as follows:
For FSMs coded in VHDL using enumerated types, use the same
encoding style (syn_enum_encoding attribute value) on both the state
machine enumerated type and the state signal. This is because
discrepancies in the type of encoding can negatively affect the final
circuit.
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Design Guidelines
Increase the fanout limit when you set the implementation options. A
higher limit means less replicated logic and fewer buffers inserted
during synthesis, and a consequently smaller area. In addition, as
P&R tools typically buffer high fanout nets, there is no need for
excessive buffering during synthesis.
For designs with large FSMs, use the gray or sequential encoding
styles, because they typically use the least area.
If you are mapping into a CPLD and not meeting area requirements,
set the default encoding style for FSMs to sequential instead of onehot.
For small CPLD designs (less than 20K gates), you might improve
area by using the syn_flatten attribute. With this attribute, the software
optimizes across hierarchical boundaries and creates smaller
designs.
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Design Guidelines
Use realistic design constraints, about 10 - 15% of the real goal. Over
constraining your design can be counter-productive because you can
get poor implementations. Use clock boundary, false path, and
multicycle path constraints to make the constraints realistic.
Run a second iteration using the -improve or -route options with the
appropriate timing constraint. Use the -improve option if Synplify Pro
and the P&R tool both report the same critical path.
This forces the software to restructure the design to meet clock
frequency goals. Use the -route option if the P&R tool reports a
different critical path. With this option, the software adds route delay
to its calculations when trying to meet the clock frequency goal. In
both cases, use realistic values for the constraints.
For FSMs, use the onehot encoding style, because it is often the
fastest implementation. If a large output decoder follows an FSM,
gray or sequential encoding could be faster.
If you saw warnings about feedback muxes being created for signals
when you compiled your source code, make sure to assign set/resets
for the signals. This improves performance by eliminating the extra
mux delay on the input of the register.
Make sure that you pass your timing constraints to the place-androute tools, so that they
LOcan use the constraints to optimize timing.
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Output Netlist
P&R Tool
Actel
EDIF (*.edn)
Designer Series
Actel ProAsic
EDIF (*.edn)
ASICmaster
Altera Flex
EDIF (*.edf)
MAX+PLUSII
Altera Apex
Verilog (*.vqm)
Quartus, Quartus II
Altera Max
EDIF (*.edf)
MAX+PLUSII
Atmel
EDIF (*.edf)
Figaro
Cypress
VHDL (*.vhn)
Warp
Lattice
EDIF (*edf)
ispExpert
Lattice Mach
ispExpert
Lucent
EDIF (*edn)
ORCA Foundry
QuickLogic
*.qdf
SpDE
Triscend
EDIF (*.edf)
FastChip
Xilinx CoolRunner
Xilinx M2-1i
Xilinx Virtex
EDIF (*edf)
Xilinx M2-1i
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Chapter 4
Advanced Techniques
This chapter covers topics for the advanced user:
Batch Mode on page 4-2
Working with Tcl Scripts and Commands on page 4-4
Working with Constraint Files on page 4-9
Defining Black Boxes for Synthesis on page 4-15
Defining State Machines for Synthesis on page 4-24
Inferring RAMs on page 4-41
Classic Interface on page 4-52
Working with Altera Designs on page 4-54
Working with Xilinx Designs on page 4-59
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Batch Mode
Batch Mode
Batch mode is a command-line mode where you run scripts from the
command line. You might want to set up multiple synthesis runs with a
batch script. You can run in batch mode if you have a floating license, but
not with a node-locked license.
Batch scripts are in Tcl format. For more information about Tcl scripts,
see Working with Tcl Scripts and Commands on page 4-4 or the Synplify
Pro Reference Manual.
This section describes the following operations:
Running Batch Mode on a Project File
Running Batch Mode with a Tcl Script
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Batch Mode
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4-3
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2. To run a Tcl script, either type source Tcl_scriptfile in the Tcl script
window, or do the following:
Select File -> Run Tcl Script.
Select the Tcl file you want and click Open.
The software runs the selected script and executes the commands in
it. For more information about Tcl scripts, refer to the following
sections.
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Set of frequencies
to try
Foreach loop
set try_freq {
20.0
24.0
Synplify Pro Tcl commands that set
28.0
the frequency option, create log
32.0
files for each run, and run synthesis
36.0
40.0
)
foreach frequency $try_freq {
set_option -frequency $frequency
project -log_file $frequency.srr
project -run}
Foreach loop
set try_tech {
FLEX8000
FLEX10K
Synplify Pro Tcl commands that set
ACT3
the technology option and run
XC4000
synthesis.
XC4000E
XC400EX
)
foreach technology $try_tech {
set_option -technology $technology
project -run}
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3. Create a new project for the top level with project -new.
4. Add the top-level data:
Add source files with add_file -vhdl or add_file -verilog.
Add constraint files with add_file -constraint.
Set the top-level options with set_option.
Set the output file information with project -result_file and
project -log_file.
Save the project with project -save.
Run the project with project -run.
When the script has finished running, the entire design is synthesized, beginning with the lower-level logic blocks specified in the
sourced files, and then the top level.
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Object
i:
Instance names
p:
b:
n:
Net names
Use the following syntax for instance, port, and net names in
VHDL modules, where v: identifies it as a view object, lib is the
name of the library, cell is the name of the design entity, view is a
name for the architecture, prefix is a prefix to identify objects
with the same name, and object_name is an instance path with
periods as separators. You only need view if there is more than
one architecture for the design. See the preceding table for the
prefixes for different objects.
v:cell[.view] [prefix:]object_name
You can use the * and ? wildcards to match names. The asterisk
matches any number of characters, and the question mark matches
a single character. These characters do not match periods that are
used as hierarchy separators. For example, you can use the following
to identify all bits of the statereg instance in the statemod module:
statemod | i: statereg[*]
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Use...
Clock frequencies
define_clock
syn_reference_clock
(attribute)
define_clock_delay
define_clock_delay
define_clock_delay
define_reg_input_delay
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To define...
Use...
define_reg_output_delay
define_input_delay
define_output_delay
define_multicycle_path
define_false_paths
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Vendor Constraint
Altera *.tcl File
define_input_delay
define_output_delay
define_clock
Frequency
global frequency
Frequency
duty_cycle
DUTY_CYCLE = %_of_clk_period
altera_chip_pin_lc
define_input_delay
define_output_delay
define_clock
global frequency
FREQUENCY = freq
altera_chip_pin_lc
define_input_delay
define_output_delay
define_clock
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Vendor Constraint
define_multicycle_path
define_false_paths
define_input_delay
define_output_delay
define_clock
define_multicycle_path
define_false_path
4. For Lucent designs, you must copy the constraints into the Lucent
.prf file.
Open the ORCA Foundry place-and-route tool, and run the Map
stage. This creates a .prf file.
Copy the .lp file created by the Synplicity software and paste it at
the end of the .prf file. Do not overwrite the .prf file.
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5. After synthesis, merge the black box netlist and the synthesis results
file using the method specified by your vendor.
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Use...
syn_tpd
syn_tsu
syn_tco
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Clk buffer
Pad
black_box_pad_pin
syn_isclock
1. To specify that a clock pin on the black box has access to global clock
routing resources, use syn_isclock.
Depending on the technology, different clock resources are inserted.
In Xilinx, the software inserts BUFG, for Actel it inserts CLKBUF, and
for QuickLogic, it inserts Q_CKPAD.
2. To specify that the software need not insert a pad for a black box pin,
use black_box_pad_pin.
Use this for technologies that automatically insert pad buffers for the
I/Os like Xilinx, some Altera families, Actel, Lattice, QuickLogic,
Lucent, and Triscend.
3. To define a tristate pin so that you do not get a mixed driver error
when there is another tristate buffer driving the same net, use
black_box_tri_pins.
4. To ensure consistency between synthesized black box netlist names
and the names generated by third party tools or IP cores, use the
following attributes (Xilinx only):
syn_edif_bit_format
syn_edif_scalar_format
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Startup
xc_isgr
R
Black Box
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The file name must be the same as the module name. Both STAMP
files have the same name, with different extensions. Although the
STAMP format allows multiple .data files, you can only use one file
with the synthesis software. For information about STAMP files, see
the Synopsys documentation.
4. Add the .mod and .data files to the project, using the Project-> Add
Source File command.
In the Project view, the software creates a separate folder and adds
the files to it.
5. Run synthesis.
Synplify Pro translates the STAMP information into a proprietary
internal format. It automatically links the converted model to the rest
of the design and uses it during synthesis.
Limitations
Because Synplify Pro is a synthesis tool, not a timing tool, it only supports
a subset of the STAMP capabilities. The following are some of the
currently unsupported timing features:
Multiple .data files for different operating conditions
Conditional arcs
Max/min timing arcs
Internal timing points
Modes
Models other than worst-case timing
Models using multiple clocks or edges
Constraints other than setup/hold and posedge/negedge
Generated clocks
Internal pins
Buses
Scaling information
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This example shows how to set the current state value with define
statements:
define state1 2h1
define state2 2h2
...
current_state = state2;
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VHDL
VHDL
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4. Select View->View Log File and check the log file for the descriptions.
The following extract shows the state machine and the reachable
states as well as the encoding style, gray, set by FSM Explorer.
Extracted state machine for register cur_state
State machine has 7 reachable states with original encodings of:
0000001
0000010
0000100
0001000
0010000
0100000
1000000
....
Adding property syn_encoding, value "gray", to instance
cur_state[6:0]
List of partitions to map:
view:work.Control(verilog)
Encoding state machine work.Control(verilog)cur_state_h.cur_state[6:0]
original code -> new code
0000001 -> 000
0000010 -> 001
0000100 -> 011
0001000 -> 010
0010000 -> 110
0100000 -> 111
1000000 -> 101
5. Check the state machine implementation in the RTL and Technology
views and in the FSM viewer.
For information about the FSM viewer, see Using the FSM Viewer on
page 3-89.
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Pipelining
Pipelining
Pipelining is the process of splitting logic into stages so that the first stage
can begin processing new inputs while the last stage is finishing the
previous inputs. This ensures better throughput and faster circuit performance. If you have a Xilinx Virtex design, you can use another, related
technique to improve performance: retiming. See Retiming on page 4-34
for details.
For pipelining, The software splits the logic by moving registers into the
module:
Without Pipelining
Data
Reg
LUT
LUT
LUT
Reg
LUT
Reg
Reg
LUT
LUT
Reg
LUT
LUT
Reg
Clk
After Pipelining
Data
Clk
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Pipelining
[lefta:0] a_aux;
[leftb:0] b_aux;
[lefta+leftb+1:0] res /* synthesis syn_pipeline=1 */;
[lefta+leftb+1:0] res1;
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Pipelining
The value 1 indicates that pipelining is turned on. For detailed information about Verilog attributes and examples of the files, see the
Synplify Pro Reference Manual.
3. For VHDL source code, add the syn_pipeline attribute to a register as
an attribute:
architecture beh of onereg is
signal temp1, temp2, temp3,
std_logic_vector(31 downto 0);
attribute syn_pipeline : boolean;
attribute syn_pipeline of temp1 : signal is true;
attribute syn_pipeline of temp2 : signal is true;
attribute syn_pipeline of temp3 : signal is true;
For detailed information about VHDL attributes and sample files, see
the Reference Manual.
4. Run synthesis.
The software looks for registers with the syn_pipeline attribute and
pushes them into the previous multiplier or ROM.
5. Check that the registers you marked were pipelined. Check the log
file (*.srr) and the RTL view.
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Pipelining
Select the register and press F12 to filter the schematic view.
In the new schematic view, select the output and type e (or select
Expand from the popup menu. Check that the register is suitable
for pipelining.
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Retiming
If you created a new constraints file, add the constraints file to the
project.
4. Run synthesis.
The software looks for registers with the syn_pipeline attribute and
pushes them into the previous module.
5. Check that the registers you marked were pipelined. Check the log
file (*.srr) and the RTL view.
Retiming
Retiming is a powerful technique for improving the timing performance of
sequential circuits. Retiming automatically moves registers (register
balancing) across combinatorial gates or LUTs to improve timing while
ensuring identical behavior as seen from the primary inputs and outputs
of the design. Retiming moves registers across gates or LUTs, but does not
change the number of registers in a cycle or path from a primary input to
a primary output. However, it can change the total number of registers in
a design.
The Synplify Pro retiming algorithm retimes only edge-triggered registers.
It does not retime level-sensitive latches. Currently you can use retiming
for the Xilinx Virtex families only (Virtex, VirtexE, Spartan 2, and
Virtex 2).
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Retiming
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Retiming
Retiming Example
The following example shows two levels of logic between the registers and
the output, and no levels of logic between the inputs and the registers.
The next figure shows the results of retiming the three registers at the
input of the OR gate. The levels of logic from the register to the output are
reduced from two to one. The retimed circuit has better performance than
the original circuit. Timing is improved by transferring one level of logic
from the critical part of the path (register to output) to the non-critical
part (input to register).
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Inserting Probes
Retiming Report
The retiming report is part of the log file, and includes the following information:
The number of registers added, removed, or untouched by retiming.
Registers added by retiming have a _ret suffix added to their names.
Names of the registers that were moved by retiming and which no
longer exist in the Technology view.
Names of the registers created as a result of the retiming moves and
which did not exist in the RTL view.
Inserting Probes
Specifying Probes in the Source Code
To specify probes in the source code, you must add the syn_probe attribute
to the net. You can also add probes interactively, using the procedure
described in Adding Probe Attributes Interactively on page 4-40.
1. Open the source code file.
2. For Verilog source code, attach the syn_probe attribute as a comment
on any internal signal declaration:
module alu(out, opcode, a, b, sel);
output [7:0] out;
input [2:0] opcode;
input [7:0 a, b;
input sel;
reg [7:0] alu_tmp /* synthesis syn_probe=1 */;
reg [7:0] out;
//Other code
The value 1 indicates that probe insertion is turned on. For detailed
LO attributes and examples of the files, see
information about Verilog
the Synplify Pro Reference Manual.
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Inserting Probes
To define probes for part of a bus, specify where you want to attach
the probes; for example, if you specify reg [1:0] in the previous code,
the software only inserts two probes.
3. For VHDL source code, add the syn_probe attribute as follows:
architecture rtl of alu is
signal alu_tmp : std_logic_vector(7 downto 0) ;
attribute syn_probe : boolean;
attribute syn_probe of alu_tmp : signal is true;
--other code;
For detailed information about VHDL attributes and sample files, see
the Synplify Pro Reference Manual.
4. Run synthesis.
The software looks for nets with the syn_probe attribute and creates
probes and I/O pads for them.
5. Check the probes in the log file (*.srr) and the Technology view.
This figure shows some probes and some probe entries in the log file.
Adding property syn_probe, value 1, to net pc[0]
Adding property syn_probe, value 1, to net pc[1]
Adding property syn_probe, value 1, to net pc[2]
Adding property syn_probe, value 1, to net pc[3]
....
@N|Added probe pc_keep_probe_1[0] on pc_keep[0] in
eight_bit_uc
@N|Also padding probe pc_keep_probe_1[0]
@N|Added probe pc_keep_probe_2[1] on pc_keep[1] in
eight_bit_uc
@N|Also padding probe pc_keep_probe_2[1]
@N|Added probe pc_keep_probe_3[2] on pc_keep[2] in
eight_bit_uc
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Inferring RAMs
Inferring RAMs
There are two methods of handling RAMs: instantiation and inference.
The software can automatically infer RAMs if they are structured correctly
in your source code. For details, see the following sections:
Inference vs. Instantiation
Structuring RAMs for Inference
Coding Altera RAMs for Inference
Coding Xilinx Block RAMs for Inference
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Inferring RAMs
Instantiation
Advantages
Portable coding style
Automatic timing-driven synthesis
No additional tool dependencies
Advantages
Most efficient use of the RAM primitives of
a specific technology
Supports all kinds of RAMs
Limitations
Glue logic to implement the RAM might
result in a sub-optimal implementation.
Can only infer synchronous RAMs
No support for address wrapping
No support for RAM enables, except for
write enable
Pin name limitations means some pins are
always active or inactive
Limitations
Source code is not portable because it is
technology-dependent.
Limited or no access to timing and area
data if the RAM is a black box.
Inter-tool access issues, if the RAM is a
black box created with another tool.
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Inferring RAMs
2. For a single-port RAM, make the address for indexing the write-to the
same as the address for the read-from. The following figure and code
example illustrate how Synplify Pro infers a single-port RAM.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity ramtest is
port (q : out std_logic_vector(3 downto 0);
d : in std_logic_vector(3 downto 0);
addr : in std_logic_vector(2 downto 0);
we : in std_logic;
clk : in std_logic);
end ramtest;
architecture rtl of ramtest is
type mem_type is array (7 downto 0) of std_logic_vector
(3 downto 0);
signal mem : mem_type;
begin
q <= mem(conv_integer(addr));
process (clk, we, addr) begin
if rising_edge(clk) then
if (we = '1') then
mem(conv_integer(addr)) <= d;
end if;
end if;
end process;
end rtl;
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Classic Interface
If you do not want to generate glue logic for dual port RAMs, either
register the RAM output or set syn_ramstyle to no_rw_check. Use
this attribute value only if you do not care about a read/write
check.
4. To implement RAMs using distributed memory in Xilinx
technologies, you can set syn_ramstyle to select_ram. If you do not set
this value explicitly, the software automatically uses this value,
because it is the default.
Classic Interface
For the look and feel of the Synplify classic interface, you can run Synplify
Pro in this mode.
1. To switch to the classic interface, select Options->Project View Options.
2. Check the box for Synplify Classic View, and click OK.
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Classic Interface
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Instantiating LPMs
Altera LPMs (Library of Parameterized Modules) are technology-independent logic functions that are parameterized for scalability and adaptability. There are two ways to instantiate LPMs in your source code: as
black boxes, or by using prepared components. The first method can be
used to instantiate any Altera LPM, but requires more coding. The second
method, the prepared components method, uses generics instead of
attributes to specify design parameters. It is simpler to use, but you can
not use it on all LPMs. In addition, you can only use this method with
VHDL source code.
1. To instantiate an LPM as a black box in Verilog or VHDL, do the
following:
Define a black box for the LPM.
Assign LPM-specific attributes like LPM_TYPE, LPM_WIDTH, and
LPM_WIDTHAD.
Instantiate the LPM in the higher-level module.
For details about handling black boxes, see Defining Black Boxes for
Synthesis on page 4-15.
2. To instantiate an LPM using the prepared components method, do
this in VHDL:
Specify the appropriate library and use clauses.
Instantiate the components.
Assign the ports and values for the generics.
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Inferencing ROMs
The software automatically infers ROMs from CASE statements in the RTL
code. This procedure shows you how to control the implementation of
ROM in APEX and FLEX designs with the syn_romstyle attribute.
1. To implement the ROM structure as a block, do the following:
Apply the syn_romstyle attribute to the signal output value.
Set the value of the attribute to block_ROM. You can set the
attribute in the source code, SCOPE, or directly in the constraint
file. See Adding Attributes and Directives on page 3-95 for
information.
Format
Example
Verilog
VHDL
Run synthesis.
The software implements all small ROMs (less than seven address
bits) as logic. It implements the larger ROM structures as extended
system blocks (ESBs) in APEX designs and extended array blocks
(EABs) in FLEX designs.
If you have to conserve ROM resources, you can turn off ROM implementation globally with the altera_auto_use_esb and altera_auto_use_eab
attributes, and then specify the ROMs you want implemented as
block ROMs with the syn_romstyle attribute.
2. To implement the ROM structure as discrete logic, do the following:
Apply the syn_romstyle attribute to the signal output value.
Set the value of the attribute to logic.
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Format
Example
Verilog
VHDL
Run synthesis.
The software implements all small ROMs (less than seven address
bits) and all other ROMs with this attribute as discrete logic primitives instead of blocks.
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Example
Verilog
VHDL
define_global_attribute syn_useioff 1
Example
Verilog
VHDL
entity test is
port (d : in std_logic_vector (3 downto 0);
clk : in std_logic;
q : out std_logc_vector (3 downto 0);
attribute syn_useioff : boolean;
attribute syn_useioff of q : signal is true;
end test;
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xc_map Value
XC4000, Spartan
fmap
hmap
4
3
Virtex
lut
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If you do not specify the attribute, the software assumes that the
attribute is set with a value of select_srl, which maps the components
to SRL16 primitives. When you specifically set the attribute to registers, the components are implemented as registers.
3. Run synthesis.
After compilation, the software displays the components as seqShift
components in the RTL view. The RTL component has the following
pins: raddr (read address), data (data in), we (write enable), clk (clock),
a_rst (asynchronous reset), s_rst (synchronous reset), and dout (data
out). Currently, the a_rst and s_rst pins are not used. The following
figure shows the seqshift component in the RTL view.
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VHDL Example
This is a VHDL example of a shift register with no resets. It has four 8-bit
wide registers and a 2-bit wide read address. Registers shift when the
write enable is 1.
library IEEE;
use IEEE.std_logic_1164.all;
entity srltest is
port ( inData: std_logic_vector(7 downto 0);
clk, en : in std_logic;
outStage : in integer range 3 downto 0;
outData: out std_logic_vector(7 downto 0)
);
end srltest;
architecture rtl of srltest is
type dataAryType is array(3 downto 0) of std_logic_vector(7
downto 0);
signal regBank : dataAryType;
begin
outData <= regBank(outStage);
process(clk, inData)
begin
if (clk'event and clk = '1') then
if (en='1') then
regBank <= (regBank(2 downto 0) & inData);
end if;
end if;
end process;
end rtl;
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Verilog Example
module test_srl(clk, enable, dataIn, result, addr);
input clk, enable;
input [3:0] dataIn;
input [3:0] addr;
output [3:0] result;
reg [3:0] regBank[15:0];
integer i;
always @(posedge clk) begin
if (enable == 1) begin
for (i=15; i>0; i=i-1) begin
regBank[i] = regBank[i-1];
end
regBank[0] = dataIn;
end
end
assign result = regBank[addr];
endmodule
LO
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Module Synthesis
Planning
Final Assembly
Top-level Synthesis
Simulation
Module P&R
Top-level P&R
Design Entry
The steps in each phase are briefly described in the following sections,
with emphasis on the tasks done with Synplify Pro.
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Planning
Using the team design model, the team leader defines the HDL top-level
design, the global design constraints, and determines the positions of
each of the modules by doing some preliminary floorplanning. The team
leader partitions the design into smaller self-contained modules or structures, and assigns the modules to different teams or designers. This
planning stage can be merged with the next stage of Design Entry.
1. Partition the design into smaller self-contained modules or
structures.
2. Use initial floorplanning to assign them to specific physical locations
on the target device.
3. Allocate global resources like clock buffers.
4. Assign each module to a designer or a design team.
This modular flow uses a simple example to illustrate the flow. The design
consists of a top-level design with two lower-level modules, mux and flop.
See Design Files and Area Floorplanning on page 4-81 for the files.
Top-Level Design
Flop
Mux
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connections between I/O ports and modules. For the top-level file
used as an example here, see Top-Level Design File on page 4-82.
A file for each module. This file is a black box wrapper for the
module and lists the inputs and outputs. It also contains
attributes to declare the module a black box (syn_black_box) and set
the physical location of the module, based on initial floorplanning
(xc_modular_region). For information about generating the area
numbers for xc_modular_region, see Determining the Area Range
for xc_modular_region on page 4-85. For the module files used in
this example, see Module Mux File on page 4-83 and Module Flop
File on page 4-84.
A top-level constraint file. You can use SCOPE to set global clock
constraints. If there is a conflict between the global clock
constraint and a clock constraint set on a module, the global clock
constraint is used.
Synthesize the design. Make sure you set Technology to Xilinx Virtex or
Virtex2 and check the Modular Flow checkbox on the Device tab of the
Implementation Options form.
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When you check Modular Flow, the software generates the directory
structure needed for the flow in the Xilinx place-and-route tool.
The software creates top-level .edif and .ncf files, which it places in the
top-level directory. It issues warnings if it finds a module that is
instantiated more than once at the top level.
2. Generate a top-level .ngo file that contains the top-level area
constraints.
Start the Xilinx place-and-route tool.
Go to the top_level directory and run ngdbuild in initial mode. Use
this syntax and type the command at the command line:
ngdbuild -modular initial <toplevel>.edf
To run our example, the command is ngdbuild -modular initial
example_top.edf. This command generates a .ngd file and a .ngo file
that contains the top-level area constraints for place and route.
3. Archive the directories, and give each designer or design team
working on a module a copy of these files.
LO
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Active Implementation
The active implementation phase starts after the designer finishes the
module-level design. This phase consists of module synthesis, top-level
synthesis, and module-level placement and routing.
Module Synthesis
The advantage to using the modular design flow is the elimination of
dependencies and the need for all teams to be done before an individual
team can synthesize a module design with the overall design. Individual
teams can synthesize their assigned modules with the top-level design
without depending on the progress of other design teams. It allows the
module designer to iterate the module design with the top level more
frequently, and evolve the overall design and separate modules more
efficiently.
Although this is module-level synthesis, you actually synthesize your
module design with the top-level design, the top-level constraint file,
wrapper files for other modules, and optional module-level constraint
files. To use our example, if you are assigned to mux, you create HDL
source code for it. You synthesize mux using the project created by the
team leader, replacing the original mux wrapper file with the design you
created. The project file includes the top-level design source code and
constraint file, as well as the wrapper file for the flop module, which
remains a black box from your perspective.
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1. Start with the project set up by the team leader and set device
options in Synplify Pro with Project->Implementation Options. The module
file is now updated to contain the design.
On the Device tab, set the device to Xilinx Virtex or Xilinx Virtex2.
Check the Modular Flow checkbox.
On the Implementation Results tab, check that the name of the output
netlist matches the name of the module you are actively
synthesizing as it occurs in the top-level EDIF file, so that the
name of the netlist for this module and the name in the top-level
EDIF file are the same. For example, the name for the output file
for mux must be mux.edf to match the name of the component in
the top-level EDIF file.
Set any other device options you want, and click OK.
The software issues warnings if it finds either of the following:
A module that is instantiated more than once at the top level.
Internal tristates. Unlike the regular design flow, in the modular
flow the software cannot move internal tristates up to the top level
because of the strict hierarchy limits required by this flow.
LO
2. Compile the design with Run->Compile Only. You need to do this to
initialize constraints for SCOPE.
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Top-level Synthesis
Optionally, you can synthesize the top-level design as an intermediate
check, although it is not necessary with the modular flow. This is because
the top-level module contains the physical locations of the devices and all
modules use the same top-level area constraint file. At this point, you
have finished the synthesis phase. The rest of the flow uses the Xilinx
place-and-route tool.
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Final Assembly
After all subordinate modules have been synthesized separately, use their
combined netlists to place and route the entire design.
1. Complete all the modules, and copy them to the PIM directory. See
Module Synthesis on page 4-75 for details. At this point, you can do
functional and timing simulation before placing and routing the top
level with the Xilinx P&R tool.
2. Open a command prompt, and go to the top_level_final directory,
and type the following:
ngdbuild -p <part_num> -modular assemble -pimpath
<path_to_pim_dir> -use_pim <module_name>
<path_to_top_level_ngo_file>
This command runs ngdbuild in assembly mode, specifying each of
the modules in the pim directory. You must repeat -use_pim
<module_name> as many times as needed to specify all the modules
in the design. For example:
ngdbuild -p xcv50-6bg256 -modular assemble -pimpath ..\PIM use_pim mux -use_pim flop example_top.ngo
The command generates a top-level .ngd file that is a fully expanded
design file.
3. Map the design with the following command. The command maps
each module using the files in the pim directory.
map <top_level_file>.ngd
For our example:
map top.ngd
4. Place and route the design with the following command. The
command uses the files in the PIM directory.
par -w <top_level_file>.ncd <top_level_file_par>.ncd
For example:
par -w example_top>.ncd
LO example_par.ncd
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5. Open the place-and-route tool and verify the locations of the modules
with this command:
fpga_editor <top_level_file_par>.ncd
To use our example, you type the following:
fpga_editor <top_level_file_par>.ncd
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VHDL
library ieee;
use ieee.std_logic_1164.all;
entity example_top is port (
inmux : in std_logic_vector(3 downto 0);
sel : in std_logic_vector(1 downto 0);
reset : in std_logic;
clk : in std_logic;
output : out std_logic);
end example_top;
architecture beh of example_top is
component mux is port (
inmux : in std_logic_vector(3 downto 0);
sel : in std_logic_vector(1 downto 0);
outmux : out std_logic);
end component;
component flop is port (
inflop : in std_logic;
clk : in std_logic;
reset : in std_logic;
outflop : out std_logic);
end component;
signal bridge : std_logic;
begin
U0 : mux port map (inmux,sel,bridge);
U1 : flop port map (bridge,clk, reset, output);
end beh;
LO
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Verilog
module modular_design_top (inmux, sel, reset, clk, out);
input [3:0] inmux;
input [1:0] sel;
input
reset;
input
clk;
output
out;
wire bridge;
mux
U0
(.inmux(inmux), .sel(sel), .outmux(bridge));
flop U1 (.inflop(bridge), .outflop(out), .reset(reset),
.clk(clk));
endmodule
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VHDL
library ieee;
use ieee.std_logic_1164.all;
entity mux is port (
inmux : in std_logic_vector(3 downto 0);
sel : in std_logic_vector(1 downto 0);
outmux : out std_logic);
end mux;
architecture beh of mux is
attribute syn_black_box : boolean;
attribute syn_black_box of beh : architecture is true;
attribute xc_modular_region : string;
attribute xc_modular_region of beh : architecture is
"CLB_R1C1:CLB_R5C5";
begin
end beh;
Verilog
module mux (inmux, sel, outmux) /* synthesis syn_black_box
xc_modular_region="CLB_R1C1:CLB_R5C5" */;
input
input
output
[3:0] inmux;
[1:0] sel;
outmux;
endmodule
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VHDL
library ieee;
use ieee.std_logic_1164.all;
entity flop is port (
inflop : in std_logic;
clk : in std_logic;
reset : in std_logic;
outflop : out std_logic);
end flop;
architecture beh of flop is
attribute syn_black_box : boolean;
attribute syn_black_box of beh : architecture is true;
attribute xc_modular_region : string;
attribute xc_modular_region of beh : architecture is
"CLB_R7C7:CLB_R8C8";
begin
end beh;
Verilog
module flop (inflop, outflop, reset, clk) /* synthesis
syn_black_box xc_modular_region="CLB_R7C7:CLB_R8C8" */;
input
input
input
output
inflop;
reset;
clk;
outflop;
endmodule
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ABCDEFGHIJKLMNOPQRSTUVWXYZ
Index
Symbols
APEX
netlist 3-109
packing I/Os 4-58
.ini file
setting preferences 3-51
setting preferences from the UI 3-50
attributes
adding 3-95
from RTL and Technology views 3-99
in constraint files 4-12
in SCOPE 3-97
Verilog 3-96
VHDL 3-95
altera_implement_in_eab 4-57
altera_implement_in_esb 4-57
for FSMs 3-87, 4-26
pipelining 4-31
syn_edif_bit_format 4-60
syn_edif_scalar_format 4-60
syn_encoding 3-88
syn_forward_io_constraints 4-12
syn_pipeline 4-31
syn_probe 4-38
syn_romstyle 4-56
syn_useioff in Altera 4-58
syn_useioff in Xilinx 4-62
VHDL package 3-95
xc_clockbuftype 4-60
xc_fast 4-59
xc_map 4-64
xc_ncf_auto_relax 4-12
xc_padtype 4-66
xc_rloc 4-64, 4-65
xc_uset 4-64, 4-65
Verilog
VHDL
A
Actel netlist 3-109
Altera
EABs 4-57
ESBs 4-57
forward-annotation 4-13
I/O packing 4-58
LPMs 4-55
netlist 3-109
RAMs 4-46
ROMs 4-56
Altera design tips 4-54
Apex 4-54
FLEX 4-55
altera_implement_in_eab attribute 4-57
altera_implement_in_esb attribute 4-57
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Synplify Pro User Guide, February 2001
Go Back
Index -1
Index
ABCDEFGHIJKLMNOPQRSTUVWXYZ
B
B.E.S.T 3-42
batch mode 4-2
Behavior Extraction Synthesis
Technology. See B.E.S.T
black box
pin attributes 4-21
black boxes 4-15
adding constraints 4-19
EDIF naming consistency 4-21
for IP cores 4-60
internal startup blocks 4-22
using Stamp models 4-22
Verilog 4-15
VHDL 4-17
bookmarks
in source files 3-7
using in log files 3-73
constraints
adding for Xilinx (tutorial) 2-27, 2-41
adding in Tcl files 4-11
black box 4-19
defaults 3-33
define_clock 4-11
define_clock_delay 4-11
define_reg_input_delay 4-11
forward-annotating 4-12
kinds of 3-30
module-level 4-77
options 3-25
RLOCs 4-64
setting 3-31
setting in tutorial 2-17, 2-30
syn_reference_clock 4-11
CoreGen 4-60
cores, instantiating in Xilinx
designs 4-60
critical paths
analyzing for Altera (tutorial) 2-25
analyzing for Xilinx designs
(tutorial) 2-39
viewing 3-67
C
classic mode 4-52
clock constraints, setting 3-32
clock DLLs 4-60
clock-to-clock constraints, setting 3-32
colors, setting 3-52
column editing 3-7
comments in source files 3-7
constraint files 4-9
See also SCOPE
creating in a text editor 4-11
creating with SCOPE 3-29
opening 3-30
vendor-specific 4-12
when to use 4-9
crossprobing 3-54
allowing to place-and-route file 3-50
and retiming 4-36
filtering text objects for 3-59
from FSM viewer 3-60
from log file 3-73
from text files 3-9
Hierarchy Browser 3-55
importance of encoding style 3-60
paths 3-58
RTL view 3-56
Technology view 3-56
Text Editor view 3-56
text file example 3-58
to FSM Viewer 3-60
Verilog file 3-56
VHDL file 3-56
within RTL and Technology views 3-55
Cypress netlist 3-109
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Index
errors
definition 3-6
source files 3-5
Verilog 3-5
VHDL 3-5
design flows
FPGA 1-4
Synplify Pro 3-2
tutorial 2-3
features 1-2
files
*.acf 4-13
*.lp 4-13
*.ncf 4-13
.data 4-22
.mod 4-22
.prf 4-14
.sdc 3-30
.v 3-3
.vhd 3-3
adding Stamp files 4-23
adding to tutorial project file 2-7
fsm.info 3-85
input. See source files
log 3-72
output 3-109
rom.info 3-47
Stamp 4-22
statemachine.info 3-93
synplify.ini 3-51
Tcl 4-4
See also Tcl commands
Tcl batch script 4-3
device options
See alsoimplementation options
setting for Altera (tutorial) 2-20
setting for Xilinx (tutorial) 2-32
directives
adding 3-95
Verilog 3-96
VHDL 3-95
black box 4-19
for FSMs 3-87
syn_state_machine 3-85
syn_tco 4-19
syn_tpd 4-19
syn_tsu 4-19
drivers
preserving duplicates with
syn_keep 3-102
selecting 3-66
E
EABs, inferring 4-57
Edit menu commands
for editing source files 3-7
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Index
ABCDEFGHIJKLMNOPQRSTUVWXYZ
Find command
in RTL and Technology views 3-43
in the Editing window (tutorial) 2-10
flattening
using syn_hier 3-100
FLEX netlist 3-109
forward annotation
frequency constraints in Xilinx 4-59
vendor-specific constraint files 4-12
FPGA configuration 1-6
FPGA design flow 1-4
H
HDL Analyst
See also RTL view, Technology view
changing the colors used 3-51
critical paths 3-67
crossprobing 3-54
filtering schematics 3-64
Push/Pop mode 3-45, 3-48
setting colors 3-51
sheet connectors 3-49
using 3-61
HDL file icon 3-3
hierarchy
flattening 3-62
traversing 3-44
FSM Explorer
running 4-27
when to use 4-26
Hierarchy Browser
controlling display 3-50
crossprobing from 3-55
defined 3-44
G
global optimization options 3-25
I
I/Os
packing in Apex designs 4-58
packing in Xilinx designs 4-62
implementation options 3-22
constraint 3-25
device 3-22
global optimization 3-25
part selection 3-22
specifying results 3-26
implementations
copying 3-105
deleting 3-105
renaming 3-105
input constraints, setting 3-32
input files. See source files
instances
preserving with syn_noprune 3-102
IP cores 4-60
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Index
logic removal
preserving with syn_preserve 3-102
warning message 3-80
keyboard shortcuts
Alt-c 3-7
Ctrl+F2 3-8
Ctrl+Shift+F2 3-8
Ctrl-d 3-33
Ctrl-f 3-7
Ctrl-F5 3-6
Ctrl-g 3-7
Ctrl-n 3-3
Ctrl-o 3-6
Ctrl-s 3-3
Ctrl-Shift-u 3-7
Ctrl-w 3-34
F12 3-64
F2 3-8, 3-45
Shift+F2 3-8
Shift+F8 3-5
shift-F7 3-5
Shift-left arrow 3-49
Shift-right arrow 3-49
Tab 3-7
M
Max netlist 3-109
mixed language files 3-17
L
latches
warning message 3-77
log files
checking (tutorial) 2-38
checking errors 3-5
checking for Altera (tutorial) 2-25
checking for Xilinx (tutorial) 2-37
checking FSM descriptions 4-28
checking information 3-72
pipelining description 4-31
retiming report 4-38
state machine descriptons 3-84
viewing 3-72
N
netlists for different vendors 3-109
nets
preserving for probing with
syn_probe 3-102
preserving with syn_keep 3-102
selecting drivers 3-66
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Index
ABCDEFGHIJKLMNOPQRSTUVWXYZ
ngdbuild command
final assembly 4-80
module level 4-78
probes
adding in source code 4-38
project files
adding files 3-14
adding files to 3-16
batch mode 4-2
creating 2-6, 3-13
definition 2-6
deleting files from 3-16
opening 3-15
replacing files in 3-17
O
optimization
for area 3-107
for timing 3-107
preserving hierarchy 3-103
preserving objects 3-102
tips for 3-106
output constraints, setting 3-32
P icon 3-13
par command
final assembly 4-80
module level 4-79
pipelining
adding attribute 4-31
definition 4-29
prerequisites 4-30
whole design 4-31
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Documents
retiming
example 4-37
overview 4-34
report 4-38
return codes 4-2
RLOCs 4-64
rom.info file 3-47
ROMs
inferencing in Altera designs 4-56
pipelining 4-30
viewing data table 3-47
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ABCDEFGHIJKLMNOPQRSTUVWXYZ
Index
sheet size
setting number of objects 3-50
setting number of objects (.ini file) 3-52
shift register lookup table. See
sequential shift components
shortcuts
checking source files 3-11
editing text 3-11
project-level operations 3-21
Show Critical Path icon 3-67
slack
handling 3-68
setting margins 3-68
source code
adding pipelining attribute 4-31
crossprobing from Tcl window 3-60
defining FSMs 4-24
fixing errors 3-8
opening automatically to
crossprobe 3-57
optimizing 3-106
specifying RLOCs 4-64
supported standards 1-3
when to use for constraints 4-9
S
schematic page size 3-50
SCOPE
adding attributes 3-97
adding probe insertion attribute 4-40
creating constraints 3-29
pipelining attribute 4-32
specifying RLOCs 4-64
state machine attributes 3-87
using in tutorial 2-17, 2-30
using the wizard 3-30, 3-34
source files
See also Verilog, VHDL.
adding files 3-14
checking 3-5
checking in the tutorial 2-9
column editing 3-7
creating 3-3
crossprobing 3-9, 3-10, 3-57
editing operations 3-7
mixed language 3-17
navigating with bookmarks 3-8
resolving errors in the tutorial 2-10
specifying default encoding style 3-27
specifying top level 3-14
specifying top-level file 3-27
state machine attributes 3-87
using bookmarks 3-7
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Index
ABCDEFGHIJKLMNOPQRSTUVWXYZ
STAMP 4-22
model files 4-22
restrictions 4-23
state machines
See also FSM Compiler, FSM Explorer,
FSM viewer, FSMs.
attributes 3-87
descriptions in log file 3-84
implementation 3-85
statemachine.info file 3-93
Synplify Pro
design flow 3-2
features 1-2
overview 1-2
starting 1-8
starting tutorial 2-4
synplify.ini file 3-51
syn_keep
preserving nets 3-102
preserving shared registerss 3-102
syn_maxfan
setting fanout limits 3-101
syn_noprune
preserving instances 3-102
syn_pipeline attribute 4-31
syn_preserve
logic removal warnings 3-80
preserving FSMs from
optimization 3-87
preserving logic 3-102
syntax
checking source files 3-5
checking Verilog 3-5
checking VHDL 3-5
synthesis
checking source files 3-5
checking Verilog 3-5
checking VHDL 3-5
rerunning for Altera (tutorial) 2-27
rerunning for Xilinx (tutorial) 2-40
running for Altera (tutorial) 2-22
running for Xilinx (tutorial) 2-35
T
Tcl commands
batch script 4-3
batch scripts return codes 4-2
entering in SCOPE 3-32
running 4-4
syn_probe
inserting probes 4-38
preserving nets 3-102
Index-8
syn_useioff attribute
Altera 4-58
Xilinx 4-62
syn_allow_retiming attribute
using for retiming 4-36
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syn_srlstyle attribute
mapping sequential shift components
to registers 4-67
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ABCDEFGHIJKLMNOPQRSTUVWXYZ
Tcl files 4-4
adding constraints 4-11
creating 4-5
for bottom-up synthesis 4-7
guidelines 4-9
naming conventions 4-10
recording from commands 4-5
using variables 4-6
wildcards 4-10
U
UNIX commands, synplify_pro 1-8
unused input, warning message 3-80
V
vendor-specific netlists 3-109
Verilog
adding attributes and directives 3-96
adding probes 4-38
black boxes 4-15
checking 3-5
clock DLLs 4-61
creating source files 3-3
crossprobing 3-56
defining FSMs 4-24
editing operations 3-7
mixed language files 3-17
RAM structures for inference 4-42
RLOCs 4-64
sequential shift components 4-70
supported standards 1-3
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Index
ABCDEFGHIJKLMNOPQRSTUVWXYZ
VHDL
adding attributes and directives 3-95
adding probes 4-38
black boxes 4-17
checking 3-5
clock DLLs 4-61
creating source files 3-3
crossprobing 3-56
defining FSMs 4-25
editing operations 3-7
mixed language files 3-17
RAM structures for inference 4-42
RLOCs 4-64
sequential shift components 4-69
supported standards 1-3
Virtex
block RAM 4-50
clock DLLs 4-60
I/O buffers 4-66
netlist 3-109
PCI core 4-60
W
warning messages
async load 3-76
handling 3-76
latch generation 3-77
logic removal 3-80
sensitivity list 3-79
unused input 3-80
X
xc_clockbuftype attribute 4-60
xc_fast attribute 4-59
xc_map attribute 4-64
xc_modular_region attribute
determining area range 4-85
xc_ncf_auto_relax attribute 4-12
xc_padtype attribute 4-66
xc_rloc attribute 4-64, 4-65
xc_uset attribute 4-64, 4-65
Xilinx
analyzing critical paths (tutorial) 2-39
block RAMs 4-49
clock DLLs 4-60
CoreGen 4-60
design guidelines 4-59
design tips 4-59
device options (tutorial) 2-32
forward-annotation 4-13
I/O buffers 4-66
IP cores 4-60
netlist 3-109
packing registers 4-62
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Synplify Pro User Guide, February 2001