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Use of High-k Dielectric materials in

Microelectronics
Sameer Badachi, PG Student, IIT-Delhi

Abstract This paper attempts to summarize the potentials of

using High-k dielectric material for MOS gate engineering.
Continual scaling down of device has led to shorter channel
lengths & thinner oxide thicknesses. While this has improved the
transistors performance and area, there are problems
accompanying with shrinking of sizes, electrically the gate gets
lesser control over the device and the manufacturing process
limits reducing the oxide layer beyond a certain thickness. In
addition to this very thin layers of SiO2 tend to have high leakage
currents wasting energy and build-up heat. Alternate materials
to SiO2 are being explored and High-k dielectrics are among the
possible solutions. We will first understand the scaling limits of
SiO2, the relevance of High-k Dielectrics and analyze the effect of
highk dielectric on a gate engineered MOSFET.

Index Terms Short channel effects, Dual material gate,

high-k gate dielectric.
I. INTRODUCTION
The transistors have up to now followed a trend of improved
performance with down scaling of size as predicted by the
Moores law, and CMOS technology has made it possible.
However there are issues that cause excessive power
consumption and heat generation in ICs. Also Modern CMOS
process is eventually reaching its limits, thus alternative
performance boosters are looked for, particularly, in direction
of introducing new materials and new device architecture thus
replacing standard silicon CMOS technology [2]. The various
approaches include, introduction of low-k interconnects,
replacement of bulk silicon by strained silicon-on-insulator
(sSOI), channel material having high mobility like
germanium, GaAs, graphene etc., non-planar CMOS device
structures like FinFET and high - k gate dielectric.
Particularly for the gate oxide, scaling has reached
fundamental material limits, If the thickness of the standard
SiO2 based gate dielectric drops below the tunneling limit,
gate leakage current will increase tremendously. For an oxide
thickness of 1.5 nm at 1.5 V the leakage current density would
be 100A/cm2 which is clearly unwanted for low power
applications [1].
To prevent this tunneling current, the dielectric layers have to
be physically thicker and as the gate dielectric become
physically thicker, consequently the transistor requires a
material with high dielectric constant to maintain its electrical
The authors are with the Department of Electrical Engineering, Indian
Institute of Technology, Delhi, 110 016 India
(e-mail: sameerbadachi@gmail.com; mamidala@ee.iitd.ac.in).

characteristics [3]. In addition, SiO2 thickness uniformity

across a 12 inch wafer imposes even more crucial difficulty in
the growth of very thin film, since slight variation in thickness
presents a large percentage difference and thus can result in
the variation of threshold voltage across the wafer [4] causing
reliability, the biggest concern for such thin layer of SiO2
film. Therefore further scaling can only be realized by using
new materials with higher k (dielectric constant) values.
Intel is one of the pioneers of the new process using high-k
materials. They have demonstrated at 45nm node process, a
combination of a high-k dielectric based on hafnium and a
new metal gate material that is compatible with hafnium,
reduced source-drain leakage substantially [5-6].
IBM too an early adopter has followed a slightly different
approach for leakage problem, has also used a high-k
dielectric gate, [6].These developments at Intel and IBM have
helped III-V devices enter the market and silicon industries.
High-k dielectric is at the core of this, and high-k compound
semiconductor MOSFETs will be able to influence the circuit
designers in the coming years [6].
In this paper, we first look at the restrictions posed by
scaling & manufacturing of thin oxide. How use of high-k
materials solves the problem posed by SiO2.What are the
material requirements of high-k dielectrics. Later the effect of
use of high-k materials for gate will be analyzed MOSFET [3],
a comparison between the performances of latter over
traditional MOS is given. Also how high-k materials become
imminent for FinFETs [7].
II. SCALING LIMITS OF SiO2
Fig. 1 shows the schematic view of standard MOS structure
and structure with high-k dielectric & metal gate.
The success of modern ICs is realized by continuous shrinking
miniaturization of transistors, which has not only increased

Fig1. MOS transistor structure [8].

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package densities, but also enhanced speed of circuit and

reduced power dissipation. These improvements were
achieved by scaling down the physical thickness of the gate
dielectric (Tox) and length of the gate (Lgate). But as the
Fig.2, suggests, the scaling of Tox and Lgate is slowing with
technology nodes [2].

2
The predicted leakage current over the years is as shown in
Fig.4 [9]. High leakage is a matter of great concern for high
performance and low power applications.

Fig. 4 The predicted range of acceptable gate leakage current over the years;
the upper limit represents high performance and the lower limit represents low
power applications

Fig 2. Scaling trend of gate length and oxide thickness (ITRS

International Technology Roadmap for Semiconductors)[2]

The static power can hence go above the active power, due to
this increase in the leakage current, as shown in fig. 5, [9]. To
minimize the active power, supply voltage needs to be reduced
as well.

Fig. 3 shows the plot for ratio of channel length to gate oxide
thickness, for Intel's process technologies over the past 20
years [9]. Each data point corresponds to a process
technology, used to fabricate Intel's Microprocessors. A
simple relationship between the oxide thickness and the
minimum channel length set by short channel effects is
visible.

Fig. 5. Active and static power increase with scaling of LGATE [9]

But scaling of VDD is also deviating from the predicted

roadmap targets as shown in plot of Fig.6, further limiting the
reduction of active power and increase in the electric field
across the gate oxide, thus the reliability of the gate oxides is
under question

Fig 3. Channel length to gate oxide thickness ratio versuschannel length for
some Intel process technologies [9]

Thermally grown silicon dioxide (SiO2) has been used till

now as material for gate dielectric as it offers an excellent
interface due to many desirable properties such as: thickness
controllability, high thermal stability, and good reliability [9].
However For new CMOS nanotechnology (LGATE< 90nm)
SiO2 has reached its physical limitations. A physical thickness
of 11-15 is so thin that electrons can directly tunnel through
the oxide, resulting in excessively high gate leakage current.

Fig. 6. Scaling of VDD with technology nodes [9]

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The solution for the aforementioned problems related to

SiO2scaling is to select an alternative material for gate
dielectric that can provide a lower equivalent oxide thickness
at higher physical thickness.

III. HIGH-K DIELECTRIC: RELEVANCE & MATERIAL REQUIREMENTS

The capacitance (C/A) is directly proportional to k value and

inversely propositional to thickness of the dielectric layer [10]
as given by the equation:

(1)
where tox and k are the thickness and relative dielectric
constant (a measure of how much charge a material can hold)
of the material respectively.
Scaling necessitated the decrease of the SiO2 thickness
drastically to gain higher capacitance densities. But
fundamental limits of SiO2 as a dielectric material, imposed
by electron tunneling, will be reached as the film thickness
approaches ~1 nm [10]. This thickness has reached already to
a point where severe problems have started to occur. To
counter these problems, we need to select a gate dielectric
with a higher permittivity than that of SiO2 (k =3.9). High-k
dielectrics are a logical solution.

Low oxygen diffusion coefficients to control the

formation of a thick low-k interface layer.
Low defect densities in high-k bulk films and at the
high-k/Si interface with negligible C-V hysteresis (<
30 mV).
Low fixed charge density (~1010cm-2eV-1).
Low high-k/Si interface state density (~1010cm2eV1).
High enough channel carrier mobility (~90% of
SiO2/Si system).
Good reliability and a long life time.

IV. STUDY OF THE EFFECT OF GATE ENGINEERING ON

DOUBLE GATE MOSFETS USING HIGH-K.
The Dual material double gate (DM DG) MOSFETs have
proven to be significant devices for nanoscale circuits as
compared to bulk CMOS technology due to their better
scalability below 45 nm. Also the presence of second gate
provides the effective gate control increases, reducing DIBL.
Fig7 shows the schematic cross-sectional view of a DM DG
MOSFETs under discussion.

If SiO2 has to be replaced by a high-k dielectric, then

dielectric thickness (Tk) increases proportionally to keep the
same dielectric capacitance. A figure of merit to judge a highk gate dielectric layer is the equivalent oxide thickness (EOT)
of a material , defined as the thickness of the SiO2 layer that
would be required to achieve the same capacitance density as
the high-k material in consideration. EOT is thus given by

(2)
Since a thicker layer is used for insulating, the tunneling
current is drastically reduced. Numerous materials with high-k
are being actively studied, in order to identify a efficient
material ranging from Al2O3 (k ~ 9) to perovskites (k ~ 102
104) , that can be used for long term. However, finding a
suitable high-k material is also major challenge because the
required material must have a higher resistivity, be thermally
stable, act as a good barrier layer, and most importantly form
an ideal interface with silicon.
There is a set of material and electrical requirements for a
viable and alternate high-k gate dielectric material [12, 13]
which include:
Larger energy band gap with higher barrier height to
Si substrate and metal gate to reduce the leakage
current.
Good thermodynamic stability on Si to prevent the
formation of a low-k SiO2 interface.
Good kinetic stability
High amorphous-to-crystalline transition temperature
to maintain a stable morphology after heat treatment.

Fig 7. Cross-sectional view of the DM-DG MOSFET

The DM DG MOSFETS have their gate engineered using two

different materials having different workfunctions, are
combined together to form a single gate of a bulk MOSFET
[5]. In this structure, the work function of the gate material
(M1) which is close to source, is chosen higher than the one
close to drain (M2),. M1 is Molybdenum with a work function
4.55 eV and M2 is Aluminum with a workfunction of 4.1
eVfor n-channel MOSFETs.
As a result, at the interface of two gates, the electric field and
electron velocity along the channel suddenly increases which
results in increased gate transport efficiency which implies
that the threshold voltage under gate material M1 is higher
than that of under gate material M2.
To study the behavior of above structure, simulations are
performed for a wide range of proposed gate dielectric k
values. The parameters that are studied are doping profile, the
electric field and the carrier velocity along the channel. For the
simulations the oxide thickness is kept at 3 nm and a silicon
film thickness of 20nm.

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The silicon film is kept practically undoped (10-15 cm-3), and
the gate work function is fixed at 4.577 eV to obtain the
threshold voltage of 0.3 V at a drain voltage of 0.1 V. [9]
Simulations are performed for gate dielectric k values of 3.9,
10 and 25 corresponding to SiO2, Al2O3 and HfO2/ZrO2
respectively. In each simulation, the physical gate oxide
thickness was proportionately scaled such that the electrical
oxide thickness (EOT) remains the same [9].
The plot of Fig 8 shows the VI characteristics of DM-DG
across different gate voltages & k values. From the plot it can
be observed that for different gate voltages, HfO2/ZrO2 is
having maximum drain current and SiO2 is having minimum
drain current.

4
This is due to the greater channel control achieved by the top
and bottom gates in the device [10]. From Fig.4, it is evident
that HfO2/ZrO2 is having maximum transconductance value
of 0.06 and SiO2 is having minimum transconductance of
0.019 when drain voltage is kept at 0.6V.HfO2/ZrO2 has the
highest transconductance when compared to other k values[9].
The electrostatic potential for different values of k , is plotted
and shown in the fig 10, it is clear that the electrostatic surface
potential is the highest for a k value of 3.9 which corresponds
to SiO2 and minimum for dielectric constant HfO2/ZrO2 [9] .

Fig 10.Plot showing the electrostatic surface potential of DM DG n-channel

for various high k dielectrics[9]
Fig 8 Plot showing the Id-Vgs characteristics of DM DG n-channel
MOSFET for different gate voltages for various high k dielectrics[9]

The gate engineered device show an increase of drain current

by about 5% in the subthreshold region. This is because the
electron velocity is increased at the source end and thus
improving carrier transport efficiency of the device.
Fig 9 shows the plot of transconductance of the device. The
transconductance is the ratio of drain current to gate voltage.

After analysis of characteristics like, transconductance and

electrostatic surface potential of Dual Material Double Gate
MOSFETs for a range of different high k dielectrics, it is clear
that there is a significant improvement in the performance for
device that uses higher-k value and since these improvements
are seen in subthreshold regime the device is suitable for low
power subthreshold analog circuits.
V. CONCLUSION

Fig 9.Plot showing the transconductance of DM DG n-channel for

various high k dielectrics[9]

From the plot a 3% increase in transconductance in strong

inversion can be seen for the gate engineered device.

In this paper, we looked at how manufacturing process limits

further scaling of SiO2.Based on these thoughts it was clear
that newer materials are to be investigated. Thus materials
having high dielectric constants was studied.
A discussion on analysis of the impact of gate engineering on
ID-VGS characteristics, transconductance and electrostatic
surface potential of Dual Material Double Gate MOSFETs
that use different high k dielectrics was done. The results
showed a significant improvement for the gate dielectrics
having higher k values.
But there are still great challenges that are open; it is observed
that the performance is degraded in FINFETs with use of
High-k gate stacks [7], so different methods have to be
identified to recover the degradation caused.
One of the other challenges is to choose an appropriate
material among many available, that provides stability and is
prone to interface problems and their fabrication techniques.

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Thus it can be established that high-k materials are very

promising for microelectronic devices with scope of further

improvements.
ACKNOWLEDGMENT
I would like to thank Prof. M. Jagadesh Kumar for his support
& guidance while writing this paper.
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