ECEN 454

Digital Integrated Circuit Design

Lecture 1 Introduction and Basics

ECEN 454 Lecture 1

Chips Inside

ECEN 454 Lecture 1

Int
od ction
Introduction
Integrated
g
circuits: manyy transistors on one chip
p
Very Large Scale Integration (VLSI): very many
Complementary Metal Oxide Semiconductor (CMOS)

Fast, cheap, low power transistors

Today: How to build your own simple CMOS chip

CMOS transistors
Building logic gates from transistors
Transistor layout and fabrication

Rest of the course: How to build a good CMOS chip

ECEN 454 Lecture 1

Invention of the Transistor

Vacuum tubes ruled in first half of 20th centuryy Large,
g ,
expensive, power-hungry, unreliable
1947: first point contact transistor

John Bardeen and Walter Brattain at Bell Labs

See Crystal Fire
by Riordan, Hoddeson

AT&T Archives.
Reprinted with
permission.
permission

ECEN 454 Lecture 1

Bi
th of Integ
ated Ci
c it
Birth
Integrated
Circuit
1958: First integrated circuit

Flip-flop using two transistors

Built by Jack Kilby at Texas
Instruments
Courtesy Texas Instruments

ECEN 454 Lecture 1

G
th R
t
Growth
Rate
53% compound
p
annual growth
g
rate over 50 years
y

No other technology has grown so fast so long

Driven by miniaturization of transistors

Smaller is cheaper, faster,

f
lower in power!
Revolutionary effects on society

[Moore65]
Electronics Magazine

ECEN 454 Lecture 1

Ann
al Sales
Annual
>1019 transistors manufactured in 2008

1 billion for every human on the planet

ECEN 454 Lecture 1

MOS Integ
ated Ci
c its
Integrated
Circuits
1970s p
processes usuallyy had onlyy nMOS transistors

Inexpensive, but consume power while idle

Intel
Museum.

[Vadasz69]

Reprinted
with
permission.

1969 IEEE.

Intel 1101 256-bit SRAM

Intel 4004 4-bit Proc

1980
1980s-present:
t CMOS processes for
f low
l
idle
idl power
ECEN 454 Lecture 1

M
Moores
Law
L

ECEN 454 Lecture 1

F
t
Si
Feature
Size
Minimum feature size shrinking
g 30% everyy 2-3 yyears

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10

Core i7
Quad core (& more)
Pentium-style architecture
2 MB L3$ / core
Characteristics
45-32 nm process
731M transistors
2.66-3.33+ GHz
Up to 130 W
32/64 bit word size
1366-pin
p LGA
Multithreading
On-die memory controller

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11

Design Flo
Flow
Architecture: Users p
perspective,
p
, what does it do?

Instruction set, registers

MIPS, x86, Alpha, PIC, ARM,

Microarchitecture

Single cycle, multi-cycle, pipelined, superscalar?

Logic: how are functional blocks constructed

Ri l carry, carry lookahead,

Ripple
l k h d carry select
l t adders
dd

Circuit: how are transistors used

Complementary CMOS, pass transistors, domino

Physical: chip layout

Datapaths, memories, random logic

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Design Cycles
C cles
System/Architectural
y
/
Design
g
HDL
Logic Design

Verification/Simulation

Physical Design/Layout
Parasitic Extraction
Fabrication
ECEN 454 Lecture 1

Testing
13

Hie a chical Design

Hierarchical
mips
controller

alucontrol

datapath

standard
cell library

bitslice

inv4x flop

alu
fulladder or2

zipper

ramslice

and2 mux4

nor2 inv nand2

mux2
tri

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Y Cha t
Y-Chart
Structural
domain

Behavioral
domain

Processor

Algorithm

Register
Gate

Finite state machine

Module description

Transistor

Boolean function
Mask
Cell placement
Module placement
Floorplan

Physical domain

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15

Design and Technology

Technolog Styles
St les
Custom design

Mostly manual design, long design cycle

High
g performance,
p
, high
g volume
Microprocessors, analog, leaf cells, IP

Standard cell

Pre-designed cells, CAD, short design cycle

Medium performance, ASIC

FPGA/PLD

Pre-fabricated, fast automated design, low cost

Prototyping, reconfigurable
f
computing
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16

Silicon Lattice
Transistors are built on a silicon substrate
Silicon is a Group IV material
Forms crystal lattice with bonds to four neighbors

Si

Si

Si

Si

Si

Si

Si

Si

Si

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17

Dopants
Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)
Si

Si

Si

Si

Si

Si

As

Si

Si

Si

Si

Si

Si

Si

ECEN 454 Lecture 1

Si
Si
Si

18

p
n JJunctions
nctions
p-n
A jjunction between p-type
p yp and n-type
yp semiconductor
forms a diode
Current flows only in one direction

p-type

n-type

anode

cathode

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nMOS Field Effect T

ansisto
Transistor
Field Effect Transistor (FET)
(
)
Four terminals: gate, source, drain, body
Gate oxide body stack looks like a capacitor

Gate is conductor, although no longer made of metal

SiO2 (oxide) is a very good insulator
Body is also called substrate or bulk
Source

Gate

Drain
Polysilicon
SiO2

n+

n+
p

ECEN 454 Lecture 1

bulk Si
20

nMOS Ope
ation - OFF
Operation
Bodyy is commonlyy tied to g
ground (0
( V))
When the gate is at a low voltage:

p-type body is at low voltage

Source-body and drain-body diodes are OFF
No current flows, transistor is OFF
Source

Gate

Drain
Polysilicon
SiO2
0

n+

n+
S
p

bulk Si

ECEN 454 Lecture 1

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nMOS Ope
ation - ON
Operation
When the g
gate is at a high
g voltage:
g

Positive charge on gate of MOS capacitor

Negative charge attracted to body
Inverts a channel under gate to n
n-type
type
Now current can flow through n-type silicon from source
through channel to drain, transistor is ON
Source

Gate

Drain
Polysilicon
SiO2
1

n+

n+
S
p

bulk Si

ECEN 454 Lecture 1

22

pMOS T
ansisto
Transistor
Similar,, but doping
p g and voltages
g reversed

Body tied to high voltage (VDD)

Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
Source

Gate

Drain

Polysilicon
SiO2

p+

p+
n

ECEN 454 Lecture 1

bulk Si

23

Po
e S
ppl Voltage
Power
Supply
GND = 0 V
In 1980s, VDD = 5V
VDD has decreased in modern processes

High VDD would damage modern tiny transistors

Lower VDD saves power

VDD = 3.3,
3 3 2.5,
2 5 1.8,
1 8 1.5,
1 5 1.2,
1 2 1.0,
10

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T
ansisto s as S
itches
Transistors
Switches
We can view MOS transistors as electricallyy controlled
switches
Voltage at gate controls path from source to drain

d
nMOS

pMOS

g=0

g=1

d
OFF

ON

OFF

ON
s

s
ECEN 454 Lecture 1

s
25

Signal St
ength
Strength
Strength
g of signal
g

How close it approximates ideal voltage source

VDD and GND rails are strongest 1 and 0

nMOS pass strong 0

But degraded or weak 1

pMOS pass strong 1

But degraded or weak 0

Thus nMOS are best for pull-down network

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26

Pass T
ansisto s
Transistors
Transistors can be used as switches
g
s

g
s

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Pass T
ansisto s
Transistors
Transistors can be used as switches
g=0

g
s

Input g = 1 Output
0
strong 0

g=1
s

1
Input

g=0

g
s

g=1

d
d

ECEN 454 Lecture 1

g=0

g=1
s

degraded 1

degraded 0
g=0

Output

strong 1

28

T
ansmission Gates
Transmission
Pass transistors p
produce degraded
g
outputs
p
Transmission gates pass both 0 and 1 well

ECEN 454 Lecture 1

29

T
ansmission Gates
Transmission
Pass transistors p
produce degraded
g
outputs
p
Transmission gates pass both 0 and 1 well
Input
g
a

b
gb

b
gb

g = 0, gb = 1
a
b

g = 1, gb = 0
0
strong 0

g = 1,
1 gb = 0
a
b

g=1
1, gb = 0
strong 1
1

g
a

g
b

gb

Output
p

b
gb

ECEN 454 Lecture 1

30