ELIMINATING SYNCHRONIZATION LATENCY USING

SEQUENCED LATCHING

ABSTRACT:
Modern multicore systems have a large number of components operating in different
clock domains and communicating through asynchronous interfaces. These interfaces use
synchronizer circuits, which guard against metastability failures but introduce latency in
processing the asynchronous input. We propose a speculative method that hides synchronization
latency by overlapping it with computation cycles. We verify the correctness of our approach
through a field programmable gate array implementation and apply it to a number of synthesized
benchmarks. Synthesis results reveal that our approach achieves average savings of Area, costs
and power costs compared to two similar speculative techniques. The Proposed design will be
implemented using Verilog HDL.

EXISTING SYSTEM:
Speculation is the use of either time or resource redundancy to perform potentially useful
work. Modern digital systems employ speculation at different abstraction levels. For example,
memory management speculatively populates cache hierarchies with perfected data to reduce the
impact of slow memory access on processing speed. Also, processors that use branch prediction
speculatively execute the instructions following branches to increase throughput.

EXISTING SYSTEM ALGORITHM:

Speculation

EXISTING SYSTEM DRAWBACKS:

Slow Processing Speed.

PROPOSED SYSTEM:
In this proposed system, we describe a novel technique to latch data reliably during
synchronization cycles. In short, we use the synchronizer as a state machine to sequence a series
of latching operations. The synchronizer is constrained such that its state does not change when a
latching operation fails. Therefore, any failed latching attempts are automatically retried in the
Subsequent cycles. This method is called sequenced latching.

PROPOSED ALGORITHM:

Sequenced Latching.

BLOCK DIAGRAM:

Asynchronous controller which uses sequenced latching

ADVANTAGES:

Less delay, High speed.

SOFTWARE REQUIREMENT:

ModelSim6.4c.

Xilinx 9.1/13.2.

HARDWARE REQUIREMENT:

FPGA Spartan 3.

APPLICATION:

Digital System

Digital radio receivers

FUTURE ENHANCEMENT:
We will analyze the Proposed System Delay with Normal Designs.

ALTERNATE TITLES:
Title 1: Implementation of Sequenced latching on FPGA
Title 2: Sequenced latching by removing synchronization latency
Title 3: Realization of Sequenced latching using Verilog HDL without synchronization
latency

PROJECT FLOW:
First Phase:
60% of Base Paper (3 Modules only Simulation)

Second Phase:

Remaining 40% of Base Paper with Future Enhancement (Modification)