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CHAP. 3]

83

CHARACTERISTICS OF BIPOLAR JUNCTION TRANSISTORS

Solved Problems
3.1

For a certain BJT,  50; ICEO 3 A, and IC 1:2 mA.

Find IB and IE .

By (3.2),
IC  ICEO 1:2  103  3  106

23:94 A

50

IB
And, directly from (3.4),

IE IC IB 1:2  103  23:94  106 1:224 mA

3.2

A Ge transistor with  100 has a base-to-collector leakage current ICBO of 5 A. If the
transistor is connected for common-emitter operation, nd the collector current for
(a) IB 0 and (b) IB 40 A.
(a) With IB 0, only emitter-to-collector leakage ows, and, by (3.3),
ICEO  1ICBO 100 15  106 505 A
(b) If we substitute (3.3) into (3.2) and solve for IC , we get
IC IB  1ICBO 10040  106 1015  106 4:505 mA

3.3

A transistor with  0:98 and ICBO 5 A is biased so that IBQ 100 A. Find ICQ and IEQ .
By (3.2) and (3.3),

0:98

49
1   1  0:98
 1ICBO 49 15  106 0:25 mA


so that

ICEO

And, from (3.2) and (3.4),

ICQ IBQ ICEO 49100  106 0:25  103 5:15 mA
IEQ ICQ IBQ 5:15  103 100  106 5:25 mA

3.4

The transistor of Fig. 3-11 has  0:98 and a base current of 30 A.
and (c) IEQ . Assume negligible leakage current.
iC

RC
C
RB

+
_ VCC

LCE
_

iB

_ VBB

E
iE

Fig. 3-11

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Find

(a) ;

b ICQ ,

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84

CHARACTERISTICS OF BIPOLAR JUNCTION TRANSISTORS

[CHAP. 3


0:98

49
1   1  0:98

(b) From (3.2) with ICEO 0, we have ICQ IBQ 4930  106 1:47 mA:
(c)

From (3.1) with ICBO 0,

IEQ

3.5

ICQ 1:47

1:50 mA

0:98

The transistor circuit of Fig. 3-11 is to be operated with a base current of 40 A and VBB 6 V.
The Si transistor VBEQ 0:7 V) has negligible leakage current. Find the required value of RB .
By KVL around the base-emitter loop,
VBB IBQ RB VBEQ

3.6

so that

RB

VBB  VBEQ
6  0:7

132:5 k

IBQ
40  106

In the circuit of Fig. 3-11,  100; IBQ 20 A, VCC 15 V, and RC 3 k
. If ICBO 0, nd
(a) IEQ and (b) VCEQ . (c) Find VCEQ if RC is changed to 6 k
and all else remains the same.



100

0:9901
 1 101

Now, using (3.2) and (3.1) with ICBO ICEO 0, we get

ICQ IBQ 10020  106 2 mA
IEQ

and

ICQ 2  103

2:02 mA

0:9901

(b) From an application of KVL around the collector circuit,

VCEQ VCC  ICQ RC 15  23 9 V
(c)

If IBQ is unchanged, then ICQ is unchanged.

The solution proceeds as in part b:

VCEQ VCC  ICQ RC 15  26 3 V

3.7

The transistor of Fig. 3-12 is a Si device with a base current of 40 A and ICBO 0. If VBB 6 V,
RE 1 k
, and  80, nd (a) IEQ and (b) RB . (c) If VCC 15 V and RC 3 k
, nd
VCEQ .

RC

C
iC
RB

B
+

iB

iE

_ VCC

_ VBB
RE

Fig. 3-12

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CHAP. 3]

CHARACTERISTICS OF BIPOLAR JUNCTION TRANSISTORS

85


80

0:9876
 1 81

Then combining (3.1) and (3.2) with ICBO ICEO 0 gives

IEQ

IBQ
40  106

3:226 mA
1   1  0:9876

(b) Applying KVL around the base-emitter loop gives

VBB IBQ RB VBEQ IEQ RE
or (with VBEQ equal to the usual 0.7 V for a Si device)
RB
(c)

VBB  VBEQ  IEQ RE 6  0:7  3:2261

51:85 k

IBQ
40  106

From (3.2) with ICEO 0,

ICQ IBQ 8040  106 3:2 mA
Then, by KVL around the collector circuit,
VCEQ VCC  IEQ RE  ICQ RC 15  3:2261  3:23 2:174 V

3.8

Assume that the CE collector characteristics of Fig. 3-9(b) apply to the transistor of Fig. 3-11. If
IBQ 20 A, VCEQ 9 V, and VCC 14 V, nd graphically (a) ICQ ; b RC ; c IEQ , and
(d)  if leakage current is negligible.
(a) The Q point is the intersection of iB IBQ 20 A and vCE VCEQ 9 V. The dc load line must pass
through the Q point and intersect the vCE axis at VCC 14 V. Thus, the dc load line can be drawn on
Fig. 3-9(b), and ICQ 2:25 mA can be read as the iC coordinate of the Q point.
(b) The iC intercept of the dc load line is VCC =Rdc VCC =RC , which, from Fig. 3-9(b), has the value
6.5 mA; thus,
RC
(c)

VCC
14

2:15 k

6:5  103 6:5  103

By (3.4), IEQ ICQ IBQ 2:25  103 20  106 2:27 mA.

(d) With ICEO 0, (3.2) yields



3.9

ICQ 2:25  103

112:5
IBQ
20  106

In the pnp Si transistor circuit of Fig. 3-13, RB 500 k
, RC 2 k
, RE 0, VCC 15 V,
ICBO 20 A, and  70. Find the Q-point collector current ICQ .
By (3.3), ICEO  1ICBO 70 120  106 1:42 mA. Now, application of the KVL around
the loop that includes VCC , RB , RE 0, and ground
VCC VBEQ IBQ RB

so that

IBQ

VCC  VBEQ
15  0:7

28:6 A
RB
500  103

Thus, by (3.2),
ICQ IBQ ICEO 7028:6  106 1:42  103 3:42 mA

3.10

The Si transistor of Fig. 3-14 is biased for constant base current. If  80, VCEQ 8 V,
RC 3 k
, and VCC 15 V, nd (a) ICQ and (b) the required value of RB . (c) Find RB if
the transistor is a Ge device.

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86

CHARACTERISTICS OF BIPOLAR JUNCTION TRANSISTORS

[CHAP. 3

_V

CC

RC
+
RB

RB
_

RC
iC

C
iC

+
_ VCC

iB
B
iE

RE
E

Fig. 3-13

Fig. 3-14

(a) By KVL around the collector-emitter circuit,

ICQ

VCC  VCEQ
15  8

2:333 mA
Rc
3  103

(b) If leakage current is neglected, (3.2) gives

IBQ

ICQ 2:333  103

29:16 A

80

Since the transistor is a Si device, VBEQ 0:7 V and, by KVL around the outer loop,
RB
(c)

VCC  VBEQ
15  0:7

490:4 k

IBQ
29:16  106

The only dierence here is that VBEQ 0:3 V; thus

RB

3.11

15  0:3
504:1 k

29:16  106

The Si transistor of Fig. 3-15 has  0:99 and ICEO 0. Also, VEE 4 V and VCC 12 V.
(a) If IEQ 1:1 mA, nd RE . (b) If VCEQ 7 V, nd RC .
iE

iC

RC

RE
B

+
VEE _

iB

VCC

Fig. 3-15
(a) By KVL around the emitter-base loop,

RE

VEE VBEQ 4 0:7

3

IEQ
1:1  103

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CHAP. 3]

87

CHARACTERISTICS OF BIPOLAR JUNCTION TRANSISTORS

(b) By KVL around the transistor terminals (which constitute a closed path),
VCBQ VCEQ  VBEQ 7  0:7 6:3 V
With negligible leakage current, (3.1) gives
ICQ IEQ 0:991:1  103 1:089 mA
Finally, by KVL around the base-collector loop,
RC

3.12

VCC VCBQ
12  6:3

5:234 k

ICQ
1:089  103

Collector characteristics for the Ge transistor of Fig. 3-15 are given in Fig. 3-16. If VEE 2 V,
VCC 12 V, and RC 2 k
, size RE so that VCEQ 6:4 V.
iC, mA
8

iE = 7 mA

6 mA

5 mA

4 mA

, iC for hf b

,LCB for hob

3 mA

, iC for hob

, iE for hfb

2 mA

1 mA

0
2

_2

_4

_6

_8

_ 10

_ 12

_ 14

_ 16

_ 18

_ 20

LCB , V

Fig. 3-16
We construct, on Fig. 3-16, a dc load line having vCB intercept VCC 12 V and iC intercept
VCC =RC 6 mA. The abscissa of the Q point is given by KVL around the transistor terminals:
VCBQ VCEQ  VBEQ 6:4  0:3 6:1 V
With the Q point dened, we read IEQ 3 mA from the graph.
leads to
RE

3.13

Now KVL around the emitter-base loop

VEE VBEQ 2 0:3

566:7

IEQ
3  103

The circuit of Fig. 3-17 uses current- (or shunt-) feedback bias. The Si transistor has ICEO  0,
VCEsat  0, and hFE 100. If RC 2 k
and VCC 12 V, size RF for ideal maximum symmetrical swing (that is, location of the quiescent point such that VCEQ VCC =2.

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88

CHARACTERISTICS OF BIPOLAR JUNCTION TRANSISTORS

+VCC
RC

RF

CC

iC
1

iS

RS

+
LS

[CHAP. 3

iL

LL

RL

iB
CC

_
0

Ri

Ro

Fig. 3-17

Application of KVL to the collector-emitter bias circuit gives

IBQ ICQ RC VCC  VCEQ
With ICQ hFE IBQ , this leads to
IBQ

VCC  VCEQ
12  6
29:7 A

hFE 1RC 100 12  103

Then, by KVL around the transistor terminals,

RF

3.14

VCEQ  VBEQ
6  0:7

178:5 k

IBQ
29:7  106

For the amplier of Fig. 3-17, CC 100 F, RF 180 k
, RL 2 k
, RS 100 k
,
VCC 12 V, and vS 4 sin20  103 t V.
The transistor is described by the default npn
model of Example 3.2.
Use SPICE methods to (a) determine the quiescent values
(IBQ ; ICQ ; VBEQ ; VCEQ ) and (b) plot the input and output currents and voltages vS ; iS ; vL ; iL .
(a) The netlist code that follows models the circuit:
Prb3_14.CIR - CE amplifier
vS 1 0 SIN(0V 4V 10kHz)
RS 1 2 100kohm
CC1 2 3 100uF
Q 4 3 0 QNPN
RF 3 4 180kohm
RC 4 5 2kohm
VCC 5 0 12V
CC2 4 6 100uF
RL 6 0 2kohm
.MODEL QNPN NPN() ; Default transistor
.DC VCC 12V 12V 1V
.PRINT DC IB(Q) IC(Q) V(3) V(4)
.TRAN 1us 0.1ms ; Signal values
.PROBE
.END

Execute hPrb3_14.CIRi and poll the output le to nd IBQ IBQ 29:3 A, ICQ
ICQ 2:93 mA, VBEQ V3 0:80 V, and VCEQ V4 6:08 V. Since VCEQ VCC =2, the transistor is biased for maximum symmetrical swing.

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CHAP. 3]

CHARACTERISTICS OF BIPOLAR JUNCTION TRANSISTORS

89

(b) The Probe feature of PSpice is used to plot iS , iL , nS , and nL as displayed by Fig. 3-18. Notice the 1808
phase shift between input and output quantities.

Fig. 3-18

3.15

Find the value of the emitter resistor RE that, when added to the Si transistor circuit of Fig. 3-17,
would bias for operation about VCEQ 5 V. Let ICEO 0;  80; RF 220 k
; RC 2 k
,
and VCC 12 V.
Application of KVL around the transistor terminals yields
IBQ

VCEQ  VBEQ
5  0:7

19:545 A
RF
220  103

Since leakage current is zero, (3.1) and (3.2) give IEQ  1ICQ ; thus KVL around the collector circuit
gives
IBQ IBQ RC  1IBQ RE VCC  VCEQ

so

3.16

RE

VCC  VCEQ   1IBQ RC 12  5  80 119:545  106 2  103

2:42 k

 1IBQ
80 119:545  106

In the circuit of Fig. 3-12, IBQ 30 A; RE 1 k
; VCC 15 V, and  80. Find the minimum
value of RC that will maintain the transistor quiescent point at saturation, if VCEsat 0:2 V,  is
constant, and leakage current is negligible.
We rst nd



80

0:9876
 1 81

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90

CHARACTERISTICS OF BIPOLAR JUNCTION TRANSISTORS

[CHAP. 3

Then the use of (3.2) and (3.1) with negligible leakage current yields
ICQ IBQ 8030  106 2:4 mA
IEQ

and

ICQ 2:4  103

2:43 mA

0:9876

Now KVL around the collector circuit leads to the minimum value of RC to ensure saturation:
RC

3.17

VCC  VCEsat  IEQ RE 15  0:2  2:431

5:154 k

ICQ
2:4  103

The Si transistor of Fig. 3-19 has  50 and negligible leakage current. Let VCC 18 V,
VEE 4 V; RE 200
, and RC 4 k
. (a) Find RB so that ICQ 2 mA. (b) Determine the
value of VCEQ for VB of part (a).
+ VCC
RC

IS

RB
RE

_V

EE

Fig. 3-19
(a) KVL around the base-emitter-ground loop gives
VEE IBQ RB VBEQ IEQ RE

Also, from (3.1) and (3.2),

IEQ

1
ICQ


Now, using (3.2) and (2) in (1) and solving for RB yields
RB

VEE  VBEQ
504  0:7
  1RE
 50 1200 72:3 k

ICQ
2  103

(b) KVL around the collector-emitter-ground loop gives



1
RE ICQ
VCEQ VCC VEE  RC



50
1
18 4  4  103
200 2  103 13:59 V
50

3.18

The dc current source IS 10 A of Fig. 3-19 is connected from G to node B. The Si transistor
has negligible leakage current and  50. If RB 75 k
, RE 200
, and RC 4 k
, nd the
dc current-gain ratio ICQ =IS for (a) VCC 18 V and VEE 4 V, and (b) VCC 22 V and
VEE 0 V.

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CHAP. 3]

CHARACTERISTICS OF BIPOLAR JUNCTION TRANSISTORS

91

(a) A Thevenin equivalent for the network to the left of terminals B; G has VTh RB IS and RTh RB .
With the Thevenin equivalent circuit in place, KVL around the base-emitter loop yields
RB IS VEE IBQ RB VBEQ IEQ RE

Using (3.2) and (2) of Problem 3.17 in (1), solving for ICQ , and then dividing by IS results in the desired
ratio:
ICQ RB IS VEE  VBEQ
75  103 10  106 4  0:7
! 237:67


R


1
IS
75  103 50 1
6
IS B
RE
10  10

200


50
50

Note that the value of VCC must be large enough so that cuto does not occur, but otherwise it does not
aect the value of ICQ .
(b) VEE 0 in (2) directly gives
ICQ

IS

75  103 10  106  0:7

10 

106

75  103 50 1

200
50
50

! 2:93

Obviously, VEE strongly controls the dc current gain of this amplier.

3.19

In the circuit of Fig. 3-20, VCC 12 V, VS 2 V; RC 4 k
, and RS 100 k
. The Ge transistor is characterized by  50; ICEO 0, and VCEsat 0:2 V. Find the value of RB that just
results in saturation if (a) the capacitor is present, and (b) the capacitor is replaced with a short
circuit.
(a) Application of KVL around the collector loop gives the collector current at the onset of saturation as
ICQ

VCC  VCEsat 12  0:2

2:95 mA
RC
4  103

With C blocking, IS 0; hence the use of KVL leads to

RB

VCC  VBEQ VCC  VBEQ

12  0:3
198:3 k

IBQ
ICQ =
2:95  103 =50

+VCC
IRB
RB

IS
+
VS

RC

RS

Lo

Fig. 3-20

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92

CHARACTERISTICS OF BIPOLAR JUNCTION TRANSISTORS

[CHAP. 3

(b) With C shorted, the application of (3.2), KCL, and KVL results in
ICQ
VS  VBEQ VCC  VBEQ

IS IRB

RS
RB
VCC  VBEQ
12  0:3
RB

278:6 k

ICQ VS  VBEQ 2:95  103
2  0:3



RS
50
100  103

IBQ
so that

3.20

The Si Darlington transistor pair of Fig. 3-21 has negligible leakage current, and 1 2 50.
Let VCC 12 V; RE 1 k
, and R2 ! 1. (a) Find the value of R1 needed to bias the circuit so
that VCEQ2 6 V. (b) with R1 as found in part a, nd VCEQ1 .
+ VCC
R1
IR1
a

T1

iB2

R2

T2
RE

IR2
b

Fig. 3-21
(a) Since R2 ! 1; IR2 0 and IBQ1 IR1 .

By KVL,

VCC  VCEQ2
12  6

6 mA
RE
1  103
IEQ2

IEQ1
2 1
IEQ1
IEQ2
6  103
IBQ1

2:31 A
1 1 1 12 1 50 150 1

IEQ2
Now

IBQ2

and

IR1

By KVL (around a path that includes R1 , both transistors, and RE ) and Ohms law,
R1

VR1 VCC  VBEQ1  VBEQ2  IEQ2 RE 12  0:7  0:7  6  103 1  103

1:99 M

IR1
IR1
2:31  106

(b) Applying KVL around a path including both transistors and RE , we have
VCEQ1 VCC  VBEQ2  IEQ2 RE 12  0:7  6  103 1  103 5:3 V

3.21

The Si Darlington transistor pair of Fig. 3-21 has negligible leakage current, and 1 2 60.
Let R1 R2 1 M
; RE 500
, and VCC 12 V. Find (a) IEQ2 , b VCEQ2 , and (c) ICQ1 .
(a) A Thevenin equivalent for the circuit to the left of terminals a; b has
R2
1  106
V
12 6 V
R1 R2 CC 1  106 1  106
R1 R2
1  106 1  106

500 k

R1 R2 1  106 1  106

VTh
and

RTh

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CHAP. 3]

CHARACTERISTICS OF BIPOLAR JUNCTION TRANSISTORS

93

With the Thevenin circuit in place, KVL gives

VTh IBQ1 RTh VBEQ1 VBEQ2 IEQ2 RE

Realizing that
IEQ2 2 1IBQ2 2 11 1IBQ1
we can substitute for IBQ1 in (1) and solve for IEQ2 , obtaining

IEQ2

1 12 1VTh  VBEQ1  VBEQ2

60 160 16  0:7  0:7
7:25 mA

RTh 1 12 1RE

500  103 60 160 1500

(b) By KVL,
VCEQ2 VCC  IEQ2 RE 12  7:25  103 500 8:375 V
(c)

From (3.1) and (3.2),

ICQ1

3.22

IEQ2
1
1
1
60 7:25  103

I
I

116:9 A
1 1 EQ1 1 1 BQ2 1 1 2 1 60 1 60 1

The Si transistors in the dierential amplier circuit of Fig. 3-22 have negligible leakage current,
and 1 2 60. Also, RC 6:8 k
, RB 10 k
, and VCC VEE 15 V. Find the value of
RE needed to bias the amplier such that VCEQ1 VCEQ2 8 V.
+ VCC

RC

RC

Lo

6
+

7
T1

T2

3
iE
L1

Lo1

RB

Lo2

RE
2

L2

_V

EE

RB

Fig. 3-22
By symmetry, IEQ1 IEQ2 .

Then, by KCL,
iE IEQ1 IEQ2 2IEQ1

Using (1) and (2) of Problem 3.17 (which apply to the T1 circuit here), along with KVL around the left
collector loop, gives
VCC VEE

1
I R VCEQ1 2IEQ1 RE
1 1 EQ1 C

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94

CHARACTERISTICS OF BIPOLAR JUNCTION TRANSISTORS

[CHAP. 3

Applying KVL around the left base loop gives

VEE IBQ1 RB VBEQ1 iE RE

IEQ1
R VBEQ1 2IEQ1 RE
1 1 B

Solving (3) for 2IEQ1 RE , substituting the result into (2), and solving for IEQ1 yield
I EQ1

1 1VCC  VCEQ1 VBEQ1

60 115  8 0:7

1:18 mA
1 RC  RB
606:8  103  10  103

and, by (3),
RE

3.23

VEE  VBEQ1 

RB
I
1 1 EQ1

2IEQ1

10  103
1:18  103
60 1
5:97 k

21:18  103

15  0:7 

The Si transistor of Fig. 3-23 has negligible leakage current, and  100.
VEE 4 V; RE 3:3 k
, and RC 7:1 k
, nd (a) IBQ and (b) VCEQ .
_V

RE

RC

EE

1
+

+ VCC

iS

iL
2

CC

LS

If VCC 15 V,

3 C
C

6
+
RL

LL

_
0

Fig. 3-23
(a) By KVL around the base-emitter loop,
IEQ

VEE  VBEQ
4  0:7

1 mA
RE
3:3  103

Then, by (3.1) and (3.2),

IBQ

IEQ
1  103

9:9 A
1
100 1

(b) KVL and (2) of Problem 3.17 yield




VCEQ VCC VEE  IEQ RE  ICQ RC VCC VEE  RE
RC IEQ
1


100
3
3
3
15 4  3:3  10
7:1  10 1  10 8:67 V
100 1

3.24

For the transistor circuit of Fig. 3-23, CC 100 F, RE 3:3 k
; RC 8:1 k
; RL 15 k
,
VCC 15 V; VEE 4 V, and vS 0:01 sin2000t V. The transistor can be described by the
generic npn model. Use SPICE methods to (a) determine the quiescent voltage VCEQ and
(b) plot the input and output currents and voltages.
(a) The netlist code below describes the circuit.

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CHAP. 3]

CHARACTERISTICS OF BIPOLAR JUNCTION TRANSISTORS

95

Prb3_24.CIR - CB amplifier
vs 1 0 SIN(0V 10mV 1kHz)
CC1 1 2 100uF
RE 2 4 3.3kohm
VEE 0 4 4V
Q 3 0 2 QNPNG
RC 3 5 8.1k
VCC 5 0 15V
CC2 3 6 100uF
RL 6 0 15kohm
.MODEL QNPNG NPN(Is=10fA Ikf=150mA Isc=10fA Bf=150
+ Br=3 Rb=1ohm Rc=1ohm Va=30V Cjc=10pF Cje=15pF)
.DC VCC 15V 15V 1V
.PRINT DC V(3,2)
.TRAN 1us 1ms
.PROBE
.END

After executing hPrb3_24.CIRi, examine the output le to nd VCEQ V3; 2 7:47 V.

VCEQ VCC =2, the transistor is biased for maximum symmetrical swing.

Since

(b) Use the Probe feature of PSpice to plot the input and output currents and voltages as displayed by Fig.
3-24. Notice that this circuit amplies the output voltage while the output current is actually less in
amplitude than the input current.

Fig. 3-24

3.25

Find the proper collector current bias for maximum symmetrical (or undistorted) swing along the
ac load line of a transistor amplier for which VCEsat ICEO 0.
For maximum symmetrical swing, the Q point must be set at the midpoint of the ac load line. Hence,
from (3.13), we want


1
1 VCEQ
ICQ
1
ICQ iC max
2
2 Rac

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96

CHARACTERISTICS OF BIPOLAR JUNCTION TRANSISTORS

[CHAP. 3

But for a circuit such as that in Fig. 3-9(a), KVL gives

VCEQ  VCC  ICQ Rdc

which becomes an equality if no emitter resistor is present. Substituting (2) into (1), assuming equality, and
solving for ICQ yield the desired result:
ICQ

3.26

VCC
Rac Rdc

In the circuit of Fig. 3-8(a), RE 300
; RC 500
; VCC 15 V;  100, and the Si transistor
has -independent bias. Size R1 and R2 for maximum symmetrical swing if VCEsat  0.
For maximum symmetrical swing, the quiescent collector current is
ICQ

1 VCC
15

9:375 mA
2 RE RC 2300 500

Standard practice is to use a factor of 10 as the margin of inequality for  independence in (3.8).
RB

Then,

RE 100300
3 k

10
10

and, from (3.7),

VBB  VBEQ ICQ 1:1RE 0:7 9:375  103 330 3:794 V
Equations (3.5) may now be solved simultaneously to obtain
RB
3  103
4:02 k

1  VBB =VCC 1  3:794=15

V
15
R2 RB CC 3  103
11:86 k

VBB
3:794

R1
and

3.27

In the circuit of Fig. 3-10(a), the transistor is a Si device, RE 200
; R2 10R1 10 k
,
Assume that CC and CE are very large, that
RL RC 2 k
;  100, and VCC 15 V.
VCEsat  0, and that iC 0 at cuto. Find (a) ICQ , b VCEQ , c the slope of the ac load
line, (d) the slope of the dc load line, and (e) the peak value of undistorted iL .
(a) Equations (3.5) and (3.7), give
1  103 10  103
1  103
909

and
VBB
15 1:364 V
3
11  103
11  10
VBB  VBEQ
1:364  0:7


3:177 mA
RB = 1 RE 909=101 200

RB
so

ICQ

(b) KVL around the collector-emitter circuit, with ICQ  IEQ , gives
VCEQ VCC  ICQ RE RC 15  3:177  103 2:2  103 8:01 V
c

d
(e)

Slope

Slope

1
1
1
1

2
1 mS
Rac RC RL
2  103

1
1
1

0:454 mS
Rdc RC RE 2:2  103

From (3.14), the ac load line intersects the vCE axis at

vCE max VCEQ ICQ Rac 8:01 3:177  103 1  103 11:187 V

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CHAP. 3]

CHARACTERISTICS OF BIPOLAR JUNCTION TRANSISTORS

97

Since vCE max < 2VCEQ , cuto occurs before saturation and thus sets Vcem . With the large capacitors
appearing as ac shorts,
v
v
iL L ce
RL RL
or, in terms of peak values,
ILm

3.28

Vcem vCE max  VCEQ 11:187  8:01

1:588 mA
RL
RL
2  103

In the circuit of Fig. 3-8(a), RC 300
; RE 200
; R1 2 k
; R2 15 k
; VCC 15 V, and
 110 for the Si transistor. Assume that ICQ  IEQ and VCEsat  0. Find the maximum
symmetrical swing in collector current (a) if an ac base current is injected, and (b) if VCC is
changed to 10 V but all else remains the same.
(a) From (3.5) and (3.7),
2  103 15  103
2  103
1:765 k

and
VBB
15 1:765 V
3
17  103
17  10
VBB  VBEQ
1:765  0:7
 IEQ

4:93 mA
RB = 1 RE 1765=111 200

RB
so

ICQ

By KVL around the collector-emitter circuit with ICQ  IEQ ,

VCEQ VCC  ICQ RC RE 15  4:93  103 200 300 12:535 V
Since VCEQ > VCC =2 7:5 V, cuto occurs before saturation, and iC can swing 4:93 mA about ICQ
and remain in the active region.
b

VBB
so that
and

ICQ  IEQ

R1
2  103
VCC
10 1:1765 V
R1 R2
17  103

VBB  VBEQ
1:1765  0:7

2:206 mA
RB = 1 RE 1765=111 200

VCEQ VCC  ICQ RC RE 10  2:206  103 0:5 8:79 V

Since VCEQ > VCC =2 5 V, cuto again occurs before saturation, and iC can swing 2:206 mA about
ICQ and remain in the active region of operation. Here, the 33.3 percent reduction in power supply
voltage has resulted in a reduction of over 50 percent in symmetrical collector-current swing.

3.29

If a Si transistor were removed from the circuit of Fig. 3-8(a) and a Ge transistor of identical 
were substituted, would the Q point move in the direction of saturation or of cuto?
Since R1 ; R2 , and VCC are unchanged, RB and VBB would remain unchanged. However, owing to the
dierent emitter-to-base forward drops for Si (0.7 V) and Ge (0.3 V) transistors,
ICQ 

VBB  VBEQ
RB = 1 RE

would be higher for the Ge transistor. Thus, the Q point would move in the direction of saturation.

3.30

In the circuit of Fig. 3-10(a), VCC 12 V; RC RL 1 k
; RE 100
, and CC CE ! 1.

The Si transistor has negligible leakage current, and  100. If VCEsat 0 and the transistor
is to have -independent bias (by having R1 kR2 RE =10, size R1 and R2 for maximum symmetrical swing.
Evaluating Rac and Rdc , we nd
Rac RL kRC

1  103 1  103
500

1  103 1  103

Rdc RC RE 1  103 100 1100

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98

CHARACTERISTICS OF BIPOLAR JUNCTION TRANSISTORS

[CHAP. 3

Thus, according to (3) of Problem 3.25, maximum symmetrical swing requires that
VCC
12

7:5 mA
Rac Rdc 500 1100
RE 100100

1 k

RB R1 kR2
10
10

ICQ
Now,

and, by (3.6) and (2) of Problem 3.17,

!


RB  1
1  103 100 1
VBB

RE ICQ VBEQ
100 7:5  103 0:7 1:53 V

100

100
Finally, from (3.5),
R1

3.31

RB
1  103

1:34 k

1  VBB =VCC 1  1:53=12

and

R2

RB VCC 1  103 12

10:53 k

VBB
1:53

The Si transistor of Fig. 3-10(a) has VCEsat ICBO 0 and  75. CE is removed from the
circuit, and CC ! 1. Also, R1 1 k
; R2 9 k
; RE RL RC 1 k
, and VCC 15 V.
(a) Sketch the dc and ac load lines for this amplier on a set of iC -vCE axes. (b) Find the
maximum undistorted value of iL , and determine whether cuto or saturation limits iL swing.
Rdc RC RE 1  103 1  103 2 k

Rac RE RC kRL 1  103

and

1  103 1  103
1:5 k

1  103 1  103

By (3.5),
VBB

R1
1  103
VCC
15 1:667 V
R2
9  103

and

RB R1 kR2

1  103 9  103
900

1  103 9  103

and from (3.7),

 1VBB  VBEQ
75 11:667  0:7
0:96 mA

RB  1RE
900 75 11  103

ICQ

By KVL around the collector loop and (2) of Problem 3.17,





1
75 1
VCEQ VCC  RC
RE ICQ 15  1  103
1  103 0:96  103 13:07 V

75
The ac load-line intercepts now follow directly from (3.13) and (3.14):
iC max

VCEQ
13:07
ICQ
0:96  103 9:67 mA
Rac
1:5  103

vCE max VCEQ ICQ Rac 13:07 0:96  103 1:5  103 14:51 V
The dc load-line intercepts follow from (3.9):
VCC
15

7:5 mA
Rdc
2  103
vCE -axis intercept VCC 15 V
iC -axis intercept

The required load lines are sketched in Fig. 3.25.

(b) Since ICQ < 12 iC max , it is apparent that cuto limits the undistorted swing of ic to ICQ 1:92 mA.
By current division,
iL

RE
1  103
i
0:96 mA 0:48 mA
RE RL c 1  103 1  103

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CHAP. 3]

CHARACTERISTICS OF BIPOLAR JUNCTION TRANSISTORS

99

iC, mA

iC max = 9.67
VCC
= 7.5
Rdc

DC load line
AC load line

ICQ = 0.96

VCC = 15
LCE, V
LCE max = 14.51

Fig. 3-25

3.32

In the common-collector (CC) or emitter-follower (EF) amplier of Fig. 3-26(a), VCC

12 V; RE 1 k
; RL 3 k
, and CC ! 1. The Si transistor is biased so that VCEQ 5:7 V
and has the collector characteristic of Fig. 3-26(b). (a) Construct the dc load line. (b) Find the
value of . (c) Determine the value of RB .
(a) The dc load line must intercept the vCE axis at VCC 12 V.

It intercepts the iC axis at

VCC VCC
12

12 mA
Rdc
RE
1  103
The intercepts are connected to form the dc load line shown on Fig. 3-26(b).
(b) IBQ is determined by entering Fig. 3-26(b) at VCEQ 5:7 V and interpolating between iB curves to nd
IBQ  50 A. ICQ is then read as  6:3 mA. Thus,

(c)

By KVL,

RB

3.33

ICQ 6:3  103

126
IBQ
50  106

VCC  VBEQ 

1
ICQ RE


IBQ

12  0:7 

126 1
6  103 1  103
126
105:05 k

50  106

The amplier of Fig. 3-27 uses an Si transistor for which VBEQ 0:7 V.
Assuming that
the collector-emitter bias does not limit voltage excursion, classify the amplier according to
Table 3-4 if (a) VB 1:0 V and vS 0:25 cos !t V; b VB 1:0 V and vS 0:5 cos !t V,
(c) VB 0:5 V and vS 0:6 cos !t V, (d) VB 0:7 V and vS 0:5 cos !t V.
As long as vS VB > 0:7 V, the emitter-base junction is forward-biased; thus classication becomes a
matter of determining the portion of the period of vS over which the above inequality holds.
(a) vS VB
0:75 V through the complete cycle; thus the transistor is always in the active region, and the
amplier is of class A.
(b) 0:5 vS VB 1:5 V; thus the transistor is cut o for a portion of the negative excursion vS . Since
cuto occurs during less than 1808, the amplier is of class AB.
(c) 0:1 vS VB 1:1 V, which gives conduction for less than 1808 of the period of vS , for class C
operation.
(d) vS VB
0:7 V over exactly 1808 of the period of vS , for class B operation.

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+ VCC

RB

CC

CC
iS

LB
_

+
LE
_

RE

iL
+
LL
_

RL

Zin

Zo
(a)

iC, mA
DC load line (Problem 3.32)
AC load line (Problem 3.54)

100 mA

14

80 mA

12

10

60 mA

Q
40 mA

20 mA
2

iB = 10 mA
iB = 0

0
0

10

12

14

16

18

4.7 5.7 6.7

LCE, V

(b)

Fig. 3-26

RL

RB

2
+

LS

VCC

_
+
VB

Fig. 3-27

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LCE, V