GEETHANJALI COLLEGE OF ENGINEERING AND TECHNOLOGY

CHEERYAL, KEESARA.
MTECH 1ST YEAR 1ST SEM I MID EXAMINATIONS
DEPARTMENT OF ECE
(Common to VLSI ,ES,ECE)
FACULTY : P. Sneha Naga Shilpa
Subject: VLSI Technology & Design

DURATION : 2HRS

SET-1
PART- A
Answer all the questions. Each question carry 4 marks.
1.
2.
3.
4.

Compare CMOS and Bi-polar Transistors.

Draw the schematic & layout for an CMOS NAND gate.
Derive the expressions for Input transconductance Gm.
What is Fan- out?

PART- B
Answer any THREE questions. Each question carry 8 marks.
1. Determine the Pull-up to pull-down ratio for an NMOS inverters driven through one or more
pass transistors.
2. Explain in detail about BiCMOS Inverters?
3. Write in detail about Pseudo- nmos logic.
4. Explain the Delay through resistive Interconnect.
5. Explain about Standard Cell Layout Design.

GEETHANJALI COLLEGE OF ENGINEERING AND TECHNOLOGY

CHEERYAL, KEESARA.
MTECH 1ST YEAR 1ST SEM I MID EXAMINATIONS
DEPARTMENT OF ECE
(Common to VLSI ,ES,ECE)
FACULTY : P. Sneha Naga Shilpa
Subject: VLSI Technology & Design

DURATION : 2HRS

SET-2
PART- A
Answer all the questions. Each question carry 4 marks.
1.
2.
3.
4.

What is Body effect? How we can overcome it?

Draw the schematic & layout for an CMOS NOR gate.
Write short notes on Enhancement mode Nmos transistor.
Write short notes on Path delay.
PART- B

Answer any THREE questions. Each question carry 8 marks.

1. Determine the Pull-up to pull-down ratio for an NMOS inverter driven by another NMOS
inverter.
2. Explain in detail about the fabrication process of NMOS transistor.
3. Write in detail about Domino logic.
4. Draw a Layout for a CMOS Inverter and explain its transfer characteristics.
5. Explain in detail about Transistor sizing.

GEETHANJALI COLLEGE OF ENGINEERING AND TECHNOLOGY

CHEERYAL, KEESARA.
MTECH 1ST YEAR 1ST SEM I MID EXAMINATIONS
DEPARTMENT OF ECE
(Common to VLSI ,ES,ECE)
FACULTY : P. Sneha Naga Shilpa
Subject: VLSI Technology & Design

DURATION : 2HRS

SET-3
PART- A
Answer all the questions. Each question carry 4 marks.
1.
2.
3.
4.

Write short notes on Enhancement mode nmos transistor.

Draw a transistor schematic for following expressions *a(b+c)+.
Write a short notes on Switch logic.
Write short notes about Fan-in.

PART- B
Answer any THREE questions. Each question carry 8 marks.
1.
2.
3.
4.
5.

What is latch-up condition in CMOS circuits? How it can be eliminated?

Explain in detail about the fabrication process of CMOS transistor.
Write in detail about Pseudo- nmos logic & DCVS logic.
Explain in detail about the delay through RC transmission line.
Explain about device modeling.

GEETHANJALI COLLEGE OF ENGINEERING AND TECHNOLOGY

CHEERYAL, KEESARA.
MTECH 1ST YEAR 1ST SEM I MID EXAMINATIONS
DEPARTMENT OF ECE
(Common to VLSI ,ES,ECE)
FACULTY : P. Sneha Naga Shilpa
Subject: VLSI Technology & Design

DURATION : 2HRS

SET-4
PART- A
Answer all the questions. Each question carry 4 marks.
1.
2.
3.
4.

Differentiate between CMOS inverter and BiCMOS inverter.

Write a short notes on DCVS logic. What are the limitations of scaling?
Differentiate Pseudo-nmos , Domino & DCVS logic.
Write short notes on critical path.
PART- B

Answer any THREE questions. Each question carry 8 marks.

1.
2.
3.
4.
5.

Derive the relationship between Ids & Vds for an nmos transistor.
Explain in detail about the fabrication process of p-well.
Explain in detail about the delay through RLC transmission line.
Explain the Scalable design rules.
Explain how to minimize the crosstalk in VLSI.