ASSIGNMENT - 2

Shubham Sahay
2014EEN2401
October 2, 2014

Question 1

Design a circuit in Schematic to calculate CMOS inverter delay which takes account of all the conditions
such as loading on inverter, Input slew, Input output coupling, sizing etc.

1.1

2 stage load Circuit

1.1.1

3 stage load circuit

1.2
1.2.1

Calculation
Sizing

in order to take the effect of both loading at input and the output i used the 3 load inverter circuit in
which the input and outputs were calculated for the 2nd inverter giving 1st inverter an input pulse.As the
delay had to be compared with the earlier inverter made in spectre,i used the same sizing here and the
delay results obtained are summarised here.
LOAD
spectre Inverter
2 load
0.120
inverter used to load
1.2.2

Wp(um)
4
3 load inverter

Lp(nm)
0.120
4

Wn(um)
2
0.120

Ln(nm)
0.120
2

12

12

Inverter Delay
Tplh = delay ( v(IN) 0.6 1 falling v(OUT) 0.6 1 rising)
Tphl = delay ( v(IN) 0.6 1 rising v(OUT) 0.6 1 falling)

1.2.3

SlewRate

SlewRate = slewRate( v(OUT) 10n t 30n t 10 90) using X coordinates

LOAD
spectre Inverter
2 load Inverter
3 load Inverter

1.3

tplh(ns)
0.1853
0.7468
1.5

tphl(ns)
0.0304
0.53
0.83

spectre Inverter Transient Response

DELAY(ns)
0.102
0.6384
1.165

SLEWRATE(V/us)
732.1252
456.23
428.45

1.4

2 load Inverter Transient Response

1.5

2 load Inverter Transient Response

thus we conclude that the delay increases due to loading and the slew rate also decreases as the load
capacitance and gate capacitances have increased.

QUESTION 2

Design a ring oscillator using 5 inverters. Calculate its time period and compare its result with theoretical
calculations using inverter delays from spectre net list.

2.1

2.1.1

Circuit

Refrence Inverter Schematic

2.1.2

2.2
2.2.1

Calculation
Sizing of the reference inverter
LOAD
Ref Inverter

2.2.2

Reference Inverter Symbol

Wp(um)
4

Lp(nm)
120

Wn(um)
2

Ln(nm)
120

Reference Inverter Delay

Tplh = delay ( v(IN) 0.6 1 falling v(OUT) 0.6 1 rising)
Tphl = delay ( v(IN) 0.6 1 rising v(OUT) 0.6 1 falling)

Ref Inverter
2.2.3

tplh(ns)
0.1853

tphl(ns)
0.0304

DELAY(ns)
0.10

Time Period and Frequency when initial condition is 1mV

Theoretical
Practical

Inverter Delay(ns)
0.295
0.295

Time Period(ns)
0.139
0.1405568

Frequency(GHz)
0.217
7.114561

2.2.4

Ring Oscillator Transient Response

thus we conclude that the frequency of the wave is 7.14 Ghz when the reference inverter is used.

3
3.1
3.1.1

QUESTION 3

Design NAND and NOR gates in schematic using static CMOS. Convert
these into symbols
NAND sized wrt reference inverter

Schematic:

Symbol:

3.1.2

NOR sized wrt reference inverter

Schematic:

Symbol:

3.2

Circuit Diagram and Sizing using logical effort method

3.2.1

Circuit Diagram:

3.2.2

Delay Calculation:

Formula for Delay using the logical effort method:

tp = tpo

X
N

pi +

i=1

G = g1 .g2 .g3 .g4 .g5

B = b1 .b2 .b3 .b4 .b5
CL
F =
Cinp
H = GF B

N
h= H

10

3.2.3

Sizing:

Formula for Sizing :

g1 .s1
si =
gi

 i1
Y

fj
b
j=1 j

Here although the inverter stage doesnot make any sense.But for worst case we consider the delay because of
that also.Also the input loading factor g1 f oraisdueto2gatesnowwhichisef f ectively3.T hesizesweref oundtobescaledass1 =
1, s2 = 0.6225, s3 = 0.51875, s4 = 0.7806ands5 = 1.4635.thesesizesarewithrespecttof irststagei.e.thenorgate.
Sizing :
NOR1
INVERTER
NAND1
NOR2
NAND2

Wp(um)
8
2.49
2.075
6.2448
5.8544

Lp(nm)
120
120
120
120
120

Wn(um)
2
1.245
2.075
1.5612
5.8544

Ln(nm)
120
120
120
120
120

Delay :
NOR1
INVERTER
NAND1
NOR2
NAND2

Tphl(ns)
0.409
0.024
0.41
0.037
0.73

Tplh(ns)
2.42
0.06
0.034
0.031
0.029

Delay(ns)
1.41
0.042
0.222
0.034
0.3795

Total Worst Case Delay (ns) : 2.0875 ns

3.2.4

Output Waveforms:

NOR1 Output Waveform:

11

INVERTER Output Waveform and sized :

NAND1 Output Waveform and sized :

12

13

NOR2 Output Waveform and sized :

NAND2 Output Waveform and sized :

14

15

Total Output Waveform :

16

BONUS QUESTION

Using Ring Oscillator (5 stage) generate a periodic wave of frequency 10 MHz

4.1

METHOD

By changing the inverter delays i.e by changing the length and widths we can change the intrinsic delay
and as such the period of wavveform.Note: changing lengths would increase the delays even more.

4.2

Sizing

By changing lengths keeping the width fixed as the reference inverter i arrived at the following length and
widths to achieve a frequency of nearly 10 MHz.

NMOS
PMOS

4.3

Wp(um)
2
4

Waveform

17

Lp(um)
4.83
4.88