SEMINAR REPORT 2009 ESD PROTECTION DEVICES

INTRODUCTION
High tech companies lose at least 4-6 percent of annual gross sales due
to
electrostatic discharge (ESD) every year, according to Stephen Halperin,
president of the Electrostatic Discharge Association. “I know of companies
who are aware of ESD losses totaling 10 percent or more of their gross
sales and that is only the losses above which they had budgeted for,”
notes Halperin .

The quest to provide reliable electronic products (computers, network

hardware, cell phones, PDA’s, etc.), requires a look at the “brains” of
those devices. At the core of modern electronics is integrated circuitry
(IC) that provides processing and communication functions. Because they
are so crucial to the product, they need to be protected against electrical
transients that can be generated by their users.

Specifically, Electrostatic Discharge (ESD) transients can be

introduced to the devices (and ultimately to the IC’s) during normal usage
by the end user. But how does this occur? Picture an electronic device as
a black box. Inside are various circuits (IC’s, ASIC’s, magnetics, etc.) that
provide functionality; outside are various components (switches, buttons,
keypads, data ports, etc.) to control the device.

Connecting the outside and inside environments are physical

interconnects (cables, connectors/ports) that allow the flow of information
(data). These input and output channels are necessary for the data flow,
but they can also allow the introduction of ESD into the “box”. Once in the
“box”, ESD seeks to dissipate its energy, a portion of which will gain
exposure to the integrated circuitry .

This report discusses general ESD protection principles, basic devices

used as ESD protection structures, and the underlying device physics.
Understanding of these ESD protection device fundamentals are essential
to successful design of ESD protection circuits . This is particularly true as
IC technologies become more complex and IC chips get more
sophisticated .

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1 ELECTROSTATIC DISCHARGE(ESD)
1.1 What is ESD
Electrostatic Discharge(ESD) is a sudden transfer of charge from a body
or a
Surface to another body at a different potential. Static charge build up is
caused by either friction between two surfaces (called triboelectrification)
or by proximity to an electrostatic field (called induction charging). Bodies
or surfaces may develop triboelectric charges due to
contact,pressure,friction and seperation. Depending upon friction and the
speed with which bodies are coming in contact and seperating the
voltages developed may easily go upto 25kV. Another way of developing
static charges is by induction. If an isolated or ungrounded object comes
inside an electrostatic field it may develop charges. These high voltages
when discharge through a grounded surface cause a large current to flow
through the bodies for a small duration of time. This high current may
cause Electrical Overstress and breakdown of the object.

Figure 1.1: Static Charge Generation and Accumulation

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If proper protection devices are not put in place,electrostatic

discharge can lead to very high voltages and currents which can destroy
the internal circuits of the chip and cause its failure.ESD is the most
common cause of IC chip failure and hence ESD protection is a very
important aspect of chip design.

1.2 Effect of Environment on ESD

Depending on a material’s electronegativity and conductivity it may

acquire and build up very high potential when it comes in contact with
other materials. Various objects commonly available in any ordinary room
may interact to produce potentials of several thousands of volts. If proper
measures are not taken these static voltages can damage the IC. Thus
during IC production and handling various precautions are taken, these
include use of proper kind of materials, maintaining temperature and
humidity of the manufacturing environment and grounding of objects and
people handling the ICs.

Materials which have insulating property are completely removed from

the work place since they acquire the maximum amount of static charge.
Conductors are also not preferred because they have very low surface
resistance and any ESD current through them would be large. The
preferred material for IC handling are Dissipative in nature, since they
allow the static charges to bleed off at an optimal speed and have
sufficiently high surface resistance. The special packing used for IC
transportation and storage are made of such materials.

Maintaining a high relative humidity inside the room greatly reduces

the ESD voltages produced due to static charges, thus reducing the
danger of ESD. The effect of relative humidity on the ESD voltages
generated by some common event during IC handling are listed below.

Events Relative Humidity

10% 40% 50%

Walking across the vinyl floor 12000 5000 3000

Motion of bench employee 6000 800 400

Removing ICs from plastic tube 2000 700 400

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Packing PWBs in form line box 21000 11000 5500

Table 1.1: Static Voltages produced at different Relative Humidity (in

volts)

Another measure that is taken is grounding of the working platform

and wearing wrist bands connected to the floor or the footwear. By
bringing every object at the same common ground potential ESD events
can be avoided.

1.3 ESD Endangered Systems

Everything from fabricated silicon wafers to the end customer systems
like computer and mobiles come under the threat of ESD. An ESD event at
a pin of an IC chip is very different from the ESD event at a
communication port of a system, therefore the two are grouped and
studied separately as the Device Level and the System Level ESD.

1.3.1 ESD on Device Level

There are several modes in which an IC package can come under the
effect of an ESD event. These modes have been classified and modeled to
help in the study of various ESD dangers to an IC and to establish an
industry standard for the ESD protection devices. The ESD standards
released by ESDA and JEDEC are commonly used to check the ESD
robustness of IC chips by semiconductor industry.

• Human Body Model(HBM): The Human Body Model ESD

event occurs when a charged person(human body’s capacitance is
modeled at 100pF) touches a packaged device through the body
resistance of 1.5KΩ. A HBM ESD event of charge level 2kV can
cause a peak discharge current of 1.3A with a typical decay time
of 150ns. According to the industry standards, ESD robustness
requires the protection device to be able to block a minimum HBM
ESD event of 2kV.
• Machine Model(MM): A discharging event from a machine is
modeled as Machine Model, with a capacitance of 200pF and a
low series resistance. A MM ESD event pf charge level 200V can
cause a peak discharging current of 3-4A with a rise time of 10ns.
Both HBM and MM usually result in similar thermal damage
phenomena. A protection device is expected to block a MM ESD
event of a minimum of 200V.

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Charged Device Model(CDM): ESD phenomena can also occur if

an arbitrarily charged IC is suddenly discharged to a metallic ground
plane. Such an event as modeled as Charged Device Model ESD event.
A CDM ESD event of charge value 1kV can produce much higher
discharging currents of upto 15A with a rise time of only 200ps. All
commercial ICs are expected to at least sustain an CDM ESD event of
1kV level.

1.3.2 ESD on System Level

An ESD event at a communication port of a system can go upto very high

levels of 10-20kV if not checked properly. Though the probability that the
discharge current would pass through an IC chip inside the system is
small the damage due to a system level ESD can be more extensive and
dramatic, when compared to the damage due to a device level HBM ESD
event.

Figure 1.2: Damage due to ESD at System Level

One of the most common mode of ESD at system Level is the Cable
Discharge Events(CDE). Cable Discharge Event occurs when a statically
charged cable is plugged into a communication port of the system.
Ethernet wires, which are generally very long, and USB cables can acquire
a lot of charge and are the most common cause of a cable discharge
event.

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2 ESD PROTECTION CONCEPTS

2.1 Basic ESD Clamp
Before looking into the protection circuits we need to take a look at how
an electrical overstress can occur in an IC chip. Electrical overstress can
occur in the form of a positive or negative voltage pulse with respect to
Vcc or Vss. This makes four combinations which are: positive-to-Vss (PS
mode) negative-to-Vss (NS mode) positive-to-VDD (PD mode) and
negative-to-VDD (ND mode)[5]. To protect the IC from such high voltage
pulses, ESD clamps are placed between every I/O pin and ground. These
clamps turn on only when an ESD pulse is detected and remain off for
normal operations. These
clamps are essentially like a diode and turn on when a voltage above
their threshold voltage is applied at the pin.

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Figure 2.1: Simplified view of the ESD clamp on I/O Pins

Just placing ESD clamps on the I/O pins and diverting the high ESD
pulse to the ground pins is not enough to ensure the safety of the device.
There may be an ESD event in which the Vcc pin may be stressed with
respect to the ground pin. So we need to put a suitable ESD clamp
between
the power pins. The power clamp needs to have the property of being
able to carry large amount of current without being destroyed itself. The
ESD clamp at the I/O pins and the power clamp together form the basis of
the ESD Protection Circuit at IC level.

2.2 ggNMOS as the Clamping Device

A MOSFET(metal oxide semiconductor-field effect transistor) is a four
terminal device consisting of a source, drain, gate and substrate. A NMOS
has highly doped n-type drain and source regions and a p-type substrate
region. When a positive voltage is applied between the source and drain
with zero gate voltage, no current can flow since the n+ region of the
source and the p region of the substrate are reversed biased

When a voltage greater that the Threshold Voltage(VT ) is applied

at the gate terminal, the holes in the substrate region are pushed back
and theelectrons from the source region come in to form a n type
depletion region.The depth of the depletion region depends upon the

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magnitude of the gatevoltage applied. This depletion region allows a

current to flow through whena positive voltage(< VGS − VT ) is applied
between source and drain. Thismode of operation is called the Linear
Region. The drain current in the linear region is governed by the equation
2.1

ID = µnCox W

The applied voltage VDS appears as a gradient between the source

and the drain region, that is, the voltage at the source end is zero and the
voltage at the drain side is VDS. Therefore, if VDS is greater than VGS −
VT then the depth of the depletion region at the drain will be almost zero.
This is called Pinch-Off. In this situation the drain current saturates and no
longer depends on VDS. The drain current in the pinch off mode is given
by the equation 2.2

Figure 2.2: Gate Grounded NMOS (ggNMOS)

A NMOS transistor, with the gate and the source terminal grounded
and the drain connected to the I/O pin of the IC, is most commonly used
as the clamping circuit. Since the gate pin is grounded, the transistor will
never turn on during normal operation,(voltage at the I/O pin is positive).
But if a negative voltage(< −VT ) is applied on the I/O pin the upper
terminal will act as the source. This will make VG = 0 and VS < −VT so
the device will turn on(VGS > 0). In this way a ggNMOS effectively acts
like a diode connected between the source and the drain terminal as
shown in the figure 2.2. Thus this circuit can effectively divert a negative
ESD pulse(NS mode and ND mode) to the ground.

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But as mentioned above, an ESD stress can occur in positive-

toVSS(PS) and positive-to-VDD(PD) modes as well. For protection against
positive voltage pulse an almost similar circuit but with a PMOS is put on
the I/O in. The gate of the PMOS device is connected to VDD so that it can
not turn on during normal operation. When a high positive voltage is
applied at the I/O pin the PMOS diverts it to the VDD pin. Therefore a
power clamp is required to provide a path for the discharging current
during a PD and PS mode ESD event. Since several I/O pins may be under
ESD stress at any time, the power clamp needs to be carrying much
larger current as compared to the ESD clamps on individual pins. So the
NMOS used for the power clamp must have a much larger depletion
region width(W). Instead, more robust devices like SCR or field-oxide
device can also be used. A complete overview of the protection circuit is
given below in figure 2.3

Figure 2.3: Overview of the Basic Protection Circuit

The above circuit has a transient detecting circuit. It follows the VCC
to ground voltage with a small time constant. For slow variation in VCC,
VX will be approximately same as VCC. So the PMOS device will be off and
the NMOS device will be on, it will ensure that the gate voltage of the
power clamp device is kept at zero. When VCC rises very fast, then VX will
become

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significantly less that than VCC. The threshold voltage VT of the PMOS
transistors in the transient detecting circuit must be designed in such a
way
that it switches on the power clamp transistor at this instant.

2.3 High Voltage Characteristics of NMOS

The high voltage characteristics of NMOS transistor is fundamental to ESD
protection design. As mentioned before, when VDS becomes more than
VGS− VT the transistor goes into pinch off mode. Thus the ggNMOS will
always be in pinch off mode during any ESD event(VGS = 0). Let us see
what happens during pinch off.

Figure 2.4: Avalanche Breakdown and turn on of the Parasitic Bipolar

As we can see in the figure 2.4 the density of the equipotential

surfaces
becomes very high near the drain. This creates a strong electric field near
the drain substrate junction. This high electric field causes the first
avalanche breakdown of the NMOS transistor. Due to the breakdown
electrons and holes are created. These holes flow towards the
substrate(Isub) due to the positive gate potential thereby forward biasing
the source-substrate junction. This turns on the parasitic Bipolar
Transistor. The threshold voltage and current at which the avalanche
breakdown occurs are called Vt1 and It1 respectively. After the first
breakdown the voltage decreases sharply since the bipolar transistor gets
switched on and starts to conduct. As the current increases further after
the snapback, thermal heating of the device becomes prominent and a
second thermal breakdown occurs at the voltage and current threshold
values of Vt2 and It2 respectively.

The high current IV characteristics of ggNMOS is summarized in the

figure 2.5. In normal nomenclature It2 represents the failure current
normalized to the device finger width. The robustness to ESD is measured

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by It2 which can be typically at 5 mA/μm as measured by 100 ns wide

square wave pulses. This It2 then roughly translates to 10 V/μm for the
HBM. Therefore, a 200μm wide transistor should provide 2 kV HBM level
but this is not possible to achieve due to departure from ideal behavior .

Figure 2.5: High Current IV characteristics of ggNMOS

2.4 NonLinear Parasitic Capacitance

All electrostatic discharge protection devices have a nonlinear
capacitance
associated with the reverse baised p-n junction. Such a parasitic junction
capacitance is nonlinear and depends on the input voltage level. This
nonlinear capacitance along with any finite source impedance form a low
pass filter that significantly distorts the input signal. This distortion
becomes a limiting factor for analog input signals even at relatively lower
frequencies. Thus, the associated capacitance is an important design
parameter for high speed analog input and output pins .

The total input capacitance of the protection circuit in figure 2.3 can
be
varied by choosing the layout spacings in the NMOS and PMOS clamping
transistors properly [6]. It is quite useful for real circuit design that the
variation on the input capacitance of a proposed ESD protection circuit
design can be minimized by simply choosing the suitable device
dimensions and layout spacings in the NMOS and PMOS devices for a
given CMOS process .

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2.5 Effect of Technology Scaling

As the feature sizes, defined by the nominal polysilicon gate length,
Lpoly, of
technologies enter the sub micron region, the prospect of designing good
ESD protection circuits becomes more challenging. Some of the major
concerns for protection circuits in the sub micron region include the thin
gate oxide (40-80 °A), small channel lengths (0.25-0.5 μm), shallow
junctions, salicided diffusions and lightly doped drain (LDD) regions .

As the size of the NMOS transistor decreases the electric field

intensity at the drain junction increases, this leads to the problem of hot-
carriers and
early avalanche breakdown of the substrate-drain junction. To counter
this,
lightly doped drain (LDD) with n− doped extension regions were used at
the source/drain. Use of lightly doped drain reduces the junction depth
and
hence degrades the second breakdown current It2, which in turn
decreases
the efficiency of the protection circuit. Salicide clad diffusions are used in
MOSFETs to reduce the source/drain sheet resistance and thereby
increase
circuit speed. The introduction of salicide diffusions reduced the ESD
performance by a factor between 3x and 5x. Salicidation reduces the
effective junction depth at the source, which reduces the emitter
efficiency of the parasitic bipolar transistor. Salicidation also causes the
current in the drain to be restricted to the region close to the salicide and
increases the effective current density in the drain. These two effects
combine to increase the junction heating and decrease It2. The degrading
effects of LDD and salicide can be overcome by implementing deeper
implants at the source/drain [7].

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Figure 2.6: Effect of Scaling on various Breakdown Voltages[8]

Part (a) of figure 2.6 shows the variation of Oxide Breakdown Voltage
BVox, as a function of oxide thickness tox, for NMOS transistor in a 0.25
μm technology. It also shows the avalanche breakdown voltage, Vt1, for
the same values of oxide thickness. It is clear from the graph that the
margin between BVox and Vt1 decreases with oxide thickness. It is
obvious that, for being able to use a NMOS clamp to protect an input gate
oxide, there must be a sufficient margin between oxide breakdown
voltage and avalanche breakdown voltage. Below 50°A, some drain
engineering will be required to improve this margin .

Part (b) of figure 2.6 shows the variation of avalanche breakdown

voltage(Vt1), snapback voltage(Vsp) and the second breakdown
voltage(Vt2) with the technology feature size for a NMOS. As expected,
the threshold breakdown voltages decrease with the feature size .

Not all changes brought about by technology scaling are bad for ESD
protection circuits. The use of TiW barrier metals in the contacts has
greatly improved contact integrity and the higher eutectic temperature
prevents the
occurrence of contact melting before the required ESD levels are reached.
Due to smaller channel lengths the efficiency of the parasitic bipolar
transistors in the NMOS increases with decrease in feature size. This
causes the second breakdown current It2 to actually increase with
decrease in feature size [8] .

Hence, as the feature size reduces, effective ESD protection circuits

can
be made provided the degrading effects of shallower junctions are offset
by
the positive effect of the reduction in effective channel length .

3 ADVANCEMENTS IN ESD PROTECTION CIRCUIT

3.1 Use of SCR for ESD Protection
Hot carrier triggered SCR’s have been developed for ESD protection.
These
hot carrier triggered SCR’s (HCTSCR) replace the bulky NMOS as the ESD
protection device in the power rail clamps. The use of SCR structure
provides more effective ESD protection than the NMOS FET because SCR

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has a lower on resistance and a more uniform distribution of electric field.

The SCR also works effectively with salicided diffusions.

Figure 3.1: Schematic of hot-carrier triggered SCR ESD protection

circuit[9].

In the figure 3.1 the part inside box is the schematic representation of
the SCR device used for protection against positive polarity stress on VCC
with respect to VSS. The SCR is triggered into the low impedance state by
the hot carrier generated substrate current from the NMOS transistor M1.
Transistor M2 in connected as a capacitor to follow the VCC voltage.
Transistor M4 acts as an ESD clamp and limits the voltage across the gate
oxide of M2. During normal working M3 keeps the gate voltage of M1
(Vgate) at Vss, so that the SCR can not be turned on. By optimizing M2
and M3 it is ensured that Vgate > Vt1 when an ESD pulse is detected by
the trigger circuit. Where Vt1 is the avalanche breakdown voltage of M1 .

The trigger voltage of the SCR can be tuned by varying the gate
length of the trigger FET M1. The minimum VCC trigger voltages are 6.5V
for 0.5 μm gate length and 9.3V for 5.0 μm gate length. The SCR clamps
Vcc to about 1.4V at low current once it is triggered and achieves an HBM

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ESD failure threshold in excess of 8800V, corresponding to >100V/μm of

device width[9].

3.2 Use of Substrate Triggering Field Oxide Device

As the feature size is decreased, the pad to pad spacing available on chip
also reduces and the total area available for the ESD protection circuit
including latchup guardings becomes very small. Hence it is essential that
the protection device has a high V/μm2 ESD protection limit. Substrate
triggering field oxide devices(STFOD) have been proposed which can
obtain the whole chip ESD protection within a very small space[10].

The schematic of the protection circuit using STFOD is similar to that

in figure 2.3 but with a STFOD as the power rail clamp instead of a NMOS.
The substrate of the STFOD is connected to the output of the ESD
transient detecting circuit and its gate is connected to VDD. When turned-
on the STFOD provides a very low impedance to the VDD to Vss path and
hence can clamp the ESD voltage across the VDD and Vss power lines to
a very small value. The turn-on time of the STFOD is designed as long as
200 ns to meet the half energy discharging time of the HBM ESD event

Figure 3.2: The device structure of the substrate triggering field oxide
device.

The structure of STFOD is shown in figure 3.2. The substrate bias

voltage is applied at VB which causes the holes in the p+ region to flow
towards the substrate, providing the substrate triggering current Itrig. As
in the case of the parasitic bipolar of the NMOS this substrate current
forward biases the base-emitter junction of the lateral bipolar transistor. A
N-wel surrounding the whole STFOD is added in the source region to
enhance its lateral bipolar action. The second breakdown current It2 of a

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NMOS and a STFOD for various values of substrate bias voltage is shown
in figure 3.3. As can be observed from the figure, a drastic improvement
in the value of It2 (per unit channel width) can be achieved by properly
selecting the substrate trigger value. Therefore a STFOD can provide a
much more robust ESD protection in a much smaller area .

Figure 3.3: The dependence of It2 (per unit channel width) on the forward
biased substrate voltage in a STFOD and a NMOS .

3.3 ESD Protection Scheme for ICs with Power Down

Mode
Low Power mode operation has become an important feature in portable
and
mobile system on chip products that require effective power saving.
Consider the circuit in figure 2.3, lets see what may happen if this
protection circuit is used for an IC with power down mode. Suppose the
power pins of the IC are floating in the low power mode and the voltage
level at the input pad is high. The internal circuits may then be triggered
to cause malfunction by charging the power lines through the parasitic
diode of PMOS connected between the input pad and VDD power line.
Also there may be a large leakage current through the parasitic diode if
the power lines are at zero potential and the voltage level at the output
pin is high. Thus the parasitic diode of the PMOS connected between the
input pad and VDD must be removed to avoid leakage current or
malfunctions in power down mode operations .

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Figure 3.4: ESD Protection Scheme for ICs with Power-Down Mode Operation[5]

A ESD protection scheme for ICs with power down mode is proposed
in
[5]. The figure 3.4 shows the schematic of the ESD protection scheme for
ICs
with power-down mode operations. This ESD protection scheme proposes
an
additional ESD bus line (VDD ESD), which is not directly connected to the
external power supply, and is separated into input and output stage by
diode D3. Diodes D1 and D2 are connected between the VDD and VDD
ESD line to block any leakage current from the input/output pads in the
power down mode(VDD = 0). The Diode D3 block any leakage current
between the input and output pads. For saving the layout area, the VDD
ESD bus line can be realized by a different parallel metal layer, which
overlaps the VDD power line .

3.4 Improving ESD Robustness for MugFETs

Fabrication of normal transistors at 32nm node and beyond becomes very
difficult, on the other hand multi gate planar transistors with silicon on
insulator (SOI) technology have many benefits, which include high speed
performance due to reduced capacitance, good body control and
suppression of short channel effect. These features make multi gate FETs

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with SOI the best candidate for continued technology scaling. But these
devices are extremely sensitive towards ESD. Due to non-uniformity of
current through all the gates, only some of the gates are effected and get
destroyed, this severely brings down the safe current limits and the
threshold breakdown values. Any fin that shows a slightly earlier
breakdown, takes over the current and gets destroyed. The heating and
partial damage makes the neighbor fin susceptible for damage too. This
can be seen in figure 3.5 where a group of fins have melt away together.
Therefore, improving the ESD robustness of individual fins leads to more
homogeneous conduction and therefore a better overall ESD robustness.
In the case of multi finger NMOS, gate coupling (which is done by tying
the gate to ground through a large resistance) is used to bring Vt1 below
Vt2 and facilitate more number of parallel npn’s to turn on .

Figure 3.5: Local ESD failure in a multi finger NMOS FinFET device

In case of MugFETs the isolation of the body region from the substrate
impacts the electro-thermal behavior seriously. To optimize the ESD
robustness of a MugFET device we need to ensure a uniform current
conduction in all the fins and to make each fin able to sustain a certain
level of ESD current without being destroyed. To increase the ESD
robustness of individual fins the thermal coupling to the source and drain
regions must be improved. Selective Epitaxial Growth (SEG) is used for
this purpose[11]. After etching the fins and formation of the gate stack,
sillcon is epitaxially grown on the part of the fins not covered by the gate.
This provides additional thermal mass attached directly to the region of
the hot spot and improves the heat conduction to the source and drain
regions. This leads to a strong improvement in the ESD performance of
the device. At the same time the on resistance of the device is reduced
which improves the voltage clamping across the device during an ESD
event and helps to protect against breakdown of gate dielectrics. To
facilitate uniform current flow even at lower robustness of the single fin a
ballasting resistance can be built-in at the drain side .

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4 FUTURE ROADMAP
4.1 Nano Thechnology for ESD Protection
As the technology is driving towards smaller chip geometries, higher
frequency and mixed signal and RF integration on the same chip, the
threat of damage from ESD is increasing for all electronic devices. We
saw that the new devices coming with technology scaling are becoming
more and more sensitive towards ESD. And at the same time both the
space and the capacitance budgets circuit designer allow for a product’s
ESD protection are decreasing .

With 100 nm node technology, newer packages like 2000 pin flip-chip
package and stacked die/package are coming up. The large pin count
makes these devices very harsh on CDM ESD protection circuits[1]. Newer
system on chip ICs have integration of analog, digital and RF circuits on
the same package, this leads to very large and complicated packages
with large number of pins and several power lines. The ESD protection
circuit required for such ICs are very complicated, but the space available
for the protection circuit is small. All these factors have created a
roadblock for the use of traditional ESD protection components .

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Figure 4.1: Schematic of the ESD Protection Circuit using PVS

This has lead to the development of Polymer Voltage

Suppressor(PVS), a new technology that has the required low capacitance
for today’s high frequency products. This material is made up of
conducting nano particles embedded in an epoxy like polymer. When a
voltage greater than a select able trigger voltage is applied across the
polymer the nano particles start to conduct and clamp the voltage to a
low value[1, 12].

The higher number of passive components needed for high density,

high
frequency ICs, has led to continuous shrinking of passive components
size,
and an increasing trend to embedding passive resistors and capacitors in
the PCB. National Electronics Manufacturing Technology Roadmap (NEMI)
focuses to reduce the number of passive components on the PCB by
embedding passives in the PCB[13]. Embedding ESD protection in the IC
package or the printed circuit board (PCB) is therefore logical and has
numerous benefits .

The major advantages of using Polymer Voltage Suppressor are, firstly

the trigger voltage of polymer voltage suppressor can be varied easily to
suit any requirement. PVS has a very fast response time of 1ns so the
detection and control of an ESD pulse is very fast. PVS offer a very small
capacitance to the system and therefore does not degrades the input
even in very high frequency applications. PVS does not require a complex
trigger circuit and can be embedded in the PCB so it saves a lot of circuit
board space.

It has been shown that the laminate used for EPI-FLO PVS connector
arrays is suitable for direct embedding in PCB. The PVS connector arrays
provide multiple line ESD protection without using PCB space [14]. Figure
4.2 shows Electronic Polymers Inc. embedded EPI-CORETM in a 4 layer
printed circuit board of a RF module.

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Figure 4.2: Fabrication Design for embedded EPI-CORE ESD protection

layer in a 4 layer RF module

CONCLUSION
High tech companies lose at least 4-6 percent of annual gross sales due
to
electrostatic discharge (ESD) every year .So the study of ESD protection
devices worth a lot. This report discusses general ESD protection
principles, basic devices used as ESD protection structures, the
underlying device physics ,recent advancements in the ESD protection
devices and future roadmap .Thus this report gives relevant ideas on ESD
protection devices.

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BIBLIOGRAPHY
[1] Charvaka Duvvury. Electrostatic protection for semiconductor
electronics. Distinguished Lecture Series at Georgia Institute of
Technology,January 2008.
[2] Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang. ”ESD Test Methods on
Intergated Circuits: An Overview”. IEEE, 2001.
[3] Charvaka Duvvury. Esd protection device issues for ic design. IEEE
custom integrated circuits conference, 2001.
[4] Harald Gossner. Optimization Strategy for ESD Robust Systems.
IWPSD IIT Bombay, December 2007.
[5] Kun-Hsien Lin, Ming-Dou Ker. ”Electrostatic discharge protection
scheme without leakage current path for CMOS IC operating in
powerdown mode condition on a system board”. Microelectronics
Reliability, 46:301–310, 2006.
[6] T.-Y. Chen, C.-Y. Wu, H.-H. Chang, Ming-Dou Ker. ”Design and
analysis of the on-chip ESD protection circuit with a constant input
capacitance for high-precision analog application”. Proc. of IEEE Int.
Symp. on Circuits and Systems, 5:61–64, 2000.
[7] Vijay Reddy Mark Rodder Ajith Amerasekera, Charvaka Duvvury.
Substrate triggering and salicide effects on esd performance and
protection circuit design in deep submicron cmos processes. IEDM,
pages 547–550, Dec 1995.
[8] Ajith Amerasekera, Charvaka Duvvury. ”The impact of technology
scaling on ESD robustness and protection circuit design”. Proc. 16th
EOS/ESD symp., October 1994.
[9] Jeffrey T. Watt, Andrew J. Walker. ”A hot carries triggered SCR for
smart power bus ESD protection”. IEDM., pages 341–344, 1995.

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[10] Ming-Dou Ker. ”Area-Efficient VDD-to-VSS ESD clamp circuit by

using substrate triggering field oxide device for whole chip
protection”. Proc. of the International Symposium on VLSI
technology, systems and applications, pages 69–73, 1997
[11] H. Gossner, J.Schneider. ”Novel Devices in ESD Protection”. IWPSD,
December 2007.
[12] Karen Shrier. ”ESD protection of an RF integrated circuit by
embedding protection in the IC package printed circuit board”.
2007.
[13] NEMI Roadmap for passives, 2000.
[14] Electronic Polymers Inc website. EPI-FLO Surface Mount ESD
Suppressors
www.electronicpolymers.com

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