Chapter 5 The MOSFET

Metal Oxide Semiconductor

Field Effect Transistor
5.1
5.2
5.3
5.4

MOS Structure
MOSFET Basics & Device Physics
MOSFET Circuit Models
SPICE Analysis

Literature: Pierret, Chapter 16&17, page 563-637

Jaeger, Blalock, Chapter 4, page 145-202
Acknowledgement Oliver Brand for slides

MOSFET Device Structure

Metal Oxide Semiconductor Field Effect Transistor
Most important device
structure in VLSI
First MOSFET: 1960
4-terminal device: gate,
substrate, drain, source

Basic Device Principle (n-channel MOSFET)

Positive gate voltage depletes holes underneath the gate oxide
Vg > VT (threshold voltage): large electron concentration (inversion)
underneath gate oxide: np > pp0
As a result, a conducting channel is formed between source and
drain, resulting in a current flow in case VD 0
Switching Device: ON: Vg > VT; OFF: Vg < VT

5.1 MOS Capacitor

5.1.1 Band Diagram
5.1.2 Electrostatics
5.1.3 The Si-SiO2 MOS Capacitor

Literature:

Pierret, Chapter 16, page 563-599

MOS Capacitor

Pierret, Fig. 17.1

5.1.1 Energy Band Diagram

Assumptions:
Thick metallic gate, i.e. equipotential region
Perfect insulator, i.e. no dc current
No charges in oxide or interface
Uniformly doped semiconductor
Sufficiently thick semiconductor having field-free region close to
contact
One-dimensional structure
Flat-band condition: M = S = + (EC EF)FB
Work function : Energy difference between vacuum level E0
and Fermi Energy EF
Electron affinity : Energy difference between vacuum level E0
and conduction band energy EC

Band Structure of Individual Materials

N-Type

Pierret, Fig. 16.2

Work Function & Electron Affinity

Pierret, Fig. 16.2

E0
M
S

vacuum level
metal work function (fundamental property of particular metal)
= 4.28 eV for Al
= 4.33 eV for Ti
= 4.50 eV for Cr
= 4.55 eV for W
= 5.10 eV for Au
= 5.65 eV for Pt
semiconductor work function (depends on material & doping)
electron affinity = E0 EC (fundamental property of semiconductor)
= 4.03 eV for Si
= 4.07 eV for GaAs
=4.00 eV for Ge

MOS Capacitor
Equilibrium Energy Band Diagram

N-Type

No band bending
under equilibrium,
because M = S!

Pierret, Fig. 16.3

MOS Capacitor
Biased Band Diagram

Bias Vg applied to gate electrode

Fermi energy:

N-Type Semiconductor

EF (metal) EF (semicon.) = qVg

Note:
EF is constant inside the
semiconductor because there is
no dc carrier flow through the
insulator
No band bending inside the
metal because it is considered an
equipotential region
Constant energy slope inside
insulator because there are no
charges inside it and thus the
electric field is constant across it
Pierret, Fig. 16.5

MOS Capacitor (N-Type)

Biasing Regions I
Accumulation
Vg > 0

Depletion
small Vg < 0

Pierret, Fig. 16.5

MOS Capacitor (N-Type)

Biasing Regions II
Onset of Inversion
Vg = VT
E
E
= 2 "#E E
i,surface

ps = ni e
= ni e

i,bulk

i,bulk

$
%

(Ei,surface EF )/kT
(EF Ei,bulk )/kT

= nbulk = ND

Inversion
Vg < VT

Pierret, Fig. 16.5

MOS Capacitor (P-Type)

Biasing Regions

Pierret, Fig. 16.6

5.1.2 MOS Capacitor Electrostatics

Potential (x) inside semiconductor

P-Type

1
(x) = #$Ei (x) Ei,bulk %&
q

Surface potential s
s =

1#
%
$Ei,bulk Ei,surface &
q

Fermi potential F
(
1$
& )> 0 for p type
E

E
%
F'
q i,bulk
*< 0 for n type
( kT $N &
-+ ln + A , for p type
- q % ni '
F = )
- kT $ND &
- q ln + n , for n type
% i'
*
F

Pierret, Fig. 16.7

s = 2 F at onset of inversion
s > 2 F in inversion
0 < s < 2 F in depletion

MOS Capacitor Electrostatics

Depletion Region (P-Type Semiconductor)
Assumptions:
P-type semiconductor
Constant charge density in depletion region:
= q NA for 0 x W
Electric Field (boundary condition: (W) = 0):

qNA
d

dx K s0
K s0

qNA
(x) =
(W x)
K s0

Electrostatic Potential (boundary condition: (W) =0):

qNA
= (x) =
(W x)2
2K s0

MOS Capacitor Electrostatics

Depletion Region (cont.)
Surface Potential s = (0):

qNA
s =
W2
2K s0
Width of Depletion Region W and Maximum Width at Onset
of Inversion WT:

2K s0
W=
s
qNA
2K s0
4K s0kT #NA &
WT =
2F =
ln % (
2
qNA
q NA
$ ni '
How does s depend on Vg in depletion mode?

MOS Capacitor Electrostatics

Gate Voltage Relationship
How does s depend on Vg in depletion mode?

EFm

EFs

Vg = semi + oxide = s + oxide

!"#
=s

No charges inside the oxide with thickness x0, i.e. oxide = 0, yields
doxide oxide
=
=0
dx
K o 0

oxide = oxide = const.

oxide =

oxide dx = x0 oxide

x 0

The electric field inside the oxide can be obtained from the
boundary condition stating that the dielectric displacement D
at the oxide-semiconductor interface must be continuous:

Doxide = Dsemi,x=0

oxide = K s semi
Ko

Ks = 11.8 for Si
Ko = 3.9 for SiO2

MOS Capacitor Electrostatics

Gate Voltage Relationship (cont.)
Resulting in a gate voltage Vg in the depletion region
Vg = s +

Ks
x0
Ko

Vg = s +

Ks
2qNA
x0
s
Ko
K s 0

semi (0)
0 s 2 F

with the electric field at the semiconductor surface

s 0
qNA
qNA 2K
semi (0) =
W=

K s 0
K s 0 qNA s
=

2qNA
s
K s 0

MOS Capacitor
Gate Voltage Vg vs.
Surface Potential s
P-Type
Surface potential is
rather rapidly varying
with Vg in the depletion
region, but not in the
accumulation or
inversion region
In the accumulation and
inversion regions,
changes in the applied
voltage are dropped
almost totally across the
oxide

Accum.

Depletion

Inversion

Pierret, Fig. 16.10

5.1.3 Si-SiO2 MOS-C

Work Function Difference

Metal-SiO2-Si is the most

extensively studied MOS
capacitor
For commonly used metal
electrodes (e.g. polysilicon and
aluminum), the work function
difference is not zero:

MS = qMS = M S 0

The work function difference

results in a band bending in the
Si and SiO2 even in equilibrium,
i.e. Vg = 0
In order to reach flat-band
conditions, the so called flatband voltage VFB has to be
applied to the gate: VFB = MS

Sze, Fig. 6.8

Si-SiO2 MOS Capacitor

Work Function Difference

Before
Contact

After
Contact
Sze, Fig. 6.9

Si-SiO2 MOS Capacitor

Interface Traps and Oxide Charges

In addition to the work function
difference, the MOS capacitor is
affected by charges in the oxide
and traps at the Si-SiO2
interface
Types of interface traps and
oxide charges:
Interface-trapped charges Qit
Fixed oxide charges Qf
Oxide-trapped charges Qot
Mobile ionic charges Qm

Pierret, Fig. 18.4

Si-SiO2 MOS Capacitor

Oxide Charges and Flat-Band Voltage

VFB

1
=
Co

% 1 xo
(
'
x (x) dx*

x
'& 0 0
*)

(a) Ideal MOS-C

Often, the flat band voltage is

expressed by the effective oxide
charges

VFB

Sze, Fig. 6.12

Influence of charges on the flatband voltage depends on

location of charges within the
oxide:
Minimal influence at the
metal-SiO2 interface
Maximal influence at the SiSiO2 interface

Q + Qm + Qot
= MS f
Co

(b)Parallel shift due to oxide charges

(c) Slope change due to interfacetrapped charges

1
with e.g. Qm =
x0

xo

x m (x) dx

5.2 MOSFET Device Characteristics

5.2.1 Qualitative Theory of Operation
5.2.2 Derivation of IV Characteristic
Long-Channel MOSFET: Square-Law Theory
5.2.3 Threshold Voltage
Workfunction Difference
Oxide Charges
5.2.4 MOSFET Types and Circuit Symbols
Literature:

Pierret, Chapter 17.1-17.2, page 611-630

(for VT: Pierret, Chapter 18, page 645-681)
Jaeger, Blalock, Chapter 4.2-4.4, page 148-165

N-Channel MOSFET Device Structure

Pierret, Fig. 17.1

N-Channel MOSFET
Device Operation
Vg < VT: Depletion (or Accumulation)
No conductive path between
source S and drain D
Drain current ID = 0 for all VD > 0
Vg VT: Inversion
Conductive channel (n-type)
between source S and drain D
Drain current ID > 0 for all VD > 0
Open Question:
ID(VD) Characteristic?
Jaeger, Blalock, Fig. 4.5

5.2.1 MOSFET
Qualitative Theory
ID(VD) Characteristic

Sze, Fig. 6.17

MOSFET Linear Regime

Linear Regime: Vg VT and VD Vg
Width of and carrier concentration in
the n-type inversion layer only
depend on Vg (and not on VD), i.e.
are constant along the length L of
the channel
As a result, the channel resistance
Rchannel does not depend on VD, but
only on Vg

ID = R1
VD
channel
For a given Vg, ID increases linearly
with VD
Rchannel decreases with increasing
Vg, thus the slope of ID vs. VD
increases with increasing Vg

Neamen, Fig. 11.40

MOSFET Non-Linear Regime

Non-Linear Regime
Vg VT and VD < VD,sat
Width of and carrier concentration in the
n-type inversion layer depend on Vg
and VD, i.e. are not constant along the
length L of the channel
As a result, the channel resistance
Rchannel increases with increasing VD;
effective voltage drop between gate and
channel is reduced towards the drain
Leveling-off of ID(VD) characteristic
Note: Jaeger/Blalock call the linear/
nonlinear regime the triode region
Neamen, Fig. 11.40

MOSFET Pinch-Off Point

Pinch-Off Point
Vg VT and VD = VD,sat
The voltage applied across the MOS
capacitor at the edge of the drain
V = Vg VD,sat is just enough to reach
the onset of inversion
dID
dVD V

= 0 with VD,sat = Vg VT

D =VD,sat

This is known as the pinch-off point

VT is the threshold voltage (the voltage
to achieve the onset of inversion) for
VD = 0
Neamen, Fig. 11.40

MOSFET Saturation Regime

Saturation Regime
Vg VT and VD VD,sat
Pinched-off portion of the channel widens
(L in Pierret, Fig. 17.2); the pinched-off
region is depleted, i.e. it has few carriers
and thus a low conductance
As a result, most of the drain voltage in
excess of VD,sat is dropped across a small
L:
ID = const. for VD VD,sat if L L
(long channel approximation)
At the pinch-off point, the carriers are
injected into the depletion region and are
swept by the strong electric field to the
drain contact

Neamen, Fig. 11.40

5.2.2 MOSFET IV Characteristic

Assumption: N-channel MOSFET
Drift current dominating in channel
+ VD
Vg

Carrier mobility in
channel n n(bulk)

GND

because of
coordinate system
+Jn in y direction

Jn Jny q nn y
Pierret, Fig. 17.6

=
d
= +q nn
dy

Note: n and n depend on x and y coordinate

MOSFET IV Characteristic (cont.)

Current flow is restricted to surface channel
x c (y)

ID =

ny

dx dz = Z

x (y)

c
d
Jny dx = Z
q n (x,y) n(x,y) dx
dy
0
!####
"####$
n (y) Qn (y)

( )

Assumption:
does not depend on x

ID = Z n (y) Qn (y)

Effective
mobility

d
dy

Assumption:
n (y) = n

Integrate over the channel length:

VD

dy = Z

Charge in inversion
layer at y [C/cm2]

VD

(y) Q (y) d = Z Q
n

MOSFET IV Characteristic (cont.)

Z n
ID =
L

VD

d
0
!
#"#
$
n

=?

Assumption: Charges added to the metal electrode after the

onset of inversion (Vg VT) result in added mirror charges in the
inversion layer only, leaving the depletion layer unchanged (see
delta-depletion theory of MOS-C): Square-Law Theory

Qgate = Qsemi = Qn
Qgate Co Vg =
!"#
[C/cm2 ]

K
Co (Vg VT ) = o 0 (Vg VT )
$
xo
Co / A

K o0
Qn =
(Vg VT )
xo

MOSFET IV Characteristic (cont.)

Effective potential drop across the MOS-C along the
channel length L is [Vg (y)]
K o0
Qn (y) =
(Vg VT (y))
xo
Inserting in the drain current equation yields
Z n
ID =
L

VD

Z nC o
ID =
L

Z n
0 Qn d = L

VD

K o0
0 x (Vg VT ) d
o

%
VD2 ( for 0 VD VD,sat and Vg VT
'(Vg VT )VD
*
2 *)
'&
VD,sat = Vg VT

Square-Law Theory

ID,sat =

ZnCo
2L

(Vg VT )2

MOSFET IV Characteristic
Square-Law Theory

Z nC o "
VD2 %
ID =
$(Vg VT )VD '
L $#
2 '&

Neamen, Fig. 11.48

and Fig. 11.49

MOSFET IV Characteristic
Square-Law Theory
Linear/Non-Linear Regime (Triode Region)
0 VD VD,sat = Vg VT
Z nC o "
VD2 %
ID =
$(Vg VT )VD '
L $#
2 '&
Z nC o "
ID
(Vg VT )VD %&
#
L

for VD Vg VT

Saturation Regime (Pinch-Off Region)

VD > VD,sat = Vg VT
ID =

Z nC o "
2$
(V

V
)
T %
2L # g

MOSFET IV Characteristic
Square-Law Theory

Jaeger, Blalock, Fig. 4.10

MOSFET IV Characteristic
Linear Regime
NMOS device (n-channel MOSFET) in common-source
configuration operated in linear regime
Example: VT = VTN = 1 V
K n = CO = 250 A / V 2

Jaeger, Blalock,
Fig. 4.7

Z nC o #
(Vg VT )VD %&
$
L
1
1
#
%
#Z C
%
I
* = ) n o (V V )* = R (V )
Ron = ) D
g
T
on
g
) VD V 0 *
L
$
&
$
&
D
ID

Voltage-Controlled Resistor

MOSFET IV Characteristic
Limitations of Square-Law Theory

Use Charge-Sheet or
Exact-Charge theories

1. Depletion layer width depends on Vg and VD, i.e. W =

W(y); the square-law theory assumes that all added
charges are added to the inversion layer; in reality, some
of these charges are added to the depletion layer; thus,
ID is always overestimated in the square-law theory: use
Bulk-Charge Theory instead!
2. The drain current is assumed to be zero for Vg < VT; in
reality, a channel exists even for Vg < VT, resulting in a
small sub-threshold current
3. The drain current does not self-saturate in the squarelaw (and bulk-charge) theory; the saturation in the pinchoff portion (VD > VD,sat) of the IV characteristic is
artificially constructed

5.2.3 Threshold Voltage

No Work Function Difference
Assuming M = S and an n-channel MOSFET, the threshold
voltage is identical to the MOS-C gate voltage at the onset of
inversion (s = 2 F)
=C1
"$=W
#T$%
o
!
K x 4qNA
x
40K s
VT = 2F + s o
F = 2F + o qNA
F
Ko
K s0
0K o
qNA
VT = 2F +

qNA WT
Q
2F B
Co
Co

with the charge per area QB = q NA WT in the depletion region

at the onset of inversion
Similarly, the threshold voltage for a p-channel MOSFET is
(QB = + q ND WT)
K x 4qND
Q
VT = 2F s o
(F ) = 2F B
Ko
K s0
Co

Threshold Voltage
Work Function Difference MS
In reality M S, i.e. a voltage
MS = q-1 (M S) has to be
applied to the gate to achieve
flat band condition
As a result, the threshold
voltage is shifted by the work
function difference:

VT = MS + 2F

QB
Co

n-channel

p-channel

>0

<0

MS

<0

<0

QB

<0

>0

Pierret, Fig. 18.1

Threshold Voltage
Work Function Difference MS

Pierret, Fig. 18.3

Threshold Voltage
Oxide Charges
With the types of oxide charges
and their charge density
(i)
(ii)
(iii)
(iv)

interface-trapped charges Qit,

fixed oxide charges Qf,
oxide-trapped charges Qot,
mobile ionic charges Qm,

the threshold voltage of the

MOSFET becomes

Pierret, Fig. 18.4

QB Qf Qit ( s ) cmQm cotQot

VT = MS + 2F

Co Co
Co
Co
Co
with 0 cm, cot 1; the charge density Qit of the interface-trapped
charges depends on the surface potential s

Threshold Voltage
Adjustment by Implantation
In modern device processing (e.g. n-channel and p-channel
MOSFETs in CMOS processes), the threshold voltage is
adjusted to the desired value by ion implantation, implanting
a controlled number of either boron or phosphorous ions into the
near-surface region of the semiconductor (in the channel region)
Under inversion bias, the additional dopant adds to the charge
near the Si-SiO2 interface (with charge density QI) and, thus,
results in a VT shift of the structure:

VT = QI / Co
Depending on the dopant type, both positive (for acceptor atoms,
B) and negative (for donor atoms, P) VT shifts are possible
Example: QI = 5 1011 cm-3 boron, xo = 10 nm yields VT = +0.23 V

5.2.4 Types of MOSFET

Sze, Fig. 6.19

Jaeger, Blalock, Fig. 4.15

MOS Transistor
Circuit Symbols

5.3 MOSFET Circuit Models

5.3.1 MOSFET DC Model
Square-Law Theory: Model Equations
MOSFET Bias Circuits
Q-Point Analysis

5.3.2 MOSFET Small Signal Model

Y-Parameter Two-Port Network
Small Signal Equivalent Circuit
Small Signal Analysis

5.3.3 Comparison MOSFET BJT

5.3.4 Common-Source Amplifier
Literature:

Jaeger, Blalock, Chapter 4.6-4.9, page 167-187

Jaeger, Blalock, Chapter 13.8-13.10, page 815-838
Jaeger, Blalock, Chapter 15.4, page 1016-1024
Jaeger, Blalock, Chapter 16.2, page 1049-1063

5.3.1 DC Models
NMOS & Square-Law Theory
Long Channel
Approximation

Short Channel
Approximation

Saturation Region
VGS > VT; VDS > VDsat

ID =

Triode Region
VGS > VT; VDS VDsat

2 %
2 &
"
#
VDS
VDS
ID = K n $(VGS VT )VDS
' ID = K n %(VGS VT )VDS
(
2 '&
2 ('
$#
%$

Cut-Off Region
VGS < VT

ID = 0

Kn
(VGS VT )2
2

ID =

Kn
(VGS VT )2 (1+ VDS )
2

ID = 0

K n = nCox (W / L)

In addition, we assume IG = 0 and IB = 0 (substrate current)

How to Perform Q-Point Analysis?

1. Educated guess: Assume the region of
operation (most often the saturation region)
2. Use circuit analysis (might require Thvenin
equivalent circuit) to find VGS
3. Use VGS to calculate ID, and ID to determine
VDS (using MOSFET model and KVL)
4. Check the validity of the operation region
assumptions
5. Change assumptions and analyze again if
necessary

Constant Gate-Source Voltage Bias

Voltage divider
biases gate
terminal
With IG = 0,
we find
VGS = 3 V
VT = 1 V
Kn = 25 A/V2
R1 + R2 is large
to minimize power
Jaeger, Blalock, Fig. 4.24
supplied by VGG
Assuming biasing in the saturation region, we find
Saturation Model : ID =
KVL : VDD = ID RD + VDS

Kn
(VGS VT )2 = 50 A
2
VDS = 5 V

Because VDS = 5 V > VGSVT= 2 V, the MOSFET is in saturation

Constant Gate-Source Voltage Bias (cont.)

Q-point is (ID, VDS) = (50 A, 5 V) at VGS = 3 V
Note: If we know the mode of operation (in this case saturation),
we can calculate VGS from ID and VDS;
thus, the Q-point is defined by ID and VDS only
Why is the constant gate-source voltage bias typically NOT
used in practical applications?
Obtained Q-point is very sensitive to variations of the
transistor parameters (Kn, VT): ID increases linearly with Kn
and quadratically on VT
Better bias circuits: two or four-resistor bias, bias with
current mirror
How would you obtain the above Q-point if = 0.02 V-1 0?
How would you perform a load-line analysis of the circuit?

MOSFET Four-Resistor Bias

Most general and
important bias method
Advantages:
Feedback circuit
helps stabilize the
Q-point upon variation
of transistor
parameters and
temperature
Only single voltage
supply needed
Lets analyze this
circuit.. VT = 1 V
Kn = 25 A/V2

Jaeger, Blalock, Fig. 4.27

MOSFET Four-Resistor Bias

Analysis
1. Assume a region of operation: Saturation
2. Perform circuit analysis to find VGS
(a) Find Thevenin equivalent circuit
for gate bias network
(see previous page):
VEQ =
REQ =

R1
V =4V
R1 + R2 DD
VEQ
VDD R2

R1R2
= 600 k
R1 + R2

Jaeger, Blalock, Fig. 4.28

(b) Use KVL and MOSFET model to extract VGS

VEQ =

IGREQ
!
= 0,because IG = 0

+ VGS +

(ID + IG )
"#$
= ID ,because IG = 0

RS

VEQ = VGS + IDRS

MOSFET Four-Resistor Bias

Analysis (cont.)
Solve quadratic equation to obtain VGS
"
Kn
2
K nRS
ID =
(VGS VT ) $
2
V
=
V
+
(V

V
)
#
2
EQ
GS
GS
T
2
$
VEQ = VGS + IDRS %

yielding VGS = 2.71 V (which would mean cut-off mode) and

VGS = 2.66 V
3. Use VGS to calculate ID, and ID to determine VDS
Kn
(VGS VT )2 = 34.4A
2
VDD = IDRD + VDS + (ID + IG ) RS
!"#

ID =

VDS = VDD ID (RD + RS ) = 6.08 V

=ID ,because IG =0

4. Check the validity of the operation region assumptions

VGS VT = 1.66 V < VDS = 6.08 V

Saturation

MOSFET Four-Resistor Bias

Analysis (cont.)
Resulting Q-point: (ID, VDS) = (34.4 A, 6.08 V)
Why is the bias point more stabilized compared to
constant VGS bias?
Bias circuit uses negative feedback to stabilize bias point
ID =

Kn
(VGS VT )2
2

and VEQ = VGS + IDRS

If ID rises (because of parameter or temperature variations),

VGS must decrease because VEQ is fixed; but a decrease in
VGS will tend to restore (decrease) ID, thus stabilizing the
operating point of the n-channel MOSFET
In the previous circuits it was assumed that the bulk contact is
connected to the grounded source contact (three-terminal
device); if this is not the case, the analysis become more
involved (body effect)

And what about PMOS FETs?

PMOS bias techniques
mirror those of NMOS bias
examples
Source of PMOS transistor
is drawn on top of device
because it is normally
connected to a potential
higher than the drain
For PMOS transistors
the drain current ID is
POSITIVE when
coming OUT of the
drain terminal and
the values for VGS and
VDS will be NEGATIVE
Try to analyze the shown
PMOSFET bias circuit

Jaeger, Blalock, Fig. 4.30

Current Sources
Current sources are widely
used to establish transistor
working points in integrated
circuits
Ideal current source delivers
constant current independent
of voltage across the source
How can we use MOSFETs
as effective current sources?
MOS transistors operated in
saturation region (pinched-off
region) deliver constant
current for VDS > VDsat

MOSFET Current Source

How can we achieve output characteristic shown on previous page?
Use NMOS transistor operated with constant gate-source voltage
VGS = 3 V (with VGS > VT)
As long as VDC VDsat, the MOSFET is biased in the pinched-off
region and the
drain current ID
remains constant
K
ID = n (VGS VT )2
2
Assuming VT = 1 V
and Kn = 25 A/V2,
we find IDC = ID =
50 A

MOSFET Current Mirror

Fundamental building block in

electronic circuit design defining
currents and current ratios (from
a single reference current)
Current mirror relies on matched
transistor parameters VT, Kn,
and W/L (rather than absolute
parameter values) to deliver
IO = IREF
Note: in a CMOS process,
absolute device parameters might
have 20-30% spread, but
neighboring transistor parameters
are typically matched to within
1-2%; as a result circuit designers
rely on ratios rather than absolute
values

NMOS Current Mirror

Assumption: Transistors M1
and M2 have matched
parameters VT, Kn, and W/L
Gate currents IG of both
transistors are zero, i.e. the
reference current must flow
into drain of M1: IREF = ID1
With VDS1 = VGS (> VGS VT),
the transistor M1 is in
saturation and
IREF = ID1 =

Kn
(VGS VT )2 (1+ VDS1)
2

Similarly, the current through

M2 becomes
IO = ID2 =

(1+ VDS2 )
Kn
(VGS VT )2 (1+ VDS2 ) = IREF
I
2
(1+ VDS1) REF

NMOS Current Mirror (cont.)

For equal values of VDS, the
output current mirrors the
reference current
Note: In most applications
VDS1 VDS2, resulting in a
slight mismatch of the
currents
By designing the transistors
M1 and M2 with different W/L
ratio, current ratios can be
defined!
IO = IREF

(W / L)2 (1+ VDS2 )

(W / L)1(1+ VDS1)

Jaeger, Blalock, Fig. 16.3

Note: Current mirror is operated between
ground and negative supply; compared to
slide 14 the supply voltage is just shifted

Multiple Current Mirrors

Current mirrors are used to

generate multiple currents from a
single reference current, as
needed in more complex circuits
The displayed circuit generates
three currents ID2, ID3 and ID5 from
the reference current IREF
The resistance R defines the
reference current with
R=

(VDD VSS ) + VGSP VGSN

IREF

Kn
(VGSN VTn )2
2
K
= ID1 = IREF = p (VGSP VTp )2
2

ID1 =
ID4

Large resistors R are typically

realized with a transistor in
integrated circuit design

274 k

5.3.2 Small Signal Analysis

Small signal model for FET to
analyze (small signal) AC
behavior of e.g. commonsource amplifier
DC voltages/currents (all
capital letters) superimposed
by AC currents/voltage (all
small letters)
v GS = VGS + v gs

v DS = VDS + v ds

iG = IG + ig

iD = ID + id

Small signal model based on

y-parameter two-port network
(expressing currents as a
function of the voltages)

Jaeger, Blalock, Fig. 13.21

ig = y11v gs + y12 v ds
id = y21v gs + y22 v ds
!i $ ! y
y12 $ ! v gs $
g
11
# & = ##
&& ## &&
#i & y
" d % " 21 y22 % " v ds %

Y-Parameter Definition (cont)

Y-parameters depend on the DC working point (Q-point) of the
MOSFET and have units of [-1]
Y-parameters are defined as partial derivatives of complete port
variables
y11 =
y21 =

iG
v GS
iD
v GS

Qpoint

Qpoint

IG
VGS
ID
VGS

y12 =
Qpoint

y22 =
Qpoint

iG
v DS
iD
v DS

Qpoint

Qpoint

IG
VDS

Qpoint

ID
VDS

Qpoint

Derivatives are evaluated from the large-signal model

equations, e.g. in the saturation region
(vDS vGS VT and iG = 0)
K
ID = n (VGS VT )2 with K n = nCox (W / L)
2

Y-Parameter Definition (cont.)

Saturation Mode
y11

Long - Channel ( = 0)
=0

Short - Channel ( 0)
=0

y12

=0

=0

y21 = gm

= K n (VGS VT )

y22 =

1
ro

=0

Jaeger, Blalock, Fig. 13.21

= K n (VGS VT )(1+ VDS ) =

=

2 ID
VGS VT

Kn
ID
(VGS VT )2 =
2
1+ VDS

iG = 0

Y-Parameter Definition (cont.)

Saturation Mode
Because the gate terminal is insulated from the
channel by the gate oxide, the input resistance 1/y11
of the FET is infinite
Transconductance gm and output resistance ro:
gm = y21 =

ID
VGS VT
2

= K n (VGS VT )(1+ VDS ) = 2K n ID (1+ VDS )

1
+ VDS
1
1
ro =
=

y22
ID
ID

Limits of Small-Signal Model

What are the limits of the linear operation of the MOSFET, i.e.
what are the limits for the input voltage amplitude vgs to enable
use of small-signal model?
Assume n-channel MOSFET in saturation region with vGS = VGS
+ vgs and iD = ID +id:
K
iD =

iD = ID + id =

(v GS VT )2

Kn
K
2 $
(VGS + v gs VT )2 = n "#(VGS VT )2 + 2(VGS VT )v gs + v gs
%
2
2

By comparison we find
id =

Kn "
2 $
2(VGS VT )v gs + v gs
#
%
2

For a linear relation between id and vgs, we must request

2
v gs
2(VGS VT )v gs

or

v gs 2(VGS VT )

Small-Signal Model for PMOS

Transistors
NMOS

Small signal model for

PMOS transistor is identical
to that of the NMOS device

Jaeger, Blalock, Fig. 13.24

PMOS

5.3.3 Comparison Small-Signal Model

for BJT and MOSFET
Parameter

BJT
IC
(kT/q)

Transconductance gm

Relation

MOSFET

2ID
2K nID
VGS VT

1 + VDS
1

ID
ID

Input Resistance r

o o (kT/q)
=
gm
IC

Output Resistance ro

VA + VCE VA

IC
IC

Amplification Factor gmro

VA + VCE
VA

(kT/q)
(kT/q)

2( 1 + VDS )
VGS VT

Small-Signal Requirement

v be (kT/q)

v gs 2(VGS VT )

IC = IS e

qVBE /kT

" V %
1 $1+ CE '
VA &
#

ID =

Kn
V VT
2 GS

) (1+ V )
DS

Comparison Small-Signal Model

for BJT and MOSFET

Small signal parameters of BJT and MOSFET are directly controlled by

the design of the Q-point
For a given operating current, the MOSFET has a much smaller
transconductance than the BJT
The MOSFET transconductance increases with the square root of the
drain current, the BJT transconductance is directly proportional to the
collector current
Transconductance of MOSFET depends on geometry W/L,
transconductance of BJT is geometry independent
Output resistance of BJT and MOSFET are similar for given operating
point (ID, VDS) = (IC, VCE), because 1/ is similar to VA
Amplification factor of BJT is larger than amplification factor of
MOSFET
Amplification factor of MOSFET decreases with increasing operating
current, whereas amplification factor of BJT is independent of operating
point
MOSFET small signal model can handle larger values of vgs than the
vbe of the corresponding BJT

5.3.4 Common-Source Amplifier

FET version of common-emitter amplifier (see Chapter 4.3)

Goal: Calculate amplifier voltage gain (see Jaeger, Blalock, Chapter 13.10)
GND

DC Analysis:
Find equivalent circuit by
replacing all capacitors with
open circuits and inductors
with short circuits
Find the Q-point from the DC
equivalent circuit using
appropriate large-signal model
for the transistor
AC Analysis:
Find AC equivalent circuit by replacing all capacitors by short circuits and
all inductors by open circuits, replacing DC voltage sources by ground
connections and replacing DC current sources by open circuits
Replace FET by its small-signal model
Simplify the resulting AC circuit as much as possible

Common-Source Amplifier
DC Analysis

Parameters: R1 = 430 k, R2 = 560 k,

RD = 4.3 k, RS = 1.3 k, VDD = 12 V,
Kn = 0.5 mA/V2, VT = 1 V, = 0.0133 V-1
Thvenin equivalent of gate bias circuit:
VEQ =

R1
V = 5.21 V
R1 + R2 DD

REQ =

R1R2
= 243.2 k
R1 + R2

Extract VGS, VDS, ID:

K
ID = n (VGS VT )2 (1+ VDS )
2
VEQ = VGS + IDRS

VDD = (RD + RS )ID + VDS

ID = 1.44 mA, VGS = 3.34 V, VDS = 3.93 V

Common-Source Amplifier

AC Analysis

Additional Parameters:
Ri = 1 k, R3 = 100 k
RG = R1 || R2 = 243.2 k
Small signal parameters:
gm = y21 =

2 ID
= 1.23 mS
VGS VT

1
1 + VDS
ro =
=
= 54.9 k
y22
ID

RL = ro || RD || R3= 3835
Calculate vgs, vo and vo/vi:
RG
v gs =
v = 0.996 v i
Ri + RG i

v o = RLgmv gs = 4.72 v gs
A v = v o / v i = RLgm

RG
= 4.7
Ri + RG

Common-Source Amplifier
AC Analysis

If RG Ri, then vgs vi and the

voltage gain of the commonsource amplifier becomes

A v gmRL

i.e. the product of the transistor

transconductance gm and the
effective load resistor RL
The sign indicates that input
and output waveform are 180
out of phase
The effective load resistance RL
consists of output resistance ro
in parallel with drain-bias
resistor RD and external load
resistor R3

Simplified equivalent circuit

for RG Ri:

Common-Source Amplifier
Input/Output Resistance

Input Resistance = total

resistance looking into amplifier
at coupling capacitance C1
Attach test signal vx to input side
and measure ix:
v
Rin = x = RG = 243 k
ix
Output Resistance = total
resistance looking into amplifier
at coupling capacitance C2
Attach test signal vx to output
side and measure ix (keep in
mind that vgs = 0 in this case):

Rout

ro RD
vx
=
= ro ! RD RD = 4.3 k
ix

Input Resistance

Output Resistance

5.4 SPICE Analysis

5.4.1 SPICE Model for MOSFET
5.4.2 Implemented Non-Idealities
Channel Length Modulation
Substrate Bias (Body Effect)
Capacitances
Series Resistances
5.4.3 Sample Problem: Putting It All Together
Jaeger, Chapter 4.5-4.7, page 165-172
Jaeger, Chapter 4.2.7-4.2.9, page 157-161

5.4.1 SPICE Model Equations

Level-1 Model for NMOS Transistor
Triode Region
v DS %
W"
iD = KP
$ v VT
' v 1+ LAMBDA v DS
L # GS
2 & DS

Saturation Region
iD =

KP W
v GS VT
2 L

) (1+ LAMBDA v )
DS

Threshold Voltage
VT = VTO + GAMMA

v SB + PHI PHI

Junction Capacitances
CJ =

CJO
MJ

! v $
#1+ R &
" PB %

and CJSW =

CJSWO
MJSW

! v $
#1+ R &
" PB %

Jaeger, Blalock, Fig. 4.18

With again many Parameters

Parameter

Name

Default

KP

20 A/V2

VTO

1V

Threshold Voltage

VT

Surface Potential 2 F

PHI

0.6 V

Body Effect

GAMMA

Channel Length Modulation

LAMBDA

UO

600 cm2/Vs

G-D Capacitance per unit width

CGDO

G-S Capacitance per unit width

CGSO

G-B Capacitance per unit width

CGBO

Junction Bottom Cap. per unit area

CJ

Grading Coefficient

MJ

0.5 V0.5

Transconductance
Zero-Bias Threshold Voltage

Mobility

Comment

calculated

typ. 0.02 V-1

SPICE Parameters (cont.)

Parameter

Name

Default

Sidewall Capacitance

CJSW

Sidewall Grading Coefficient

MJSW

0.5 V0.5

TOX

100 nm

Junction Saturation Current

IS

10 fA

Built-In Potential

PB

0.8 V

Ohmic Drain Resistance

RD

Ohmic Source Resistance

RS

Oxide Thickness

Comment

And for a simple MOSFET.

Parameter

Name

Default

KP

20 A/V2

Zero-Bias Threshold Voltage

VTO

1V

Channel Length Modulation

LAMBDA

Transconductance

KP W
iD =
v VT
2 L GS

) (1+ LAMBDA v )
DS

v DS %
W"
iD = KP
$ v GS VT
' v DS 1+ LAMBDA v DS
L #
2 &

VT = VTO
CJ = CJSW = 0

What are some of the non-idealities described in the SPICE model?

5.4.2a Channel Length Modulation

ID-VDS output characteristic of real

MOSFET has small positive slope
in saturation region due to
channel-length modulation
Similar to base width modulation
(Early effect) of BJT
As VDS increases, the pinched-off
length L of the channel increases
and L decreases; ID is proportional
to L-1, i.e. ID increases with
increasing VDS
Model for saturation regime
including channel length
modulation

ID =

Kn
VGS VT
2

) (1+ V )
DS

with 10-3 10-1 V-1

Jaeger, Blalock, Fig. 4.11

5.4.2b Body Effect

So far it has been assumed that

the source-body voltage VSB is
zero
With VSB = 0, the MOSFET acts
as a three-terminal device

VSB 0 changes the threshold

voltage of the MOSFET; for nchannel MOSFET

VT = VT0 +

VSB + 2F 2F

The parameter is the body

effect parameter with units V0.5

Jaeger, Blalock,
Fig. 4.13&14

5.4.2c Capacitances
Internal capacitances limit high-frequency performance of
electronic devices (including MOSFET)
In logic applications, capacitances limit switching speed
In amplifiers, capacitances limit frequency at which useful
amplification can be achieved
Capacitances of NMOS transistor operated in triode region:

Jaeger, Blalock, Fig. 4.16

Capacitances of NMOS Transistor

Capacitances of NMOS transistor operated in triode region:
Gate Channel Capacitance: CGC = C!!ox W L
Gate-Source Capacitance:

CGC
WL
+ CGSO W = C!!ox
+ CGSO W
2
2
C
WL
= GC + CGDO W = C!!ox
+ CGDO W
2
2

CGS =

CGD
Gate-Drain Capacitance:
CGSO and CGDO are overlap capacitances originating from
overlap of gate with source/drain; they are specified as
capacitance per unit width with units [F/m]
In addition, source-bulk and drain-bulk capacitances CSB and
CDB exist between source/drain and bulk substrate (body); these
capacitances are associated with junction capacitances of reverse
biased pn-junctions between source/drain and substrate; each
capacitance consists of a component (CJ in [F/m2]) proportional to
the bottom area of source/drain and a sidewall component (CJSW
in [F/m]) proportional to the perimeter length
Saturation and cut-off region: see Jaeger, Blalock, page 206-207

5.4.3 Sample Problem

MOSFET Common Source Amplifier
Our old Problem:
see Chapter 5.3:
Parameters: VDD = 12 V,
Kn = 0.5 mA/V2, VT = 1 V,
= 0.0133 V-1

By hand calculation we found

ID = 1.44 mA, VGS = 3.34 V, VDS = 3.93 V

SPICE Model
Q-Point of Common-Source Amplifier
SPICE results:
VGS = 3.340 V
VDS = 3.935 V
ID = 1.440 mA

SPICE Analysis
AC Sweep: Frequency Transfer
AC sweep analysis provides frequency transfer plot as output
Analysis of choice to investigate frequency dependencies

SPICE Analysis
AC Sweep: Frequency Transfer
Vin = 1 mVp

Gain: |A| 4.70

Why do we
see a low
frequency
but no high
frequency
cut-off?

SPICE Analysis
Transient Analysis
Transient signal analysis provides waveform (at a given signal
frequency) as output signal
Analysis of choice to investigate phase relations and signal distortions

SPICE Analysis
Transient Analysis: Small Amplitude
Vin = 0.1 Vp
Av = 4.64

Gain: |A| 4.70

SPICE Analysis
Transient Analysis: Large Amplitude
Vin = 1 Vp

Gain: |A|

What is the
origin of the
distortion?
4.70