MSB Chapter3+v2

Chapter 3 The PN Junction
3.1
3.2
3.3
3.4
3.5
3.6
PN-Junction Electrostatics
I-V Characteristic
Dynamic Behavior
Diode Circuit Models
Diode Applications and Circuits
SPICE Analysis
Literature:
Pierret, Chapter 5-7
Jaeger Blalock, Chapter 3
Acknowledgement Oliver Brand for slides
ECE 3040: Chapter 3 PN Junction
The PN Junction
Circuit Symbol
P
I-V Characteristic
Forward Bias
Reverse Bias
I = Is eqVA / kT 1
3.1 PN Junction: Electrostatics

3.1.1 PN Junction Basics
Junction Approximations
Band Structure
Built-In Potential
3.1.2 Step PN Junction
Equilibrium VA = 0
External Bias VA 0
Pierret, Chapter 5, page 195-226
3.1.1 PN Junction Basics

Net Doping
ND N A
Pierret, Fig. 5.1

Example: Diffusion of acceptor atoms (e.g. boron) in n-substrate
Metallurgical junction at NA = ND or ND NA =0
Doping Profile Approximations

for PN Junctions
Step Junction
Linearly Graded Junction
Pierret, Fig. 5.2

Approximations for doping profile in pn junctions:
Step Junction: approximation for ion implantation or shallow
diffusion into lightly doped wafer
Linearly Graded Junction: approximation for deep diffusion in
moderately to heavy doped wafer
PN Junction
Band Diagram
Equilibrium requires the Fermi
level to be constant across the
device
Regions far away from the
metallurgical junction will be
unaffected
Electrons diffuse from n- to pside, holes from p- to n-side,
leaving behind unbalanced
dopant site charges
This space charge creates an
electric field (band bending),
resulting in a carrier drift
balancing the carrier diffusion
(Jtot = 0)
Pierret, Fig. 5.3
qVbi
PN Junction
Band Diagram
Equilibrium requires the Fermi
level to be constant across the
device
Regions far away from the
metallurgical junction will be
unaffected
Electrons diffuse from n- to pside, holes from p- to n-side,
leaving behind unbalanced
dopant site charges
This space charge creates an
electric field (band bending),
resulting in a carrier drift
balancing the carrier diffusion
(Jtot = 0)
Pierret, Fig. 5.5
PN Junction Built-in Potential

The built-in potential can
be calculated from the
band diagram:
Vbi =
1#
E EF
q %$ i
)pside + (EF Ei)nside &('
Pierret, Fig. 5.4
With the results from Chapter 2.5
p = NA = ni e(Ei EF )/ kT p side with NA >> ni

n = ND = ni e(EF Ei )/ kT n side with ND >> ni
we obtain
" NA %
" ND % + kT (NAND +
1(
Vbi = *kT ln$ ' + kT ln$ ' - =
ln*
2
q)
# ni &
# ni & , q * n ) i ,
PN Junction Depletion Approximation
To obtain quantitative solutions for

the electrostatic variables, the
Poisson equation needs to be
solved:
q p n + ND NA
=
=
K s 0
K s 0
This requires the knowledge of the

charge distribution, which itself (n
and p) is influenced by the potential
The depletion approximation is
often used to approximate the charge
distribution:
1. The carrier concentration n and
p is negligible in the depletion
region, i.e. for -xp x xn
2. The charge density outside the
depletion region is zero
Pierret, Fig. 5.6
Electrostatics
From charge distribution to
electric field:
=
or in 1D
=
K s 0
dx K s 0
(x)
Example:
Step Junction
1
d = (x) =
K s0
(x) dx
From electric field to electrostatic

potential:
Pierret, Fig. 5.9
dV
= V or in 1D =
dx
V(x)
dV = V(x) =
(x) dx
10
3.1.2 Step Junction: VA = 0

Assuming depletion approximation
and a step junction, the charge
density in the depletion region is
% qNA
'
= &+qND
' 0
(
xp x 0
0 x xn
x < xp or x > xn
The electric field is obtained by

integration
(x)
d =
0
1
K s 0
(x) dx
with the boundary conditions

(-xp) = (xn) = 0
Pierret, Fig. 5.9
11
Step Junction with VA = 0

Resulting electric field:
% qNA
'' K xp + x
(x) = & s 0
' qND xn x
'( K s 0
xp x 0
0 x xn
The electric potential is obtained by

a second integration
V(x)
Pierret, Fig. 5.9
dV = (x) dx
with the boundary conditions

V(-xp) = 0 and V(xn) = Vbi
12
Step Junction: Charge Considerations

The electric field must be continuous at x = 0, yielding:
qNA
qND
xp =
xn
K s 0
K s 0
qNA xp = qND xn
This constitutes that the total charge within the
depletion region must sum to zero, i.e. the positive
charge
on the n-side is balanced by the negative
charge on the p-side of the junction
This overall charge neutrality is a direct consequence
of the assumption that the electric field vanishes
outside the depletion region, as follows from Gauss
law
13
Step Junction with VA = 0

Resulting electric potential:
2
%
qNA
x
+
x
p
'' 2K
s 0
V(x) = &
'Vbi qND xn x 2
'(
2K s 0
xp x 0
0 x xn
The electric potential is continuous at

x = 0, yielding:
qNA 2
qND 2
xp = Vbi
x
2K s 0
2K s 0 n
Pierret, Fig. 5.9
Together with the charge neutrality

relationship NA xp = ND xn, this
equation can be used to determine xn
and xp
14
Step Junction Depletion Layer Width

We obtain for xn and xp:
2K s 0
NA
xn =
Vbi
q ND NA + ND
xp =
2K s 0
ND
Vbi
q NA NA + ND
Thus, the depletion layer width W is
2K s 0 NA + ND
W = xn + xp =
Vbi
q
NAND
15
Step Junction
with VA 0
Pierret, Fig. 5.12
Assumption: Externally
applied voltage VA is
completely dropped
across the depletion
region
I.e., negligible voltage
drop at contacts and
across the quasi-neutral
regions
p
VA > 0: Reduces potential

step across junction
n
+
VA
VA < 0: Increases potential

step across junction
16
Step Junction
with VA 0
Forward Bias VA > 0:
Potential drop across
the depletion region
decreases; majority
carrier diffusion
dominates, resulting in a
large forward current
flow
Reverse Bias VA < 0:
Potential drop across
increases; minority
carrier drift dominates,
resulting in a small
reverse current flow
Pierret, Fig. 5.12
17
Step Junction with VA 0
Bias VA can be implemented in equations by

replacing Vbi with Vbi VA:
2K s 0 NA + ND
W=
Vbi VA
q
NAND
Pierret, Fig. 5.11
Forward Bias VA > 0

Reduced depletion layer width
Reduced space charge
Reduced electric field
Reduced potential drop across junction
Reverse Bias VA < 0
Increased depletion layer width
Increased space charge
Increased electric field
Increased potential drop across junction
18
3.2 PN Junction: I-V Characteristic

3.2.1 Qualitative Derivation
3.2.2 Quantitative Derivation
Minority Carrier Distribution
Minority Carrier Currents
I-V Characteristic
Saturation Current
3.2.3 Junction Breakdown
Avalanche Breakdown
Zener Breakdown
Pierret, Chapter 6.1, page 235-259
19
3.2.1 Qualitative Derivation

(a) Equilibrium
Under equilibrium, the
net current flow is zero,
i.e. the electron/hole
drift and diffusion
currents balance each
other
J = Jdrift + Jdiff = 0
Pierret, Fig. 6.1

Electron Currents:
Majority carrier diffusion current from n- to p-side
Minority carrier drift current from p- to n-side
Hole Currents:
Majority carrier diffusion current from p- to n-side
Minority carrier drift current from n- to p-side
20
Qualitative Derivation
(b) Forward Bias
Forward bias (VA > 0)
reduces the potential
drop across the
depletion region
As a result, the majority
carrier (electron and
hole) diffusion over the
potential hill increases
exponentially, resulting
in a net current flow
across the junction
The minority carrier
drift currents remain
constant
Majority carrier
density decreases
exponentially with
increasing energy
n(E)
p(E)
Pierret, Fig. 6.1

21
Qualitative Derivation
(c) Reverse Bias
Reverse bias (VA < 0)
increases the potential drop
across the depletion region
As a result, the majority
carrier (electron and hole)
diffusion current over the
potential hill is suppressed
for VA > few kT
The minority carrier drift
currents remain constant,
thus resulting in a
saturation current flowing in
reverse direction
Pierret, Fig. 6.1
22
3.2.2 Quantitative Derivation

Solution Strategy
1. Calculate the minority carrier concentration in the
quasineutral regions on the p- and n-side of the
junction by solving the continuity equation
2. Calculate the minority carrier current densities at
the edges of the depletion region x = xn
and x = -xp
3. Calculate the total current density flowing through
the diode by adding the hole and electron minority
carrier density, assuming no generation/
recombination effects in the depletion region
23
1-D Continuity and Current Equations

1-D Current Density Equation
dp
dx
dn
Jn = q n n + q Dn
dx
Jp = q p p q Dp
1-D Continuity Equation

np (x,t)
t
2np
np np0
= +np n
+ n
+ Dn 2 + GL
x
x
n
x
np
pn (x,t)
pn
2pn
pn pn0
= pn p
p
+ Dp 2 + GL
t
x
x
p
x
Which terms do we have to consider?

24
PN Junction: IV Characteristic
Assumptions for Quantitative Derivation
Steady state conditions

Non-degenerately doped step junction
One-dimensional pn-junction
Low-level injection in quasineutral regions
No generation/recombination processes other than
thermal recombination/generation in the diode
=0
Quasineutral
p-region
0
xp
=0
xn
Depletion
region
Quasineutral
n-region
x
25
Continuity Equation
Continuity equation for quasineutral regions
Steady state (dpn/dt = dnp/dt = 0)
No E-field, i.e. all drift terms are zero
No R-G other than thermal R-G (e.g., GL = 0)
0 = Dn
0 = Dp
d2 np
2
dx#
d2 pn
2
dx
np
n
= Dn
d2np
2
dx#
d2pn
np np0
n
pn
p pn0
= Dp
n
p
p
dx2
for x# 0
for x 0
with np = np0 + np and pn = pn0 + pn
26
Minority Carrier Concentration
General solution
np (x#) = A e x# / Ln + Bex# / Ln
pn (x) = Ce
x / Lp
+ De
x / Lp
for x# 0
for x 0
with Ln = Dn n and Lp = Dp p
Boundary conditions at ohmic contacts:

Assumption: wide quasineutral regions, i.e.
(
)
pn ( x ) = 0
np x# = 0 B = 0
D=0
27
Boundary conditions at edge of depletion region:
kT NAND kT pp0nn0
Vbi =
ln
=
ln
2
q
q
ni
ni2
pp0 np0 =ni2
kT nn0
ln
q np0
nn0 = np0 eqVbi / kT
Assumption: Equation is true also for applied VA!
Vbi Vbi VA
q Vbi VA / kT
nn = np e
np = nn e
q Vbi VA / kT
weak injection
nn nn0
nn0 eqVbi / kT eqVA / kT

!#
#"##
$
=np0
28
Boundary conditions at edge of depletion region (cont.):
np = np0 eqVA / kT
pn = pn0 eqVA / kT
and similar
qV /kT
np = np0 #$e A 1%& at x p , i.e. x' = 0
or
qVA /kT
#
pn = pn0 $e
1%& at + x n , i.e. x = 0
A = np0 eqVA / kT 1
and C = pn0 eqVA / kT 1
29
Minority Carrier
Concentration
Forward Bias
Reverse Bias
30
Thus, the minority

carrier distributions
in the quasi-neutral
regions become:
np (x#) = np0
eqVA / kT 1 e x# / Ln
pn (x) = pn0
eqVA / kT 1 e
x / Lp
Minority Carrier Concentrations
Forward Bias
Reverse Bias
Pierret, Fig. 6.8
31
Diffusion Current Densities
The minority carrier diffusion currents in the
quasineutral regions can be derived from the minority
carrier distributions by
Jn (x") = +qDn
dnp
dx"
qDnnp0
Ln
qDppn0
dpn
Jp (x) = qDp
=+
dx
Lp
[
[e
]
1] e
eqVA / kT 1 e x" / Ln
qVA / kT
x / Lp
Thus, at the edges of the depletion region
Jn x = xp = Jn (x# = 0) = +
Jp x = +xn = +Jp (x = 0) = +
qDnnp0
Ln
qDppn0
Lp
[
[e
]
1]
eqVA / kT 1
qVA / kT
32
Diffusion Current Densities
Pierret, Fig. 6.7
33
Total Current
Assuming that there is no R-G in the depletion region,
the total current density flowing through the pn
junction is the sum of the minority carrier currents at
the edges of the depletion region
J = Jn x = xp + Jp x = +xn
#qDnnp0 qDppn0 & qV / kT

=%
+
1
( e A
Ln
Lp '
$!#
##"###$
Js
]
34
Pierret, Fig. 6.6
Reverse Bias VA < 0

For |VA| > few kT/q, a small
saturation current Js is
flowing through the pn
junction
Forward Bias VA > 0

For |VA| > few kT/q, the
current flowing through the
junction increases
exponentially
35
PN Junction: Saturation Current

The saturation current density is given by
Js =
qDnnp0
Ln
qDppn0
Lp
qDnni2
LnNA
qDpni2
LpND
The saturation current depends on the intrinsic

carrier concentration ni and, thus, is strongly
temperature and material dependent
The saturation current is dominated by the
contribution from the lower doped side of the junction
in case of asymmetrical junctions
36
Real IV Characteristic
Junction Breakdown
Junction Breakdown
Pierret, Fig. 6.9

37
3.2.3 Junction Breakdown
Junction or Reverse-Bias Breakdown: current flowing in a pnjunction under reverse bias suddenly increases drastically if reverse
bias is increased over the so-called breakdown voltage VBR;
breakdown process is reversible if the junction is not overheated
(current must be limited)
The breakdown voltage depends on
Junction doping (the non-degenerate doping in case of a n+-p or
p+-n junction)
Temperature
Radius of curvature in case of junctions with curved non-planar
edges because of larger electric fields in the curved edges; this
effect becomes important for shallow junctions
The basic breakdown processes are
Avalanching
Zener process (dominating if VBR < 4.5 Eg/q)
38
Breakdown Voltage in Planar p+-n/n+-p Junctions
VBR
1
NB0.75
Avalanche
dominating
Zener
dominating
Doping conc. of lightly doped side!

Pierret, Fig. 6.11

39
Avalanche Breakdown
Avalanching Process
Minority carriers in junction
depletion region gain enough
kinetic energy to generate
electron-hole pairs during
an impact; this is called
impact ionization
This way, the
number of carriers
can increase
tremendously,
similar to a snow
avalanche, ultimately causing
a junction breakdown
Pierret, Fig. 6.12
40
Zener
Breakdown
Breakdown current due
to quantum mechanical
carrier tunneling in
highly-doped, degenerate
pn-junctions
Physical background:
there is a quantum
mechanical probability
that a particle can tunnel
through a potential
barrier even if its energy
is smaller than the barrier
height
Pierret, Fig. 6.13 & 6.14
41
3.3 PN Junction: Dynamic Behavior

Small-Signal Analysis
Equivalent Circuit
Forward-Bias / Reverse-Bias Characteristics
Depletion Layer Capacitance
Diffusion Admittance
Pierret, Chapter 7, page 301-324
42
Small-Signal Analysis
Equivalent Circuit
AC current i flowing through
the diode biased by small
AC voltage va superimposed
on DC bias VA
Small-signal admittance Y
consists of capacitive C and
conductive G component:
Y = i / va = G + jC
Equivalent circuit of diode

consists of junction
admittance Y and series
resistance Rs of quasineutral
regions
Pierret, Fig. 7.1 & 7.2
43
PN Junction: Small-Signal Behavior

(a) Reverse Bias
Small signal behavior is dominated by junction or depletionlayer capacitance Cj
The junction capacitance Cj arises from majority carrier
(charge) oscillations at the edges of the depletion region
Conductance is very small (i.e., very high resistance)
(b) Forward Bias

With increasing forward bias, the diffusion admittance
Yd = Gd + i Cd dominates the small signal behavior
The diffusion capacitance Cd arises from minority-carrier
(charge) oscillations in the quasineutral regions adjacent to
44
Junction
Capacitance
The so-called junction or depletionlayer capacitance originates from
charge oscillations at the edge of
the depletion region caused by the
applied ac voltage va
The capacitance resulting from the
small oscillations of the depletion
region around its steady-state width
W is equivalent to that of a parallel
plate capacitor with width W
Cj =
dQ(VA ,va ) K s 0 A
=
dva
W(VA )
Pierret, Fig. 7.4
45
Junction Capacitance Cj
Junction capacitance Cj depends on the applied dc bias VA,
because the depletion layer width W is a function of VA; in case
of a step junction, the depletion layer width becomes
W=
Cj =
2K s 0 NA + ND
Vbi VA
q
NAND
K s 0 A
=
W(VA )
K s 0 A
2K s 0 NA + ND
Vbi VA
q
NAND
Characteristics of Cj
Cj originates from majority carrier oscillations
C decreases with increasing reverse bias -V
j
A
Varactor diodes use Cj as voltage-controlled capacitor
Majority carrier response time in Si is < 10-10 s, i.e. Cj is
frequency-independent up to very high frequencies
46
Junction Capacitance Cj
The junction capacitance Cj can be expressed in terms of its value
Cj0 for VA = 0:
Cj =
K s 0 A
2K s 0 NA + ND
% VA (
V
1
q
NAND bi '& Vbi *)
!###"###$
C j0
% VA (
'1
*
& Vbi )
=C j (Vbi )C j0
The measurement of the junction capacitance is used as diagnosis

tool (C-V measurement) to get an inside view of the junction;
assuming an asymmetric step junction, e.g. ND NA = NB, one
obtains:
1
2
=
Vbi VA
2
2
C j qK s 0 A NB
The linear 1/Cj2 vs. VA relationship has a slope proportional to NB-1

and an intersection with the V-axis at VA = Vbi
47
Forward-Bias Diffusion Admittance

The diffusion admittance
YD = GD + jCD
is caused by minority carrier

oscillations in the quasi-neutral
regions adjacent to the
depletion region
Small signal equivalent circuit
of forward-biased pn-junction
consists of
junction capacitance Cj,
diffusion capacitance CD, and
diffusion conductance GD
Minority carrier lifetime limits the
frequency up to which the
minority carriers can follow va
Pierret, Fig. 7.8

48
Diffusion Admittance Relationship

AC behavior can be extracted similar to dc behavior from
continuity equations (example: p+-n junction)
Continuity equation for n-side minority carriers
pn (x,t)
2 pn (x,t) pn (x,t)
= Dp
2
t
p
x
with the minority carrier distribution
pn (x,t) = pn (x) + pn (x,) e jt
Using separation of variables, two DEs for the dc and ac terms

result:
2 pn pn
0 = Dp
same as dc
2
x
p
similar to dc
2pn
pn
0 = Dp
p = p /(1+ jp )
but
x2 p / 1+ jp
49
Boundary Conditions:
v(t) = VA + va e jt
"#$
= va
pn (,t) = 0
ni2 % q( VA + v a ) / kT (
pn (xn ,t) =
e
1
'
*)
ND &
ni2 qVA / kT
ni2 % qVA / kT qv a / kT
(
=
e
1 +
e
e
1
*)
ND
ND '&
"$$#$$% "$$$$#$$$$%
=pn (xn ,) e jt
=pn (xn )
for qva kT, we can simplify using ex 1 + x for small x
pn (xn ,) e jt
qv
=
eqVA / kT a
ND
kT
ni2
ni2 qVA / kT qva
pn (xn ,) =
e
ND
kT
50

Using the new boundary conditions and the modified minority
carrier lifetime, the ac diffusion current becomes (in analogy to
the dc diffusion current)
DC
Idiff = qA
Dpni2
LpND
eqVA / kT
Dp ni2 qV / kT
1 = qA
e A
1
p ND
!#"#$
=Is
AC
idiff = qA
Dp
p
ni2
1+ jp
ND
%qva qVA / kT (
' kT e
*
&
)
q qVA / kT
= IS e
1+ jp va = YD va
!kT
#
#"##
$
=G0 =
dI
dVA
51

The diffusion admittance YD for the p+n diode
idiff
YD = GD + jCD =
= G0 1+ jp
va
consists of a conductive part GD and a capacitive part CD
GD =
G0 $
1+ 2 p2 + 1'
)(
2 &%
1/ 2
G0 $
CD =
1+ 2 p2 1'
)(
2 &%
p <<1
G0
1/ 2
p <<1
G0
p
2
CD0
For p = 1 s, we get p = 1 at f = /2 = 160 kHz
52
Frequency Dependence of GD and CD
Pierret, Fig. 7.10

53
3.4 PN Junction: Diode Models

3.4.1
3.4.2
3.4.3
3.4.4
Load-Line Analysis
Ideal Diode Model
Constant Voltage Drop Model
Breakdown Model
Jaeger & Blalock, Chapter 3.10-3.12, page 96-112
54
Diode Circuit Analysis

Establish simple diode
models to facilitate (dc)
analysis of circuits containing
diodes
Example: Series circuit of
voltage source, resistor and
diode
Note: V and R may represent
Thvenin equivalent of more
complicated two-terminal
network
Goal: Find quiescent
operating point or Q-point of
diode
Jaeger, Blalock, Fig. 3.22
V = IDR + VD
What are the values
for VD and ID?
55
3.4.1 Load-Line Analysis
Load-Line Analysis =
Graphical analysis if diode
I-V characteristic is only
available in graphical form
Analysis approach:
Write load-line equation
V=10 V
R = 104
V = IDR + VD
10 = ID 10 4 + VD
ID = 104 VD +103
Plot load-line and diode I-V

characteristic
Q-point is defined by
intersection of load line and
diode I-V characteristic
Q-point = (0.95mA, 0.55V)

56
Load-Line Analysis
The Mathematical Approach
Goal: Find intersection of load line and diode I-V
characteristic using mathematical software package
1
V
ID = VD +
R
R
qVD /kT
"
ID = IS #e
1$%
Given are R = 104 , V = 10 V, IS = 10-13 A and
kT/q = 0.026 V, unknown are VD and ID
The Mathematica function FindRoot yields
VD = 0.597 V and ID = 0.940 mA
57
3.4.2 Ideal-Diode Model

Approximation of non-linear diode
characteristic by piece-wise linear
model
Ideal Diode Model =
Approximation with two straightline segments
If diode is forward-biased, voltage
across diode is zero
vD = 0 for iD > 0, i.e. short circuit
If diode is reverse-biased,
current through diode is zero
iD = 0 for vD < 0, i.e. open circuit
Diode is assumed to be either
on or off
58
Ideal Diode Model

Analysis procedure:
Select model for diode
Identify diode anode (positive
terminal) and cathode (negative
terminal) and label VD and ID
Make (educated) guess on
diode region of operation based
on circuit configuration
Analyze circuit with appropriate
diode model
Check results for consistency
with assumptions
What about our simple

example?
59
Example: Analysis with Ideal-Diode Model
Jaeger, Blalock, Fig. 3.27&28
Voltage source tries to forward-bias diode, so we replace it by

short-circuit (ON state)
V
ID = = 1mA
ID is now easily obtained:
R
VD = 0 V
The current (positive) is consistent with the assumption that the

diode is ON
60
3.4.3 Constant Voltage Drop Model

Piecewise linear model
accounting for constant
voltage drop across forwardbiased diode (associated
with turn-on voltage of
diode)
Turn-on voltage
= voltage required to obtain
significant conduction;
typically 0.5-0.7 V
Constant voltage drop (CVD)
model: simulation of diode
by series connection of
ideal diode and voltage
source
61
Constant Voltage Drop Model
If diode is forward-biased, voltage across diode is turn-on

voltage vD = Von for iD > 0, i.e. constant voltage source
If diode is reverse-biased, current through diode is zero
iD = 0 for vD < Von, i.e. open circuit
We choose Von = 0.6 V .
62
Example: Analysis with CVD Model
Voltage source tries to

forward-bias diode, so we
replace it by voltage source
(ON state)
ID is again easily obtained:
V Von
= 0.94 mA
R
VD = 0.6 V
ID =
63
Multi-Diode Circuits
Ideal diode and CVD model

enable hand-analysis of more
complex diode circuits having
two or more diodes
Alternative: SPICE analysis
(see Chapter 3.6)
Example problem: Find Q-points
of both diodes in two-diode
circuit!
Approach: Try all (four) possible
diode states (one after the
other) and check whether
results are consistent with
assumptions
Result (using ideal diode model):
D1 off: (0 mA; 1.67 V)
D2 on: (1.67 mA; 0 V)
64
3.5 Diode Applications & Circuits

3.5.1 Temperature Sensors
Diode Temperature Coefficient
PTAT Sensor
3.5.2 Rectifier Circuits
Half-Wave Rectifier Circuits
Full-Wave Rectifier Circuits
Full-Wave Bridge Rectifier Circuits
3.5.3 Voltage Regulators
3.5.4 Additional Applications
Jaeger & Blalock, Chapter 3.13-3.16, page 113-128
65
3.5.1 Temperature Sensors

Diode Temperature Coefficient
Forward-biased diode (operated with constant bias current) is
frequently used for temperature sensing:
qV /kT
ID = IS "#e D 1$%
kT "ID $ kT " ID $
VD =
ln ' +1(
ln '
(
q # IS % q #IS (T) %
Challenge: IS is proportional to ni2 and thus (strongly) depends

on temperature; as a result, the VD vs. T relationship is
nonlinear
dVD k !ID $ kT 1 dIS
= ln # &
dT q " IS % q IS dT
Work-around: PTAT circuit using a differential setup with 2
identical diodes
66
PTAT Electronic Thermometer
PTAT = proportional to absolute

temperature
Concept
Two identical diodes biased by current
sources I1 and I2
Resulting PTAT voltage, i.e., difference
in voltage drop across the two diodes is
proportional to the absolute temperature
VPTAT = VD1 VD2
" I %+ kT " I %
kT ( " ID1 %
*ln $ ' ln $ D2 '- =
=
ln $ D1 '
q *) # IS &
# IS &-, q # ID2 &
dVPTAT k " ID1 % VPTAT

= ln $ ' =
dT
q # ID2 &
T
PTAT voltage circuit is heart of most of

todays digital thermometers
Jaeger, Blalock, page 88

67
3.5.2 Rectifier Circuits

Rectifier circuit converts an ac voltage to a pulsating dc
voltage; in combination with a filter, a nearly constant dc output
voltage can be generated
Virtually every electronic device plugged into the wall utilizes a
rectifier circuit to convert the 120-240V, 50-60Hz ac power line
source to a proper dc voltage
DC power supplies are a commodity and fairly inexpensive
Power Cube
Cell Phone Charger
Jaeger, Blalock, page 128

68
Half-Wave Rectifier with Resistive Load
Sinusoidal voltage source vS = VP sint is

connected to a series combination of diode
D1 and resistor R
Using the ideal diode model, we find that the
diode is ON for vS > 0 and OFF for vS < 0,
resulting in a pulsating output voltage v0
Jaeger, Blalock, Fig. 3.42 & 3.44

69
Half-Wave Rectifier
with Resistive Load
If the input voltage amplitude

(e.g. VP 10 V) is not large
compared to the voltage drop
(0.5-1.0 V) across the forwardbiased diode, the CVD model
should be used for circuit analysis
v S 0 v 0 = VP sint Von
vS < 0
v0 = 0
In many applications, a
transformer is used to stepdown the power line voltage to a
desired level
To remove time-varying
components from output
waveform, a filter capacitor is
usually added
70
Rectifier Filter Capacitor

Peak Detector Circuit
Assumption: initially uncharged
capacitor, i.e. v0(0)=0
As input voltage rises, diode turns on
and capacitor is charged to
v0 = Vdc = VP Von
At peak of input voltage waveform,
the current through the diode tries to
reverse direction (because
iD = C d(vS Von)/dt), thus reverse
biasing the diode and disconnecting
the capacitor from the power supply
With no discharge possibility,
v0 = Vdc = VP Von stays constant;
in a rectifier however, a resistive load
R is connected in parallel to C,
providing a discharge path
71
Half-Wave Rectifier with RC Load
v0 > vS Von: diode off; capacitor

discharged through resistor R
v0 < vS Von: diode on; capacitor
charged by voltage source
During discharge process, the
voltage across the capacitor
decreases exponentially with a
time constant RC; slow voltage
decay requires large RC and thus
large capacitances C
Characteristics of rectifier circuit
Output voltage Vdc
Ripple voltage Vr
Conduction interval T
Peak diode current IP
Surge current ISC
Peak-Inverse-Voltage Rating
Diode power dissipation
72
Ripple Voltage Vr
The ripple voltage Vr should be as small as possible
Voltage across capacitor during discharge process
v 0 (t!) = VP Von e t!/RC
for
t! = t
T
0
4
The ripple voltage is thus given by
) (
) $&%e e (
Vr = v 0 t! = 0 v 0 t! = T T
= VP Von
TTRC
(V
(V
Von
'
)(
* $ T T ',1 &1+
)/
RC
(.
+ %
Von T
R C
= Idc
TT
TT /RC
T
Vr = Idc
C
73
Conduction Interval T
At the beginning of the conduction interval t = TT, we have
v 0 (t! = T T) = v s (t! = T T) Von
(V
Von e(TT)/RC = VP cos $% T T &' Von
Assuming TRC and TT, both cosine and exponential function

can be expanded in a Taylor series (cos(T-T) = cos(T))
VP Von
2&
#
# T T &
T
( V
%1
( = VP %1
%
RC ('
2 ( on
%$
$
'
Solving for T yields
1 2T VP Von 1 2Vr
T
=
RC VP
VP
Conduction angle C
2Vr
C = T
VP
74
Peak Diode Current IP
The charge lost during the

discharge period must be
supplied to the capacitor during
the short charging cycle,
resulting in large diode currents
Assuming TT, the charge
lost during one period T is
Q = Idc T; this charge must be
supplied to the capacitor during
the charging interval T
Assuming a triangular shaped
current pulse through the diode
(see SPICE simulation), the
resulting peak diode current IP
becomes
T
2T
Q = Idc T = IP
IP = Idc
2
T
Note: the peak current

can be 10s of ampere
75
Surge Current ISC
Surge current ISC = Peak current

during initial charging process of
capacitor
During the initial charging, the
diode current is determined by
the charging current of the
(uncharged) capacitor
#d
&
id (t) = iC (t) C % VP sint(
$ dt
'
= CVP cos t
= ISC
ISC = C VP
In actual devices, ISC is reduced

due to series resistances of
diode and transformer (you can
investigate this with SPICE)
76
Peak-Inverse-Voltage (PIV) Rating

and Diode Power Dissipation
Peak-Inverse-Voltage (PIV) is maximum reverse bias voltage
of rectifier diode during operation; thus, minimal breakdown
voltage must be PIV (typically PIV is given with safety margin of
25-50%)
PIV Vdc v min
= 2VP Von 2VP
S
Power dissipation in rectifier diode
T
V
1
PD1 = v D (t) iD (t) dt = on
T0
T
IP T
i
(t)
dt
=
V
= VonIdc
D
on
2
T
TT
current only flows during charging cycle
Additional power dissipation due to diode series resistance RS

T
R
1
PD2 = RS iD2 (t) dt = S
T0
T
IP2 RS T 4 T
2
i
(t)
dt
=
=
R
I
3 T
3 T S dc
TT
2
D
Note: PD2 can be substantially larger than PD1

77
Half-Wave Rectifier Example

Assume:
VP = 10 Vrms = 14.1 Vp (60 Hz)
R = 15
C = 25,000 F !!
Von = 1 V (because of large currents)
RS = 0.2
Vdc = VP Von = 13.1V

DC output voltage Vdc:
Idc = Vdc / R = 0.87 A
Output current Idc:
Vr = (Idc T) / C = 0.58 V
Ripple voltage Vr:
1
Conduction interval T and angle C: T 2Vr / VP = 0.761ms
C = T = 0.287 rad = 16.4
IP = (2 Idc T) / T = 38 A
Diode peak current IP:
ISC = C VP = 133 A
Diode surge current ISC:
PIV:
PIV 2VP = 28.2 V
4 T
2
Diode power dissipation:
PD1 = VonIdc = 0.87 W PD2 =
RS Idc
= 4.42 W
3 T
78
Half-Wave Rectifier with Negative

Output Voltage
By grounding either the top of the capacitor (compared to the

bottom in Jaeger/Blalock, Fig. 3.48) or reversing the diode, the
rectifier circuit produces a negative output voltage, i.e. the
diode conducts on the negative half-cycle of the transformer
Vdc = VP Von
79
Full-Wave Rectifier Circuits

Operation Principle
Center-tapped transformer generates two voltages with equal
amplitude but 180 phase shift
Resulting are two half-wave rectifier circuits operating on
alternate half-cycles of input waveform
D1 charges C during one half cycle, D2 charges C during the
other half cycle
Advantages
Capacitor discharge
time cut in half
Thus, requires only
one-half the filter
capacitance for a
given ripple voltage
80
Full-Wave Rectifier Circuit

Equivalent circuit for vS > 0:
Equivalent circuit for vS < 0:
Jaeger, Blalock, Figs. 3.59-3.61
RC load receives 2 current

pulses per cycle!
81
Full-Wave Rectifier Circuit

DC output Voltage Vdc:
Vdc = VP Von
Ripple Voltage Vr:
Vr =
Conduction Interval T:
1 2 T VP Von 1 2Vr
T
=
2RC VP
VP
Conduction Angle C:
C = T
Peak Diode Current IP:
IP = Idc
PIV:
PIV = 2 VP
(V
Von
R
T
T
= Idc
2C
2C
2Vr
VP
2T
2T
82
Full-Wave Bridge Rectification

Bridge arrangement of 4 diodes eliminates the need for a center-tapped

transformer
vS > 0 half cycle: D2 and D4 ON; D1 and D3 OFF
vS < 0 half cycle: D1 and D3 ON; D2 and D4 OFF
Output dc voltage is now reduced by 2 diode voltage drops
Vdc = VP 2 Von
PIV rating for each diode is reduced: PIV VP

83
Full-Wave Bridge Rectification

Half Cycle vS > 0:
Half Cycle vS < 0:
Jaeger, Blalock, Figs. 3.64 and 3.65
84
Rectifier Comparison
Rectifier
Parameter
Filter Capacitor
PIV Rating
Peak Diode
Cur. (const. Vr)
Comments
Half-Wave
Rectifier
C=
VP Von T
Vr
R
Full-Wave
Rectifier
C=
VP Von T
Vr
2R
Full-Wave
Bridge
Rectifier
C=
VP Von T
Vr
2R
2 VP
2 VP
VP
Highest
IP
Reduced
IP/2
Reduced
IP/2
Least complexity
Smaller capacitor
Requires centertapped transformer
2 diodes
Smaller capacitor
4 diodes
85
3.5.4 Additional Diode Applications

(not discussed in ECE3040)
DC-to-DC Converters
Wave-Shaping Circuits
Clamping or DC Restoring Circuit
Clipping or Limiting Circuit
Piecewise Linear Transfer Function Circuit
Optoelectronic Devices
Photo Diodes
Solar Cells
Light-Emitting Diodes
86
3.6 Diode SPICE Model

3.6.1 Circuit Simulation using SPICE
OrCAD Capture and PSPICE
Introduction to PSPICE Simulation
3.6.2 SPICE Diode Model
3.6.3 Sample Problem
Jaeger & Blalock, Chapter 3.9, page 94-96
M.E. Herniter, Schematic Capture with Cadence
PSPICE, Prentice Hall, 2nd edition, 2003
87
3.6.1 Circuit Simulation using SPICE

SPICE is a general purpose circuit simulation program
originally developed at EECS Department of UC Berkeley
Capabilities:
Analysis Types: DC, AC, transient (and more)
Circuit elements: resistors, capacitors, inductors, mutual
inductors, independent and dependent voltage and current
sources, lossless and lossy transmission lines, switches,
uniform distributed RC lines, semiconductor devices
including diodes, BJTs, JFETs, MESFETs, and MOSFETs
Implementations:
PSPICE: http://www.orcad.com/; a limited student version of
PSPICE (version 9.1) is distributed with Jaeger & Blalock; a
demo CD with version 15.7 can be downloaded from OrCAD
PSPICE (Cadence) and HSPICE (Synopsys) are
implemented in major integrated circuit design tools
88
Limits of PSPICE Student Version

Circuit simulation limited to
64 nodes
10 transistors
2 op-amps or 65 digital primitive devices
10 transmission lines
Device characterization using Model Editor limited to diodes
Stimulus generation limited to sine waves (analog) and clocks
(digital)
Sample library of approx. 39 analog and 134 digital parts
(compared to 11,300 analog and 1,600 digital device models in
the standard package)
Display of simulation data only (no saving, except Print Screen)
89
Start Capture Student
90
Start New Project
91
Place Parts from Database
92
PSPICE Model Parameters
93
Place Ground
Note: One GND must be named 0!!!
94
Wire Circuit, Define Parameters

and Create Simulation Profile
circuit must have a GND named 0
95
Simulation Settings Time Domain
RUN
96
Run Simulation and

Display Results in OrCAD PSPICE
97
Plot Traces in OrCAD PSpice
98
3.6.2 SPICE Diode Model
Nonlinear behavior of diode is

modeled by voltage
controlled current source iD
Model equation for iD includes
ideal exponential diode
behavior plus term that
accounts for carrier
generation in the depletion
region of the diode
Junction Cj and diffusion CD
capacitances are connected
in parallel
Series resistance Rs
accounting for finite
resistance of quasi-neutral
regions
99
SPICE Diode Model

(
! v $ +
iD = IS *exp # D & 1*)
" NVT % -,
CD = TT
kT
VT =
q
Cj =
iD
NVT
CJO
M
# v &
%1 D (
$ VJ '
for v D 0
for v D 0
ECE3040
Symbol
SPICE
Default
Value
Saturation Current
IS
IS
10 fA
Series Resistance
Rs
RS
Ideality Factor
Transit Time
TT
0 sec
Zero-Bias Junction Cap. for unit area
Cj A
CJO
0F
Built-In Potential
Vbi
VJ
1V
Junction Grading Coefficient
0.5
Relative Junction Area
RAREA
Parameter
100
Sample Problem
Half-Wave Rectifier without Transformer
Voltage Source VSIN
Amplitude = 15 V
Frequency = 60 Hz
Offset = 0V
Ideal Diode
IS = 10 fA, N = 1
RS = 0, Cj = CD = 0
Filter Capacitance
C = 20 mF = 20,000 F
Load Resistance
R = 15
101
DC Output Voltage & Current

voutput
ioutput
vinput
DC Output Voltage: Vdc 14 V

DC Output Current: Idc 0.93 A
102
Diode Current
ISC
IP
Peak Diode Current: IP 33 A

Diode Surge Current: ISC 115 A
103
DC Output Voltage for C = 1 mF

voutput
vinput
Modification: filter capacitance decreased from C = 20 mF to C = 1 mF

Increased ripple voltage due to reduced RC time constant
104
Diode with RS = 0.1

voutput
ISC
vinput
IP
Modification: introduce diode series resistance RS = 0.1

Reduced IP and ISC; C only charged after several cycles
105
Diode with RS = 0.1

ISC
IP
Modification: introduce diode series resistance RS = 0.1

Reduced IP and ISC; C only charged after several cycles
106

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Chapter 3 The PN Junction

ECE 3040: Chapter 3 PN Junction

3.1 PN Junction: Electrostatics

ECE 3040: Chapter 3 PN Junction

3.1.1 PN Junction Basics

Pierret, Fig. 5.1

Doping Profile Approximations

Linearly Graded Junction

Pierret, Fig. 5.2

PN Junction Built-in Potential

)pside + (EF Ei)nside &('

Pierret, Fig. 5.4

With the results from Chapter 2.5

p = NA = ni e(Ei EF )/ kT p side with NA >> ni

PN Junction Depletion Approximation

To obtain quantitative solutions for

This requires the knowledge of the

Pierret, Fig. 5.6

From electric field to electrostatic

Pierret, Fig. 5.9

ECE 3040: Chapter 3 PN Junction

3.1.2 Step Junction: VA = 0

The electric field is obtained by

with the boundary conditions

Pierret, Fig. 5.9

ECE 3040: Chapter 3 PN Junction

Step Junction with VA = 0

The electric potential is obtained by

Pierret, Fig. 5.9

with the boundary conditions

ECE 3040: Chapter 3 PN Junction

Step Junction: Charge Considerations

Step Junction with VA = 0

The electric potential is continuous at

Pierret, Fig. 5.9

Together with the charge neutrality

Step Junction Depletion Layer Width

Thus, the depletion layer width W is

Pierret, Fig. 5.12

VA > 0: Reduces potential

VA < 0: Increases potential

ECE 3040: Chapter 3 PN Junction

Pierret, Fig. 5.12

Step Junction with VA 0

Bias VA can be implemented in equations by

Pierret, Fig. 5.11

Forward Bias VA > 0

3.2 PN Junction: I-V Characteristic

ECE 3040: Chapter 3 PN Junction

3.2.1 Qualitative Derivation

Pierret, Fig. 6.1

Pierret, Fig. 6.1

3.2.2 Quantitative Derivation

ECE 3040: Chapter 3 PN Junction

1-D Continuity and Current Equations

1-D Continuity Equation

Which terms do we have to consider?

Steady state conditions

with np = np0 + np and pn = pn0 + pn

ECE 3040: Chapter 3 PN Junction

Boundary conditions at ohmic contacts:

ECE 3040: Chapter 3 PN Junction

pp0 np0 =ni2