TPSVLSI Cursul 3:

CMOS Teorie si Analiza

Marius Enachescu

Outline
Ideal CMOS Transistor Theory
Non-Ideal CMOS Transistor Theory
DC&Transient Responce

Lecture 3

Ideal CMOS Transistor Theory

Introduction
MOS Capacitor
nMOS I-V Characteristics
pMOS I-V Characteristics
Gate and Diffusion Capacitance

Introducere
Am introdus transistorul ca un switch ideal -> acum detaliam
Simboluri uzuale ale tranzistorului
ON transistor (dispozitiv cu purtatori majoritari) permite
trecerea unui current limitat:
Depinzand de tensiunile applicate pe terminale S,D,G,B.
Relatiile current-tensiune (I-V characteristics)
S, D, G au capacitati:
I = C (V/t) -> t = (C/I) V
C & I determina viteza

MOS Capacitor
Consideram G si B
Moduri de operare:
Accumulation
Depletion
Inversion

polysilicon gate
silicon dioxide insulator

Vg < 0
+
-

p-type body

(a)

Terminal Voltages
Vg
Modul de operare depinde de Vg, Vd, Vs
+
+
Vgs = Vg Vs
Vgs
Vgd
Vgd = Vg Vd
Vs
Vd
Vds = Vd Vs = Vgs - Vgd
+
Vds
S si D terminale simetrice
Prin conventie, S este se afla la o tensiune mai redusa
Prin urmare: Vds 0
nMOS B este pus la masa. Pentru inceput Vs=0.
Trei regimuri de operare:
Cutoff
Linear
Saturation
6

nMOS Cutoff
No channel
Ids 0
Vgs = 0

+
-

+
-

Vgd

n+

n+
p-type body
b

nMOS Linear
Se formeaza canalul
Curentul curge de la S
la D
e- de la S pana la D
Ids creste cu cresterea
Vds
Exact ca un resistor
ideal

Vgs > Vt

+
-

+
-

Vgd = Vgs

n+

Vds = 0

n+
p-type body
b

Vgs > Vt

+
-

+
d

n+

n+

Vgs > Vgd > Vt

Ids
0 < Vds < Vgs-Vt

p-type body
b

nMOS Saturation

Channel pinches off

Ids independent of Vds
We say current saturates
Similar to current source
Vgs > Vt

+
-

+
-

Vgd < Vt

d Ids

n+

n+

Vds > Vgs-Vt

p-type body
b

I-V Characteristics
In regiunea Liniara, Ids depinde de:
How much charge is in the channel?
How fast is the charge moving?

10

Channel Charge
MOS structure looks like parallel plate capacitor
while operating in inversions
Gate oxide channel
Qchannel = CV
Cox = ox / tox
C = Cg = oxWL/tox = CoxWL
V = Vgc Vt = (Vgs Vds/2) Vt
gate
Vg

polysilicon
gate
W
tox
n+

n+

SiO2 gate oxide

(good insulator, ox = 3.9)

+
+
Cg Vgd drain
source Vgs
Vs
Vd
channel
+
n+
n+
Vds
p-type body

p-type body

11

Carrier velocity
Sarcina e purtate de e Electronii sunt accelerate de campul electric format
intre S si D
E = Vds/L
Viteza purtatorilor v proportional cu campul-E
v = E
called mobility

Durata de timp pentru ca purtatorii sa traverseze canalul:

t=L/v

12

nMOS Linear I-V

Acum stim:
? Qchannel se afla in canal
De cat timp t are nevoie un purtator

Qchannel
I ds
t
W
Cox
L

V V Vds
gs
t
2

V
Vgs Vt ds Vds
2

V
ds

W
= Cox
L
13

nMOS Saturation I-V

If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs Vt
Now drain voltage no longer increases current

V
I ds Vgs Vt dsat
2

gs

Vt

V
dsat

14

nMOS I-V Summary

Shockley 1st order transistor models

Vds
I ds Vgs Vt
2

Vgs Vt

Vgs Vt
V V V
ds
ds
dsat

Vds Vdsat

cutoff
linear
saturation

15

Example
We will be using a 0.6 m process
From AMI Semiconductor
tox = 100
2.5
= 350 cm2/V*s
2
Vt = 0.7 V
1.5
Plot Ids vs. Vds
1
Vgs = 0, 1, 2, 3, 4, 5
0.5
Use W/L = 4/2

Vgs = 5

Ids (mA)

Vgs = 4

3.9 8.85 1014 W

W
Cox 350

8
L
100 10
L

120
A/V 2

Vgs = 3
Vgs = 2
Vgs = 1

Vds

16

pMOS I-V
All dopings and voltages are inverted for pMOS
Source is the more positive terminal
Mobility p is determined by holes
Typically 2-3x lower than that of electrons n
120 cm2/Vs in AMI 0.6 m process
Thus pMOS must be wider to
provide same current
In this class, assume
n / p = 2
0

Vgs = -1

Vgs = -2

Ids (mA)

-0.2

Vgs = -3

-0.4

Vgs = -4

-0.6

-0.8
-5

Vgs = -5

-4

-3

-2

-1

Vds

17

Capacitance
Any two conductors separated by an insulator have
capacitance
Gate to channel capacitor is very important
Creates channel charge necessary for operation
Source and drain have capacitance to body
Across reverse-biased diodes
Called diffusion capacitance because it is
associated with source/drain diffusion

18

Gate Capacitance
Approximate channel as connected to source
Cgs = oxWL/tox = CoxWL = CpermicronW
Cpermicron is typically about 2 fF/m

polysilicon
gate
W
tox
n+

n+

SiO2 gate oxide

(good insulator, ox = 3.90)

p-type body
19

Diffusion Capacitance
Csb, Cdb
Undesirable, called parasitic capacitance
Capacitance depends on area and perimeter
Use small diffusion nodes
Comparable to Cg
for contacted diff
Cg for uncontacted
Varies with process

20

Nonideal Transistor Behavior

Nonideal Transistor Behavior
High Field Effects
Mobility Degradation
Velocity Saturation
Channel Length Modulation
Threshold Voltage Effects
Body Effect
Drain-Induced Barrier Lowering
Short Channel Effect
Leakage
Subthreshold Leakage
Gate Leakage
Junction Leakage
Process and Environmental Variations
21

Ideal Transistor I-V

Shockley long-channel transistor models

Vds
I ds Vgs Vt
2

Vgs Vt

Vgs Vt
V V V
ds
ds
dsat

Vds Vdsat

cutoff
linear
saturation

22

Ideal vs. Simulated nMOS I-V Plot

65 nm IBM process, VDD = 1.0 V

23

ON and OFF Current

Ion = Ids @ Vgs = Vds = VDD
Saturation

Ioff = Ids @ Vgs = 0, Vds = VDD

Cutoff

24

Electric Fields Effects

Vertical electric field: Evert = Vgs / tox
Attracts carriers into channel
Long channel: Qchannel Evert
Lateral electric field: Elat = Vds / L
Accelerates carriers from drain to source
Long channel: v = Elat

25

Coffee Cart Analogy

Tired student runs from VLSI lab to coffee cart
Freshmen are pouring out of the physics lecture hall
Vds is how long you have been up
Your velocity = fatigue mobility
Vgs is a wind blowing you against the glass (SiO2) wall
At high Vgs, you are buffeted against the wall
Mobility degradation
At high Vds, you scatter off freshmen, fall down, get up
Velocity saturation
Dont confuse this with the saturation region
26

Mobility Degradation
High Evert effectively reduces mobility
Collisions with oxide interface

27

Velocity Saturation
Cand Elat creste, viteza purtatoriilor se satureaza:

Purtatorii imprastie atomii din structura de Si

Viteza se limiteaza la vsat
Electrons: 107 cm/s
Holes: 8 x 106 cm/s
Este nevoie de un alt model!!

28

Vel Sat I-V Effects

Ideal transistor ON current increases with VDD2
2
W Vgs Vt

Vgs Vt
I ds Cox
2
2
L
2

Velocity-saturated ON current increases with VDD

I ds CoxW Vgs Vt vmax

Real transistors are partially velocity saturated (2.4)

Approximate with -power law model
Ids VDD
1 < < 2 determined empirically ( 1.3 for 65 nm)
29

-Power Model
0

I ds I dsat ds
Vdsat

I dsat

Vgs Vt

cutoff

Vds Vdsat

linear

Vds Vdsat

saturation

30

Channel Length Modulation

Joctiunile p-n polarizate invers formeaza depletion
region
Regiuni intre n si p fara purtatori
Latimea zonei golite Ld region creste cu valoarea tensiune aplicata

Leff = L Ld
Shorter Leff gives more current
Ids increases with Vds
Even in saturation

GND
Source

VDD
Gate

VDD
Drain
Depletion Region
Width: Ld

n
+

L
Leff
p GND

n
+
bulk Si

31

Chan Length Mod I-V

I ds

Vt 1 Vds
2

gs

= coeficientul modulatiei L-canal

NU este L feature size
Determinat empiric pt a se corela cu
caracteristica I-V

32

Threshold Voltage Effects

Vt este Vgs pentru care canalul intra in inversie
Modelul ideal presupunea Vt constant
Depinde (in mica masura) de aproape toti
parametrii:
Body voltage: Body Effect
Drain voltage: Drain-Induced Barrier Lowering
Channel length: Short Channel Effect

33

Body Effect
Body este al patrulea terminal al transistorului

Vsb influenteaza sarcina necesara inintrarii in inversie a canalului

Cresterea Vs sau descresterea Vb duce la cresterea Vt

Vt Vt 0

s 2vT ln

NA
ni

s Vsb s

s = surface potential at threshold

Depinde de doping level NA

Si de intrinsic carrier concentration ni
= body effect coefficient (coeficientul efectului de substrat)

tox

ox

2q si N A

2q si N A
Cox

34

Body Effect Cont.

For small source-to-body voltage, treat as linear
(Ex.2.5)

35

DIBL
Campul electric dispre D afecteaza canalul
Efectul este mai pronuntat la tranzistoare cu canal
scurt
Drain-Induced Barrier Lowering
VVV
Vd afecteaza si Vt
ttds

Vt Vt Vds
High drain voltage causes current to increase.

36

Short Channel Effect

In tranzistoare cu canal scurt, regiunile golite S/D se
extind, micsorand canalul efectiv
Are un impact direct asupra cantitatii de sarcina
necesara inversiei canalului
Prin urmare Vt devine functie de lungimea
canalului
Efectul canalului scurt: Vt creste cu L

Some processes exhibit a reverse short channel effect in which Vt decreases with L

37

Leakage
What about current in cutoff?
Simulated results
What differs?
Current doesnt
go to 0 in cutoff

38

Leakage Sources
Subthreshold conduction Conductia sub-prag
Transistors cant abruptly turn ON or OFF
Dominant source in contemporary transistors
Gate leakage
Tunneling through ultrathin gate dielectric
Junction leakage
Curentul dat de jonctiunile (diodele) PN polarizate
invers

39

Subthreshold Leakage
Subthreshold leakage exponential with Vgs
Vgs Vt 0 Vds k Vsb

I ds I ds 0 e

nvT

Vds

1 e vT

n is process dependent
typically 1.3-1.7
Rewrite relative to Ioff on log scale

S 100 mV/decade @ room temperature

40

Gate Leakage
Carriers tunnel thorough very thin gate oxides
Exponentially sensitive to tox and VDD

A and B are tech constants

Greater for electrons
So nMOS gates leak more
Negligible for older processes (tox > 20 )
Critically important at 65 nm and below (tox 10.5 )
From [Song01]

41

Junction Leakage
Reverse-biased p-n junctions have some leakage
Ordinary diode leakage
Band-to-band tunneling (BTBT)
Gate-induced drain leakage (GIDL)

42

Diode Leakage
Reverse-biased p-n junctions have some leakage
VvD

T
I D I S e 1

At any significant negative diode voltage, ID = -Is

Is depends on doping levels
And area and perimeter of diffusion regions
Typically < 1 fA/m2 (negligible)

43

Band-to-Band Tunneling
Tunneling across heavily doped p-n junctions
Especially sidewall between drain & channel
when halo doping is used to increase Vt
Increases junction leakage to significant levels

Xj: sidewall junction depth

Eg: bandgap voltage
A, B: tech constants
44

Gate-Induced Drain Leakage

Occurs at overlap between gate and drain
Most pronounced when drain is at VDD, gate is at
a negative voltage
Thwarts efforts to reduce subthreshold leakage
using a negative gate voltage

45

Temperature Sensitivity
Increasing temperature
Reduces mobility
Reduces Vt
ION decreases with temperature
IOFF increases with temperature
I ds
increasing
temperature

Vgs

46

So What?
So what if transistors are not ideal?
They still behave like switches.
But these effects matter for
Supply voltage choice
Logical effort
Quiescent power consumption
Pass transistors
Temperature of operation

47

Parameter Variation

fast

Transistors have uncertainty in parameters

Process: Leff, Vt, tox of nMOS and pMOS
Vary around typical (T) values
Fast (F)
Leff: short
Vt: low
tox: thin
Slow (S): opposite
nMOS
Not all parameters are independent
for nMOS and pMOS

FF

pMOS

SF

TT

FS

slow

SS

slow

fast

48

Environmental Variation
VDD and T also vary in time and space
Fast:
VDD: high
T: low
Corner

Voltage

Temperature

1.98

0C

1.8

70 C

1.62

125 C

49

Process Corners
Process corners describe worst case variations
If a design works in all corners, it will probably
work for any variation.
Describe corner with four letters (T, F, S)
nMOS speed
pMOS speed
Voltage
Temperature

50

Important Corners
Some critical simulation corners include

Purpose

nMOS

pMOS

VDD

Temp

Cycle time

Power

Subthreshold
leakage

51

DC&Transient Response

Pass Transistors
DC Response
Logic Levels and Noise Margins
Transient Response
RC Delay Models
Delay Estimation

52

Pass Transistors
We have assumed source is grounded
What if source > 0?
VDD
e.g. pass transistor passing VDD
VDD
Vg = VDD
Daca Vs > VDD-Vt, Vgs < Vt
Transitorul va intra in starea OFF
nMOS pass transistors pull no higher than VDD-Vtn
Called a degraded 1
Approach degraded value slowly (low Ids)
pMOS pass transistors pull no lower than Vtp
Transmission gates are needed to pass both 0 and 1
53

Pass Transistor Ckts

54

DC Response
DC Response: Vout vs. Vin for a gate
Ex: Inverter
When Vin = 0
->
Vout = VDD
When Vin = VDD
->
Vout = 0
VDD
In between, Vout depends on
Idsp
transistor size and current
Vin
Vout
By KCL, must settle such that
Idsn
Idsn = |Idsp|
We could solve equations
But graphical solution gives more insight
55

Transistor Operation
Current depends on region of transistor behavior
For what Vin and Vout are nMOS and pMOS in
Cutoff?
Linear?
Saturation?

56

nMOS Operation
Cutoff
Vgsn < Vtn
Vin < Vtn

Linear
Vgsn > Vtn
Vin > Vtn
Vdsn < Vgsn Vtn
Vout < Vin - Vtn

Saturated
Vgsn > Vtn
Vin > Vtn
Vdsn > Vgsn Vtn
Vout > Vin - Vtn
VDD

Vgsn = Vin
Vdsn = Vout

Vin

Idsp

Vout

Idsn
57

pMOS Operation
Cutoff
Vgsp > Vtp
Vin > VDD + Vtp

Linear
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp > Vgsp Vtp
Vout > Vin - Vtp

Saturated
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp < Vgsp Vtp
Vout < Vin - Vtp
VDD

Vgsp = Vin - VDD

Vdsp = Vout - VDD

Vtp < 0

Vin

Idsp

Vout

Idsn
58

I-V Characteristics
Make pMOS wider than nMOS such that n = p

59

Current vs. Vout, Vin

Idsn, |Idsp|

Vin0

Vin5

Vin1

Vin4

Vin2

Vin3

Vin3
Vin4

Vin2
Vin1
Vout

VDD
60

Load Line Analysis

For a given Vin:
Plot Idsn, Idsp vs. Vout
Vout must be where |currents| are equal in

Idsn, |Idsp|

Vin0

Vin5

Vin1

Vin4

Vin2

Vin3

Vin3
Vin4

Vin2
Vin1
Vout

VDD
Vin

Idsp

Vout

Idsn

VDD
61

Load Line Analysis

Vin = 0V
0.4V
0.6V
0.8V
.2V
DD DD
DD

Idsn
|
dsn, |Idsp
dsp

Vin0

Vin5
in5

Vin1

Vin4

Vin2

Vin3

Vin3
Vin4

Vin2
Vin1
in0
Vout
out

VDD
DD

62

DC Transfer Curve
Transcribe points onto Vin vs. Vout plot

Vin0

Vin5

Vin1

Vin4

Vin2

Vin3

Vin3
Vin4

Vin2
Vin1
Vout

VDD

VDD

Vin0

Vin1

Vin2
B

A
Vout

C
Vin3
D
0

Vtn

VDD/2

Vin

Vin4
E
VDD+Vtp

Vin5
VDD

63

Operating Regions
Revisit transistor operating regions

Region

nMOS

pMOS

Cutoff

Linear

Saturation

Linear

Saturation

Saturation

Linear

Saturation

Linear

Cutoff

VDD
A

Vout

D
0

Vtn

VDD/2

Vin

E
VDD+Vtp

VDD

64

Beta Ratio
If p / n 1, switching point will move from VDD/2
Called skewed gate
Other gates: collapse into equivalent inverter
VDD
p
10
n

Vout

2
1
0.5

p
0.1
n

0
Vin

VDD

65

Noise Margins
How much noise can a gate input see before it does
not recognize the input?

Output Characteristics
Logical High
Output Range

VDD

Input Characteristics

NMH
VIH
VIL
Logical Low
Output Range

Logical High
Input Range

VOH

NML
VOL

Indeterminate
Region
Logical Low
Input Range

GND
66

Logic Levels
To maximize noise margins, select logic levels at
unity gain point of DC transfer characteristic
Vout
Unity Gain Points
Slope = -1

VDD
VOH

p/ n > 1
Vin

VOL
0
Vtn

VIL VIH VDD- VDD

|Vtp|

Vout

Vin

67

Transient Response
DC analysis tells us Vout if Vin is constant
Transient analysis tells us Vout(t) if Vin(t) changes
Requires solving differential equations
Input is usually considered to be a step or ramp
From 0 to VDD or vice versa

68

Inverter Step Response

Ex: find step response of inverter driving load cap

Vin (t ) u(t t0 )VDD

Vin(t)

Vout (t t0 ) VDD

Vout(t)
Cload

dVout (t )
I dsn (t )

dt
Cload

I dsn (t )
V
V

DD
t
2

VDD Vt Vout (t )
2

Idsn(t)
Vin(t)

t t0
Vout VDD Vt
V (t ) V V V
out
out
DD
t

Vout(t)
t0

69

Delay Definitions
tpdr: rising propagation delay
From input to rising output
crossing VDD/2
tpdf: falling propagation delay
From input to falling output
crossing VDD/2
tpd: average propagation delay
tpd = (tpdr + tpdf)/2
tr: rise time
From output crossing 0.2
VDD to 0.8 VDD
tf: fall time
From output crossing 0.8
VDD to 0.2 VDD
70

Delay Definitions
tcdr: rising contamination delay
From input to rising output crossing VDD/2
tcdf: falling contamination delay
From input to falling output crossing VDD/2
tcd: average contamination delay
tpd = (tcdr + tcdf)/2

71

Simulated Inverter Delay

Solving differential equations by hand is too hard
SPICE simulator solves the equations numerically
Uses more accurate I-V models too!
But simulations take time to write, may hide insight
2.0

1.5

1.0
(V)

Vin

tpdf = 66ps

tpdr = 83ps

Vout

0.5

0.0
0.0

200p

400p

600p

800p

1n

t(s)

72

Delay Estimation
We would like to be able to easily estimate delay
Not as accurate as simulation
But easier to ask What if?
The step response usually looks like a 1st order RC
response with a decaying exponential.
Use RC delay models to estimate delay
C = total capacitance on output node
Use effective resistance R
So that tpd = RC
Characterize transistors by finding their effective R
Depends on average current as gate switches
73

Effective Resistance
Shockley models have limited value
Not accurate enough for modern transistors
Too complicated for much hand analysis
Simplification: treat transistor as resistor
Replace Ids(Vds, Vgs) with effective resistance R
Ids = Vds/R
R averaged across switching of digital gate
Too inaccurate to predict current at any given time
But good enough to predict RC delay

74

RC Delay Model
Use equivalent circuits for MOS transistors
Ideal switch + capacitance and ON resistance
Unit nMOS has resistance R, capacitance C
Unit pMOS has resistance 2R, capacitance C
Capacitance proportional to width
Resistance inversely proportional to width
d

d
k
s

s
kC

R/k
g

kC

kC
s

d
k
s

kC
2R/k

kC
kC
d
75

RC Values
Capacitance
C = Cg = Cs = Cd = 2 fF/m of gate width in 0.6 m
Gradually decline to 1 fF/m in 65 nm
Resistance
R 10 Km in 0.6 m process
Improves with shorter channel lengths
1.25 Km in 65 nm process
Unit transistors
May refer to minimum contacted device (4/2 )
Or maybe 1 m wide device
Doesnt matter as long as you are consistent
76

Inverter Delay Estimate

Estimate the delay of a fanout-of-1 inverter
2C
R

2 Y

2C

2C

2C

2C

Y
R

R
C

C
C

d = 6RC
77

Delay Model Comparison

78

Example: 3-input NAND

Sketch a 3-input NAND with transistor widths chosen to
achieve effective rise and fall resistances equal to a unit
inverter (R).

2
3
3
3

79

3-input NAND Caps

Annotate the 3-input NAND gate with gate and diffusion
capacitance.
2C
2

2C
2C

2C
2

2C
2C
3C
3C
3C

2C
2

3
3
3

2C
2C
3C
3C
3C
3C

80

Elmore Delay
ON transistors look like resistors
Pullup or pulldown network modeled as RC ladder
Elmore delay of RC ladder

t pd

Ri to sourceCi

nodes i

R1C1 R1 R2 C2 ... R1 R2 ... RN C N

R1

R2

R3

C1

C2

RN
C3

CN

81

Example: 3-input NAND

Estimate worst-case rising and falling delay of 3-input NAND
driving h identical gates.
2

9C
5hC
n2
3C

3 n1
3

t pdr 9 5h RC

3C

t pdf 3C R3 3C R3 R3 9 5h C R3 R3 R3
12 5h RC

82

Delay Components
Delay has two parts
Parasitic delay
9 or 12 RC
Independent of load
Effort delay
5h RC
Proportional to load capacitance

83

Contamination Delay
Best-case (contamination) delay can be substantially less than
propagation delay.
Ex: If all three inputs fall simultaneously
2

9C
5hC
n2
3C

3 n1
3

3C

tcdr

5
R
9 5h C 3 h RC
3
3

84

Diffusion Capacitance
We assumed contacted diffusion on every s / d.
Good layout minimizes diffusion area
Ex: NAND3 layout shares one diffusion contact
Reduces output capacitance by 2C
Merged uncontacted diffusion might help too
Shared
Contacted
Diffusion

2C

2C
Isolated
Contacted
Diffusion

Merged
Uncontacted
Diffusion

2
3
3

3C 3C 3C

7C
3C
3C

85

Layout Comparison
Which layout is better?
VDD

VDD

GND

GND
86