ECE 546 - VLSI Systems Design

Lecture 5: Latchup,
Analytical Transient, Inverter Sizing
Fall 2012
W. Rhett Davis
NC State University
with significant material from Rabaey, Chandrakasan, and Nikoli
W. Rhett Davis

NC State University

Slide 1

ECE 546

Fall 2012

Announcements

HW#2 Due Tuesday

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Please do not e-mail assignments

W. Rhett Davis

NC State University

Slide 2

ECE 546

Fall 2012

Summary of Last Lecture

What are the five capacitances for a

MOSFET and how can we calculate
them?

How do you extract AS, AD, PS, & PD

values from the layout?

W. Rhett Davis

NC State University

Slide 3

ECE 546

Fall 2012

Todays Lecture

Latchup (3.3.3)

Analytical Transient (5.4 5.4.1)

Inverter Sizing (5.4.3)

W. Rhett Davis

NC State University

Slide 4

ECE 546

Fall 2012

Why are well-contacts necessary?

W. Rhett Davis

NC State University

Slide 5

ECE 546

Fall 2012

CMOS Latchup

Caused by parasitic BJTs in positive feedback

High currents can burn out a transistor
Primary way to prevent this is to minimize Rnwell & Rpsubs
by putting substrate contacts close to source contacts

W. Rhett Davis

NC State University

Slide 6

ECE 546

Fall 2012

What We Will Require in Our Class

Latchup is much less of a problem in

todays processes

Still see a lot of overdesigned layout with

overkill in substrate contacts (doesnt hurt
but might waste area)

I will require one well contact

per active area

W. Rhett Davis

NC State University

Slide 7

ECE 546

Fall 2012

Todays Lecture

Latchup (3.3.3)

Analytical Transient (5.4 5.4.1)

Inverter Sizing (5.4.3)

W. Rhett Davis

NC State University

Slide 8

ECE 546

Fall 2012

Analytical Transient
VDD

VDD

M2

M4

Vin

M2
Vout

Vin
M1

M3

M1
CL

GND

GND

Need to get circuit in the form of tp=ReqCL

Follows example 5.4 in text

W. Rhett Davis

NC State University

Slide 9

ECE 546

Fall 2012

Parasitic Capacitances
G

CGS

CGD
D

CGB

CSB

CDB

W. Rhett Davis

NC State University

Slide 10

ECE 546

Fall 2012

Computing Parasitic Capacitances

Operation
Region

CGB

CGS

CGD

Cutoff

CoxWL

COW

COW

Resistive

(1/2)CoxWL + COW

(1/2)CoxWL + COW

Saturation

(2/3)CoxWL + COW

COW

CDB = Keq AD Cj + KeqSW PD CjSW

CSB = Keq AS Cj + KeqSW PS CjSW

W. Rhett Davis

NC State University

Slide 11

ECE 546

Fall 2012

Which Capacitances Matter?

GS4
GB4

GD12

DB2

GD34
DB1
GS3
GB3

Are there any others?

W. Rhett Davis

NC State University

Slide 12

ECE 546

Fall 2012

Simplifications
1) Assume parallel capacitors can be added into one
capacitor

Allows us to combine CGD1 & CGD2

2) Assume that a capacitor tied to VDD is equivalent to a

capacitor tied to GND (if you work through the
differential equation, youll find that this doesnt change
the value of tp).

Allows us to combine CDB1 & CDB2

W. Rhett Davis

NC State University

Slide 13

ECE 546

Fall 2012

Simplifications
3) Assume that second inverter doesnt switch, and Vout
of second inverter is effectively GND.

Allows us to combine CGB3, CGS3, & CGD3 into CG3

Allows us to combine CGB4, CGS4, & CGD4 into CG4

4) Assume CG3 = CG4 = COXWL + 2COW

W. Rhett Davis

Technically, one transistor will be in cutoff, and the other in

saturation, so there will be a difference of COXWL and
(2/3)COXWL, but this is complicated, and the error from
ignoring it small.

NC State University

Slide 14

ECE 546

Fall 2012

Simplifications
5) Use Miller Effect for CGD1 & CGD2

A = gain
Assume A = -1
Therefore, CGD1 referenced to GND is 2CGD1

W. Rhett Davis

NC State University

Slide 15

ECE 546

Fall 2012

Summary of Simplifications
VDD

CGS4,
CGB4
M2
CGD12

CDB2

M4
CGD34

CDB1
M1

M2
Vout

Vin

M3

M1
CL

CGS3,
CGB3

GND

CL = 2 CGD1,2 + CDB1,2 + CG3,4

W. Rhett Davis

NC State University

Slide 16

ECE 546

Fall 2012

Tabulation of Results
Capacitance

Formula

HL vs. LH

2 CGD1

2 COnW1

same

2 CGD2
CDB1
CDB2
CG3
CG4
W. Rhett Davis

NC State University

Slide 17

ECE 546

Fall 2012

Todays Lecture

Latchup (3.3.3)

Analytical Transient (5.4 5.4.1)

Inverter Sizing (5.4.3)

W. Rhett Davis

NC State University

Slide 18

ECE 546

Fall 2012

Inverter Sizing
3.8

x 10

-11

(for fixed load)

3.6
3.4

t (sec)

3.2
3
2.8

Self-loading effect:
Intrinsic capacitances
dominate

2.6
2.4
2.2
2

W. Rhett Davis

8
S

NC State University

10

12

14

Slide 19

ECE 546

Fall 2012

NMOS/PMOS ratio in 250 nm

5

x 10

-11

tpHL

tpLH

= Wp/Wn

This curve
for 0.25 m

tp
4

t (sec)

4.5

3.5

1.5

2.5

3.5

4.5

min tp
W. Rhett Davis

equal tp
NC State University

Slide 20

ECE 546

Fall 2012

NMOS/PMOS ratio in 45 nm

Our process:
Min tp for
2.3
Equal tp for
3.1

min tp
W. Rhett Davis

equal tp
NC State University

Slide 21

ECE 546

Fall 2012

Which Sizing is Better?

Sizing for min. tp = sizing for min. avg. delay

Sizing for equal tp = sizing for min. worst case

delay

Which is better? Why?

W. Rhett Davis

NC State University

Slide 22

ECE 546

Fall 2012

Summary

Learned how to extract AS, AD, PS, & PD values

from the layout.

Learned how to compute the effective load

capacitance (CL) for an inverter loaded with an
identical inverter.

Learned how to choose = Wp/Wn for a single

Inverter
Min tp for 1.5
Equal tp for 3.5

W. Rhett Davis

NC State University

Slide 23

ECE 546

Fall 2012